KR20080071815A - Semiconductor memory device capable of reducing static noise margin - Google Patents

Abstract

A semiconductor memory device is provided to reduce static noise margin by using one MOS transistor in a read port of a memory cell included in the semiconductor memory device. A latch(210) includes an input port and an output port. A read port(220) is connect to the output port and is switched on the basis of the value stored in the latch, and includes a first pass gate implemented with one MOS(Metal Oxide Semiconductor), and determines the stored value according to the switched state of the first pass gate. A write port(230) inputs the new value to the input port on the basis of a second selection signal.

Description

Semiconductor memory devices that can reduce static noise margins {SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING STATIC NOISE MARGIN}

1 is a circuit diagram showing the structure of a memory cell of a conventional SRAM.

2 is a circuit diagram illustrating a configuration of a memory cell included in a semiconductor memory device according to an embodiment of the present invention.

3 is a circuit diagram illustrating a process of reading data stored in a memory cell, and FIG. 4 is a timing diagram illustrating a process of reading data stored in a memory cell.

FIG. 5 is a circuit diagram illustrating a process of storing data in a memory cell, and FIG. 6 is a timing diagram illustrating a process of storing data in a memory cell.

7 is a circuit diagram illustrating a configuration of a memory cell included in a semiconductor memory device according to another exemplary embodiment of the present invention.

8 is a circuit diagram illustrating a configuration of a memory cell included in a semiconductor memory device according to another embodiment of the present invention.

9 is a circuit diagram illustrating a configuration of a memory cell included in a semiconductor memory device according to another exemplary embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

210: Latch 220: Read Port

230: write port

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of reducing static noise margin.

Semiconductor memory devices are largely classified into static random access memory (SRAM) for storing data using latches and dynamic random access memory (DRAM) for storing data using capacitors.

1 is a circuit diagram showing the structure of a memory cell of a conventional SRAM.

Referring to FIG. 1, a memory cell 100 of an SRAM includes a latch 110, a first pass gate 120, and a second pass gate 130.

The latch 110 may be implemented as two inverters, and the first and second pull-up circuits 112 and 114 and the first and second pull-down circuits (CMOS) may be implemented by a complementary metal oxide semiconductor (CMOS) process. 116, 118).

The first pull-up circuit 112 is connected between the power supply voltage VDD and the first node N1, and the first pull-down circuit 116 is connected to the first node N1 and the ground voltage VSS. In addition, the gates of the first pull-up and pull-down circuits 112 and 116 are connected to the second node N2.

The second pull-up circuit 114 is connected between the power supply voltage VDD and the second node N2, and the second pull-down circuit 118 is connected to the second node N2 and the ground voltage VSS. In addition, the gates of the second pull-up and pull-down circuits 114 and 118 are connected to the first node N1.

The first pass gate 120 is connected between the first bit line BL1 and the first node N1, and the second pass gate 130 has a second bit having a complementary relationship with the first bit line BL1. It is connected between the line BL2 and the second node N2. In addition, the gates of the first and second pass gates 120 and 130 are connected to the word line WL.

With the development of the process technology, the size of the memory cells of the SRAM shown in FIG. 1 is decreasing, and thus problems related to cell stability such as static noise margin (SNM) occur. That is, as the size of the memory cell of the SRAM decreases, there is a problem that a voltage difference between two inverters included in the latch of the memory cell of the SRAM decreases.

In order to solve the problem of cell stability, there is a method of increasing the number of devices (eg, MOS circuits, metal oxide semiconductors) included in the memory cells of the SRAM, but this method reduces the density of the SRAM. This happens.

Accordingly, there is a need for a semiconductor memory device capable of solving problems related to cell stability such as static noise margin (SNM) while suppressing a decrease in the density of SRAM.

An object of the present invention is to provide a semiconductor memory device that can reduce the static noise margin even when using only one MOS for the read port of the memory cell included in the semiconductor memory device to solve the problems of the prior art.

In order to achieve the above object, a semiconductor memory device capable of reducing the static noise margin of the present invention includes a latch including an input port and an output port, connected to the output port, and switched based on a value stored in the latch and having one MOS. A read port and a second selection signal including only a first pass gate implemented by a metal oxide semiconductor (MOS) and determining the stored value according to a switched state of the first pass gate when a first selection signal is input; It includes a write port for inputting the new value to the input port based on. For example, the semiconductor memory device may correspond to a static random access memory (SRAM).

The read port applies the first select signal to a read word line and outputs the first select signal to a read bit line when the first pass gate is turned on, and the first pass gate is turned off. In this case, the first selection signal may not be output to the read bit line.

For example, the read port is implemented with one N-channel metal oxide semiconductor (NMOS) connected to a source connected to the read bit line, a drain connected to the read word line, and a gate connected to the output port. The first pass gate may be included.

The read port discharges the source of the NMOS so that the source of the NMOS corresponds to a low voltage, receives the first selection signal to the drain of the NMOS, and according to the stored value applied to the gate of the NMOS. The first selection signal may be output to the source of the NMOS.

In example embodiments, the write port includes a second pass gate connected to the input port and switched based on the second selection signal, and through the write bit line when the second pass gate is turned on. The new value received can be written to the input port.

The write port may include a first NMOS (N-channel metal oxide semiconductor) connected to a source connected to the input port, a drain connected to the write bit line, and a gate connected to the write word line. It may include a second pass gate.

The write port discharges the source of the first NMOS so that the source of the first NMOS corresponds to a low voltage, receives the second selection signal applied to the gate of the first NMOS, and receives the first NMOS. The new value input to the source of may be output to the drain of the first NMOS.

The write port further includes a third pass gate connected to the output port and switched based on the second selection signal, and when the third pass gate is turned on, the write port received through the complementary write bit line. A value complementary to the new value can be entered into the output port.

According to another embodiment, the write port is connected to the complementary write bit line, the drain is connected to the output port and the gate is connected to the second word NMOS (NMOS, N- Channel metal oxide semiconductor) may further include the third pass gate.

The write port discharges the source of the second NMOS so that the source of the second NMOS corresponds to a low voltage, receives the second selection signal applied to the gate of the second NMOS, and receives the second NMOS. The complementary value input to the source of may be output to the drain of the second NMOS.

A semiconductor memory device capable of reducing the static noise margin of the present invention for achieving the above another object is a latch including an input port and an output port, connected to the output port and switched based on the value stored in the latch It includes only a first pass gate implemented by a metal oxide semiconductor (MOS), and when the selection signal is input, the stored value is determined according to the switched state of the first pass gate and the stored value to the input port A read port for inputting and a write port for inputting a new value to the input port based on the selection signal. For example, the semiconductor memory device may correspond to a static random access memory (SRAM).

The read port applies the select signal to a word line to output the select signal to a read bit line when the first pass gate is turned on, and to output the select signal when the first pass gate is turned off. A value of the read bit line may be input to the input port so that the read bit line is not output to the read bit line and the stored value is not changed.

The read port may include a source connected to the read bit line, a drain connected to the read word line, and a gate connected to the output port, the N-channel metal oxide semiconductor (NMOS). It may include a one pass gate.

The read port discharges the source of the NMOS so that the source of the NMOS corresponds to a low voltage, receives the first selection signal to the drain of the NMOS, and according to the stored value applied to the gate of the NMOS. The first selection signal may be output to the source of the NMOS.

In example embodiments, the write port includes a second pass gate connected to the input port and switched based on the selection signal, and received through a write bit line when the second pass gate is turned on. The new value can be written to the input port.

According to one embodiment, the write port is connected to the input port, the source is connected to the write bit line, the drain is connected to the first word line (NMOS, N-channel Metal Oxide) And a second pass gate implemented as a semiconductor.

The write port discharges the source of the first NMOS so that the source of the first NMOS corresponds to a low voltage, receives the selection signal applied to the gate of the first NMOS, and the source of the first NMOS. The new value input to may be output to the drain of the first NMOS.

The write port further includes a third pass gate connected to the output port and switched based on the selection signal, and when the third pass gate is turned on, the new input received through the complementary write bit line. A value complementary to the value can be entered into the output port.

According to another embodiment, the write port is connected to the complementary write bit line, the drain is connected to the output port and the gate is connected to the second word NMOS (NMOS, N- Channel metal oxide semiconductor) may further include the third pass gate.

The write port discharges the source of the second NMOS so that the source of the second NMOS corresponds to a low voltage, receives the selection signal applied to the gate of the second NMOS, and the source of the second NMOS. The complementary value input to may be output to the drain of the second NMOS.

In the present invention, since the read port of the memory cell included in the semiconductor memory device includes only one Morse, the Morse is switched based on the stored value, thereby reducing the static noise margin.

In addition, in the present invention, even though only one Morse is used for the read port of the memory cell included in the semiconductor memory device, the read port and the write port of the memory cell can be accessed.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

On the other hand, when an embodiment is otherwise implemented, a function or operation specified in a specific block may occur out of the order specified in the flowchart. For example, two consecutive blocks may actually be performed substantially simultaneously, and the blocks may be performed upside down depending on the function or operation involved.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a circuit diagram illustrating a configuration of a memory cell included in a semiconductor memory device according to an embodiment of the present invention.

2, the memory cell 200 includes a latch 210, a read port 220, and a write port 230.

The latch 210 may be implemented with two inverters, and the first and second pull-up circuits 212 and 214 and the first and second pull-down circuits (CMOS) may be implemented by a complementary metal oxide semiconductor (CMOS) process. 216, 218).

The first pull-up circuit 212 is connected between the power supply voltage VDD and the input port N1, and the first pull-down circuit 216 is connected to the input port N1 and the ground voltage VSS. In addition, the gates of the first pull-up and pull-down circuits 212 and 216 are connected to the output port N2.

The second pull-up circuit 214 is connected between the power supply voltage VDD and the output port N2, and the second pull-down circuit 218 is connected to the output port N2 and the ground voltage VSS. The gates of the second pull up and pull down circuits 214, 218 are also connected to the input port N1.

The read port 220 includes only the first pass gate PG1 connected to the output port N2 and switched based on a value stored in the latch 210 and implemented as one metal oxide semiconductor (MOS). When a first selection signal (eg, a read wordline signal) is input, a value stored in the latch 210 is determined according to the switched state of the first pass gate PG1. In other words, the read port 220 may be implemented as a single MOS to reduce the static noise margin without reducing the density of the memory cell 200.

The read port 220 refers to a circuit integrated in a circuit, such as a latch 210 that stores data, and does not include all peripheral circuits necessary for reading data stored in the latch 210.

The write port 230 inputs a new value to the input port N1 for storing in the latch 210 based on the second selection signal (eg, a write wordline signal).

The write port 230 refers to a circuit integrated together in a circuit such as a latch 210 that stores data, and does not include all peripheral circuits necessary for writing data stored in the latch 210.

Hereinafter, a method of operating read and write operations of the semiconductor memory device will be described with reference to FIGS. 3 to 6.

3 is a circuit diagram illustrating a process of reading data stored in a memory cell, and FIG. 4 is a timing diagram illustrating a process of reading data stored in a memory cell.

When the first pass gate PG1 is turned on by applying the first select signal to the read word line, the read port 220 outputs the first select signal to the read bit line, and the first pass gate PG1 When turned off, the first select signal is not output to the read bit line.

In the first pass gate PG1, one NMOS (N-channel Metal Oxide Semiconductor) (NMOS) source connected to the read bitline, drain connected to the read wordline, and gate connected to the output port N2. It may be implemented as (PG1).

Hereinafter, a process of reading data stored in the memory cell will be described.

The read bit line pre-discharge signal, which is used to indicate a process of reading data stored in the memory cell, of the NMOS PG1 included in the first pass gate PG1 by a peripheral circuit. The timing for discharging the source is not a signal actually transmitted to the memory cell 200.

The source of NMOS PG1 is discharged so that the source of NMOS PG1 corresponds to a low voltage by a read bitline pre-discharge signal signal (step S410).

The read port 200 receives a first selection signal (eg, a read wordline signal) to the drain of the NMOS PG1 (step S420).

The read port 200 outputs the first selection signal to the source of the NMOS PG1 according to the stored value of the latch 210 applied to the gate of the NMOS PG1 (steps S430 and S440).

FIG. 5 is a circuit diagram illustrating a process of storing data in a memory cell, and FIG. 6 is a timing diagram illustrating a process of storing data in a memory cell.

The write port 230 includes a second pass gate PG2 connected to the input port N1 and switched based on the second selection signal, and the write bit line when the second pass gate PG2 is turned on. Write new value inputted through through to input port (N1).

In the second pass gate PG2, one NMOS (N-channel Metal Oxide Semiconductor) (NMOS) source connected to input port N1, drain connected to write bit line, and gate connected to write word line (PG2) can be implemented.

A process of writing new data to a memory cell will now be described.

The write bit line pre-discharge signal, which is used to indicate a process of writing new data to the memory cell, is used to determine the NMOS PG2 included in the second pass gate PG2 by a peripheral circuit. The timing for discharging the source is not a signal actually transmitted to the memory cell 200.

By the write bit line pre-discharge signal, the source of NMOS PG2 is discharged so that the source of NMOS PG2 corresponds to the low voltage (step S610).

The write port 230 receives a second selection signal applied to the gate of the NMOS PG2 (step S620).

The write port 230 outputs a new value input to the source of the NMOS PG2 to the drain of the NMOS PG2 (steps S630 and S640).

7 is a circuit diagram illustrating a configuration of a memory cell included in a semiconductor memory device according to another exemplary embodiment of the present invention.

The operation of the memory cell 700 shown in FIG. 7 is substantially similar to the operation of the memory cell 200 shown in FIG. 2, but the configuration of the write port 730 is different from that of the write port 230 of FIG. 2.

The write port 730 further includes a third pass gate PG3 connected to the output port N2 and switched based on the second selection signal, and complementary when the third pass gate PG3 is turned on. A value input through the write bit line and having a complementary relationship with the new value is input to the output port N2. The write port 730 shown in FIG. 7 includes one more Morse circuit compared to the write port 230 shown in FIG. 2, but has a faster write speed.

In a third pass gate PG3, one source is connected to the complementary write bit line, the drain is connected to the output port, and the gate is connected to the write word line. (PG3) can be implemented.

The write port 730 discharges the source of the NMOS PG3 so that the source of the NMOS PG3 corresponds to a low voltage, receives a second selection signal applied to the gate of the NMOS PG3, and receives the NMOS PG3. The complementary value input to the source of) is output to the drain of NMOS PG3.

8 is a circuit diagram illustrating a configuration of a memory cell included in a semiconductor memory device according to another embodiment of the present invention.

The operation of the memory cell 800 shown in FIG. 8 is substantially similar to the operation of the memory cell 200 shown in FIG. 2, but the configuration of the read port 820 and the write port 830 is the read port 820 of FIG. 2. ) And write port 830.

Referring to FIG. 8, the memory cell 800 includes a latch 210, a read port 820, and a write port 830.

The read port 820 is connected to the output port N2 and is switched based on the value stored in the latch 210 and only the first pass gate PG1 implemented by one metal oxide semiconductor (MOS) PG1 is provided. If the selection signal is input, the stored value is determined according to the switched state of the first pass gate PG1, and the determined stored value is input to the input port N1. The reason why the value output from the read port 820 is input again through the input port N1 is because the read port 820 and the write port 830 share one selection line.

When the first pass gate PG1 is turned on by applying the select signal to the word line, the read port 820 outputs the select signal to the read bit line and when the first pass gate PG1 is turned off. The select signal is not output to the read bit line, and the value of the read bit line is input to the input port N1 so that the stored value is not changed.

In a first pass gate PG1, a source is connected to the read bit line, a drain is connected to a read word line, and a gate is connected to an output port N2. (PG1) can be implemented.

The read port 820 discharges the source of NMOS PG1 so that the source of NMOS PG1 corresponds to a low voltage, receives a first selection signal to the drain of NMOS PG1, and The first select signal is output to the source of NMOS PG1 according to the stored value applied to the gate.

The write port 830 inputs a new value to the input port N1 based on the selection signal.

The write port 830 includes a second pass gate PG2 connected to the input port N1 and switched based on the selection signal, and through the write bit line when the second pass gate PG2 is turned on. Write new input value to input port (N1).

In the second pass gate PG2, one NMOS (N-channel Metal Oxide Semiconductor) (NMOS) source connected to input port N1, drain connected to write bit line, and gate connected to write word line (PG2) can be implemented.

The write port 830 discharges the source of the NMOS PG2 so that the source of the NMOS PG2 corresponds to a low voltage, receives a selection signal applied to the gate of the NMOS PG2, and receives the NMOS PG2. The new value input to the source of is output to the drain of the NMOS PG2.

9 is a circuit diagram illustrating a configuration of a memory cell included in a semiconductor memory device according to another exemplary embodiment of the present invention.

The operation of the memory cell 900 shown in FIG. 9 is substantially similar to that of the memory cell 800 shown in FIG. 8, but the configuration of the write port 930 is different from that of the write port 830 of FIG. 8.

The write port 930 further includes a third pass gate PG3 connected to the output port N2 and switched based on the selection signal, and the complementary write bit when the third pass gate PG3 is turned on. Input to the output port N2 that is input via a line and has a complementary relationship to the new value.

In the third pass gate PG3, one source of N-channel metal oxide (NMOS) is connected to the complementary write bit line, the drain is connected to the output port N2, and the gate is connected to the write word line. Semiconductor (PG3).

The write port 930 discharges the source of the NMOS PG3 so that the source of the NMOS PG3 corresponds to a low voltage, receives a selection signal applied to the gate of the NMOS PG3, and receives the selection signal of the NMOS PG3. The complementary value input to the source is output to the drain of the NMOS PG3.

2 and 7 to 9 may correspond to memory cells included in static random access memory (SRAM).

As described above, although the read port of the memory cell included in the semiconductor memory device includes only one Morse, the Morse is switched based on the stored value, thereby reducing the static noise margin.

In addition, in the present invention, even though only one Morse is used for the read port of the memory cell included in the semiconductor memory device, the read port and the write port of the memory cell can be accessed.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (22)

A latch including an input port and an output port; Only a first pass gate connected to the output port and switched based on a value stored in the latch and implemented as one metal oxide semiconductor (MOS), wherein the first pass gate is input when a first selection signal is input. A read port for determining the stored value according to a switched state of the read port; And And a write port for inputting the new value to the input port based on a second selection signal. The method of claim 1, wherein the read port When the first pass gate is turned on by applying the first select signal to a read word line, the first select signal is output to a read bit line, and when the first pass gate is turned off, the first select signal is output. And the select signal is not output to the read bit line. The method of claim 1, wherein the read port A source is connected to the read bit line, a drain is connected to the read word line, and a gate includes the first pass gate implemented with one N-channel metal oxide semiconductor (NMOS) connected to the output port. A semiconductor memory device, characterized in that. The method of claim 3, wherein the read port Discharging the source of the NMOS so that the source of the NMOS corresponds to the low voltage, receiving the first selection signal to the drain of the NMOS, and selecting the first according to the stored value applied to the gate of the NMOS. And a signal is output to the source of the NMOS. The method of claim 1, wherein the write port is And a second pass gate connected to the input port and switched based on the second selection signal, and when the second pass gate is turned on, the new value received through a write bit line to the input port. And a semiconductor memory device characterized in that the writing. The method of claim 5, wherein the write port The second pass gate implemented with one first NMOS (N-channel metal oxide semiconductor) connected with a source connected to the input port, a drain connected to the write bitline, and a gate connected to the write wordline. A semiconductor memory device comprising a. The method of claim 6, wherein the write port Discharging the source of the first NMOS so that the source of the first NMOS corresponds to a low voltage, receiving the second selection signal applied to the gate of the first NMOS, and inputting the source of the first NMOS. And outputting the new value to the drain of the first NMOS. The method of claim 5, wherein the write port And a third pass gate connected to the output port and switched based on the second select signal, and when the third pass gate is turned on, complementary to the new value received through the complementary write bit line. And inputting the corrected value to the output port. 9. The apparatus of claim 8, wherein the write port is The third being implemented with one second NMOS (NMOS) connected to the complementary write bit line, the drain connected to the output port, and the gate connected to the write wordline. And a pass gate. 10. The system of claim 9, wherein the write port is The source of the second NMOS is discharged so that the source of the second NMOS corresponds to a low voltage, the second selection signal applied to the gate of the second NMOS is input and input to the source of the second NMOS. And output the complementary value to the drain of the second NMOS. The semiconductor memory device of claim 1, wherein the semiconductor memory device comprises: A semiconductor memory device, characterized in that it corresponds to an SRAM. A latch including an input port and an output port; A first pass gate connected to the output port and switched based on a value stored in the latch and implemented as one metal oxide semiconductor (MOS), and a switch of the first pass gate when a selection signal is input; A read port for determining the stored value according to the read state and inputting the stored value to the input port; And And a write port for inputting a new value to the input port based on the selection signal. The method of claim 12, wherein the read port When the first pass gate is turned on by applying the select signal to a word line, the select signal is output to a read bit line, and when the first pass gate is turned off, the select signal is read by the read bit line. And a value of the read bit line is input to the input port so that the stored value is not outputted to the input port. The method of claim 12, wherein the read port A source is connected to the read bit line, a drain is connected to the read word line, and a gate includes the first pass gate implemented with one N-channel metal oxide semiconductor (NMOS) connected to the output port. A semiconductor memory device, characterized in that. 15. The apparatus of claim 14, wherein the read port is Discharging the source of the NMOS so that the source of the NMOS corresponds to the low voltage, receiving the first selection signal to the drain of the NMOS, and selecting the first according to the stored value applied to the gate of the NMOS. And a signal is output to the source of the NMOS. The method of claim 12, wherein the write port And a second pass gate connected to the input port and switched based on the selection signal, and writing the new value received through the write bit line to the input port when the second pass gate is turned on. Featured semiconductor memory device. The method of claim 16, wherein the write port is The second pass gate implemented with one first NMOS (N-channel metal oxide semiconductor) connected with a source connected to the input port, a drain connected to the write bitline, and a gate connected to the write wordline. A semiconductor memory device comprising a. 18. The system of claim 17, wherein the write port is Discharging the source of the first NMOS so that the source of the first NMOS corresponds to a low voltage, receiving the selection signal applied to the gate of the first NMOS, and being input to the source of the first NMOS And outputting a new value to the drain of the first NMOS. The method of claim 16, wherein the write port is And a third pass gate connected to the output port and switched based on the selection signal, wherein when the third pass gate is turned on, a value complementary to the new value received through the complementary write bit line. Inputting the signal to the output port. 20. The system of claim 19, wherein the write port is The third being implemented with one second NMOS (NMOS) connected to the complementary write bit line, the drain connected to the output port, and the gate connected to the write wordline. And a pass gate. 21. The device of claim 20, wherein the write port is Discharging the source of the second NMOS so that the source of the second NMOS corresponds to a low voltage, receiving the selection signal applied to the gate of the second NMOS, and being input to the source of the second NMOS And a complementary value is output to the drain of the second NMOS. The semiconductor memory device of claim 12, wherein the semiconductor memory device A semiconductor memory device, characterized in that it corresponds to an SRAM.

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