KR20160093456A - Semiconductor Memory Device - Google Patents

Abstract

The present invention relates to a semiconductor memory device comprising an SRAM cell consisting of two cross-coupled inverters each including a load transistor and a driving transistor and two access transistors for allowing access to the respective inverters from bit lines. The SRAM cell includes a conducting transistor connected between the access transistor and the driving transistor. A gate electrode of the conducting transistor is controlled by a columnar auxiliary line. Therefore, the semiconductor memory device of the present invention can improve the stability of an internal data storage device by improving dummy reading stability and reading stability compared to a conventional 6T SRAM cell and improving writing ability with the help of columnar negative voltage bias control.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device, which is improved in dummy read stability and read stability by adding two conduction PMOS transistors to a conventional 6T SRAM cell, And an 8T SRAM cell structure capable of improving the write capability.

Embedded memory is very popular in modern Very Large Scale Integration (VLSI) and system-on-chip (SoC) designs. Current embedded memories are predominantly used with 6-transistor (6T) SRAM predominantly due to their desirable embedded properties, ie, logic CMOS compatibility, high speed, and refresh free operation. 6T SRAM is used in the range of several Kbit to several hundred Mbit, and occupies a large area in the field of modern SoC. However, the scaling technique in CMOS and the increased randomness of transistor characteristics reduce the operational margins of SRAM functions.

As is known, a 6T SRAM cell is constructed by cross-coupling two inverters having access transistors. In such a conventional embedded memory bit cell, the transistor strength ratio must be selected so that both a read static noise margin (SNM) and a write margin (WM) can be obtained, Lt; / RTI > The weak balance of the transistor intensity ratio is severely affected by device variations, which drastically reduce cell operating margins in scaled technologies. Low supply voltages make the problem worse because the threshold voltage variations consume a large portion of the voltage margin. The degradation of bit cell stability increases the Fail-Bit Rate in the embedded SRAM array, thereby limiting the yield of the SoC.

In order to solve this stability problem, various structures of SRAM bit cells have been proposed. For example, a 7T cell structure has been proposed to improve read stability by blocking a pull-down path during a read operation. However, this technology has limited write capability due to a single-ended write operation. .

In addition, 8T, 9T, and 10T SRAM cell structures have been proposed. These techniques divide the data storage device and the data output device so that the read static noise margin (SNM) is equal to the read static noise margin (SNM) in the hold mode, and the write capability is the same as the 6T cell structure have. However, since they have a column-interleaving structure that is inefficient in a write operation, it is difficult to cope with multi-bit errors. Also, these techniques may cause a decrease in access time due to the single-ended read-bit line structure.

Korean Patent Publication No. 2013-0084635 "Skewed SRAM cell" Korean Patent Publication 2008-0071815 "Semiconductor memory device capable of reducing static noise margin" Korean Patent No. 1251676 "SRAM with improved cell stability and method thereof"

The present invention has been proposed in order to solve the problems of the related art, and the present invention proposes a novel SRAM bit cell capable of improving the stability of the embedded data storage device. The present invention utilizes differential swing in the read and write paths. The Column By Column Negative Bias Scheme improves read and dummy read stability as well as write capability. In the present invention, the column interleaving problem does not occur in the write operation, and the bit cell of the present invention can achieve a significant reduction in the standby current due to the stacked leakage path.

According to an aspect of the present invention, there is provided a semiconductor memory device including two access transistors cross-coupled to each other, the two inverters including a load transistor and a driving transistor, Wherein the SRAM cell comprises a conductive transistor connected between the access transistor and the driving transistor and the gate electrode of the conductive transistor is controlled by a column direction auxiliary line. Device is provided.

Here, the conduction transistor is a PMOS transistor, and a node connecting the conduction transistor and the driving transistor is used as a cell data node.

The column direction auxiliary line may be lowered to a first negative voltage in a read operation and lowered to a second negative voltage in a write operation, and the first negative voltage and the second negative voltage may have different voltage values.

The magnitude of the first negative voltage may be determined in consideration of the read speed and the static noise margin in the read operation, and the magnitude of the second negative voltage may be determined in consideration of the write margin and the power consumption.

The column direction auxiliary line is formed parallel to the bit line, and the column direction auxiliary line is supplied with a voltage from the negative voltage generator.

Wherein the negative voltage generator is connected to a column decoder to apply the first negative voltage commonly only to a predetermined number of interleaved columns selected by the column decoder, Only the interleaved column selected by the decoder is activated to perform the read operation and the cells of the remaining columns are held in the column auxiliary line at the ground to perform the dummy read operation to improve the dummy read static noise margin.

The negative voltage generator includes a column decoding gate that operates when a column predecoding signal is input and outputs first and second row signals, a negative level shifter that changes an applied voltage to a negative voltage when the first row signal is input, A boosting capacitor connected between the capacitor driving unit and the row directional auxiliary line node; a gate controlled by the output signal of the negative level shifter; and a drain connected to the boosting capacitor, And a pre-bias transistor connected to the column-direction auxiliary line node and having a source connected to the ground.

Here, the negative voltage level of the column direction auxiliary line node may be determined by a capacitance ratio between the boosting capacitor and the column direction auxiliary line node.

In the standby mode, the column directional auxiliary line is held at ground so that the conducting transistor remains in the normally on state, the two cell data nodes hold the bistable data, and at the start of the read access, And the column direction auxiliary line is lowered to the first negative voltage, and when the word line is transitioned to " HIGH ", the voltage distributed in series along the access transistor, the conductive transistor and the driving transistor becomes 0 Value of the cell data node.

In the write operation, when the column direction auxiliary line falls to the second negative voltage and the cell data node having the content 0 is to write 1, the bit line BL is set to 0, and the bit line BL is set to 0, (/ BL) is set to the supply voltage, and when the word line transitions to HIGH, the internal node between the load transistor and the conduction transistor transitions from supply voltage to zero and the voltage drop across the cell data node triggers the inverter, Is changed.

According to the present invention, the stability of the built-in data storage device can be improved by improving the dummy read stability and the read stability as well as improving the write capability by the help of the column direction negative voltage bias control as compared with the conventional 6T SRAM cell have.

1 is a circuit diagram showing a conventional 6T SRAM cell structure.
2A is a circuit diagram showing an 8T SRAM cell structure according to the present invention.
FIG. 2B shows cell bias in standby mode, read access, and write access in an 8T SRAM cell structure according to the present invention.
FIG. 3 illustrates a 64-Kbit 8T SRAM memory block to which an 8T SRAM cell according to the present invention is applied.
Figure 4 illustrates the state of a memory cell in an array during read and write accesses in Figure 3;
5 is a circuit diagram showing an internal configuration of a negative voltage generator according to the present invention.
6 shows a simulation waveform in a read operation and a write operation in an 8T SRAM cell according to the present invention.
7 shows a butterfly curve of a conventional 6T SRAM cell and an 8T SRAM cell of the present invention.
8 is a graph comparing a read static noise margin (SNM) according to a temperature change of a conventional 6T SRAM cell and an 8T SRAM cell according to the present invention.
Figure 9 shows a butterfly curve for a memory cell in which a dummy read operation is performed during read and write accesses.
FIG. 10 is a graph comparing dummy read stability of a conventional 6T SRAM cell with an 8T SRAM cell according to the present invention.
11 is a graph comparing simulation results of a write capability of a conventional 6T SRAM cell and an 8T SRAM cell of the present invention.
12A shows a simulation result of a write margin according to a temperature change of a conventional 6T SRAM cell and an 8T SRAM cell according to the present invention.
12B shows a simulation result of a write margin according to a supply voltage change of a conventional 6T SRAM cell and an 8T SRAM cell according to the present invention.
13A shows a simulation result of an atmospheric leakage power consumption according to a supply voltage change of a conventional 6T SRAM cell and an 8T SRAM cell according to the present invention.
13B shows a simulation result of the WA leakage power consumption according to the temperature change of the conventional 6T SRAM cell and the present invention 8T SRAM cell.
FIG. 14 shows leakage current paths of a conventional 6T SRAM cell and an 8T SRAM cell below the threshold value in the present invention.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a conventional 6T SRAM cell, in which MN1 and MN2 are driving transistors, MP1 and MP2 are load transistors, and MN3 and MN4 are access transistors. The fundamental stability problem of the 6T cell structure occurs in the read operation. During the read operation, the word line WL transitions from 'LOW' to 'HIGH' while the bit line pair (BL and / BL) is held at 'HIGH'. The internal nodes DN and / DN of the cell whose state value is 0 are increased in voltage through the access transistors MN3 and MN4 due to the voltage distribution effect of the access transistors MN3 and MN4 and the driving transistors MN1 and MN2 do. Furthermore, the voltage transfer gain of the cell inverter is lowered due to the parallel connection of the access transistors MN3 and MN4 and the load transistors MP1 and MP2. The voltage rise of the internal nodes (DN, / DN) of the cell severely weakens the noise immunity of the cell. If the 'LOW' node voltage is higher than the logic threshold of the other cell inverters, the contents of the cell may change, resulting in a read failure. For the read function, it is desirable to strengthen the driving transistors MN1 and MN2 and to weaken the access transistors MN3 and MN4. On the other hand, the access transistors MN3 and MN4 having a strong driving capability and the load transistors MP1 and MP2, which are relatively weak, are preferable for realizing an appropriate writing operation. Accordingly, careful transistor sizing with appropriate device size to minimize the SRAM cell area is required to ensure balanced stability in both read and write operations.

The 8T SRAM cell proposed in the present invention is shown in FIG. In this structure, two PMOS transistors MP3 and MP4, which are conductive transistors, are added between the access transistors MN3 and MN4 and the driving transistors MN1 and MN2. The gates of the conduction transistors MP3 and MP4 are controlled by a column wise assist line (CAL).

2B shows cell bias in standby mode, read access, and write access. In the standby mode, the CAL is held at ground and the conduction transistors MP3 and MP4 are maintained in the normally on state. Two cross-coupled inverters (MP1-MN1, MP2-MN2) in the cell maintain bistable data.

In the read operation (Read), it is assumed that V _DN = 0 and V _{/ DN} = V _DD initially. At the start of read access, the bit line pair (BL, / BL) is precharged to the supply voltage V _DD and the CAL drops to -V _PPR . When the word line transitions to " HIGH ", the voltages distributed in series along the access transistor MN3, the conductive transistor MP3 and the driving transistor MN1 suppress the voltage rise of the internal node DN indicating 0 . This drastically improves read stability, which depends mainly on the conductance of the conduction PMOS transistor, which is a function of the -V _PPR voltage level. Compared with the 6T cell, the pull-down driving transistor can be reduced in strength in the 8T cell.

In write access, the CAL is lowered to another negative voltage -V _PPW . For successful writing, the bit cell becomes monostable and keeps the internal voltage at its current value. It is assumed that V _DN = V _DD and V _{/ D n} = 0 as initial values. To write 0 to the DN node, BL is set to 0 and / BL is set to V _DD . When WL transitions to HIGH, the PN node transitions from V _DD to 0. Because the gate of the conduction PMOS transistor is biased to a negative voltage, the DN node can easily be discharged from V _DD to zero. The voltage drop at the DN node triggers the inverter (MP2-MN2). Positive feedback inside the cell changes the contents of the cell.

Specific design of memory

The present inventors have implemented the conventional 6T SRAM and the 8T SRAM of the present invention with 130nm logic CMOS technology in order to compare various SRAM stability measures and leakage characteristics. Typical threshold voltages of NMOS and PMOS are 0.34 and -0.34V, respectively. The nominal supply voltage for this process is 1.2V. For a conventional 6T cell, the widths of the driving transistors MN1 and MN2 are 270 nm, and the widths of the other transistors are 150 nm. In the 8T cell of the present invention, the widths of the access transistors MN3 and MN4 are 360 nm and the widths of the other transistors are 150 nm. All devices in both cells have a minimum channel length of 130 nm to minimize cell area. The 8T cell of the present invention occupies 38% more area than the 6T. In more integrated CMOS technologies such as 65nm, 45nm, or more, the area overhead will remain the same as 6T and 8T cells will be integrated in the same way.

Figure 3 shows a 64-Kbit memory array comprising an 8T SRAM cell of the present invention. The logical structure is basically the same as the conventional 6T cell array structure. The feature in the memory array of FIG. 3 is that the negative voltage generator 100 controls the CAL signal operated in parallel with the bit lines BL and / BL and provides eight CAL signals in common. The remaining main circuit and peripheral logic are mostly the same as in the prior art. In each read or write access, the negative voltage generator 100 decoded by the column address activates only eight interleaved rows (AC). On the other hand, the cells of the remaining columns of the selected row are held in the ground CAL as shown in FIG. 4, and a dummy read operation is performed.

5 shows a negative voltage generator used in the present invention. The negative voltage generator includes a column decoding gate 110, a capacitor driving unit 120, a boosting capacitor 130, a negative level shifter 140, and a pre-bias transistor M5. In the initial state, both the input node A of the negative level shifter 140 and the node D of the boosting capacitor are at the V _DD level. Therefore, CAL is connected to the ground by the pre-bias transistor M5. At the beginning of the read and write accesses, the column pre-decoded signal Y selects the appropriate local tone generator 100. Then, the preset signal (PRE) transited to 'HIGH' causes node A to be grounded. At this time, when M1 and M4 are on and M2, M3 and M5 are off, CAL is floated. The subsequent signal PB changes node D to ground, whereby the CAL is boosted to a negative voltage by capacitive coupling. After the read and write operations of the selected memory cell, the signals PB and PRE both return the boosting capacitors 130 and the negative level shifter 140 to their initial states. The negative voltage level is determined by the capacitance ratio of all parasitic capacitances associated with the boosting capacitor 130 and the CAL node. In the present embodiment, for simplicity of description, -V _PPR = -V _PPW = -0.4 × V _DD , it is desirable that these two voltages have different values that are optimized for read and write performance. In other words, the lower the CAL is, the better the speed, but the lower the read static noise margin (SNM). In the write operation, the lower the CAL, the more the write margin (WM) increases but the power consumption increases. Value is selected.

6A shows a signal waveform in a read operation. After the bit line pre-charge transistor (not shown) is disabled, the read operation is initiated by pulling CAL down to a negative voltage.

When the word line transitions to " HIGH ", the read path is turned on or off according to the state of the cell data node DN. If the cell data node DN is " HIHG ", then the read path will not be turned on and hence BL will be held at V _DD , and if the cell data node DN is LOW the read path is turned on, It will flow from BL to ground. This causes the voltage level of the bit line BL to drop. The voltage difference between BL and / BL is sensed by the sense amplifier and amplified as a full swing signal.

6B shows waveforms in a write operation. After the bit line precharge transistor is disabled, the write operation is initiated as CAL is pulled down to a negative voltage. Next, the bit line BL is driven with new data. When the word line WL is activated later on, the cell data node (DN, / DN) is immediately flipped from its original state to another state. After word line WL is switched back to ground, CAL is returned to ground and BL and / BL are precharged to V _DD .

Read Stability

7 shows a butterfly curve of a conventional 6T SRAM cell and an 8T SRAM cell of the present invention. The plot of the 8T cell was obtained when the negative CAL bias voltage V _CAL = -0.48V. The static noise margin (SNM) corresponds to the length of one side of the largest square in the curve. Here, the maximum square means the maximum size square that can be created within the space between two state transition curves. Under the conditions of V _DD = 1.2 V and room temperature, the read static noise margin (SNM) of the 8T cell of the present invention is about 88% larger than that of the 6T cell. This means that the voltage rise of the internal node representing 0 is V _DD - V _TN - V _SDP . Where V _TN is the threshold voltage of the NMOS access transistor and V _SDP is the source-drain voltage drop of the PMOS conduction transistor. This provides a butterfly curve that is close to ideal for robust SRAM bit cell designs.

Read stability for other process corners is evaluated in FIG. The process parameters have 3-sigma variability. In the graph of FIG. 8, TT is a general-NMOS, general-PMOS, FS is fast-NMOS, slow-PMOS, slow-NMOS is SF, fast-PMOS, SS is slow- NMOS, and fast-PMOS, and fast and slow represent the operation speed of the transistor. At the worst case (TT, 25 ° C), the worst (FF, -40 ° C) and the worst (SS, 100 ° C) conditions, the read static noise margin (SNM) of the 8T cell of the present invention is 80% It is high. The read SNM variation between the extreme corners (FS: low V _TN , high V _TP , SF: high V _TN , low V _TP ) in the inventive 8T cell is 60mV, which is lower than 99mV in the 6T cell, It means variation tolerance.

Stack Read Stability

Figure 9 shows a butterfly curve for a memory cell in which a dummy read operation is performed during read and write accesses. When the cell data node DN rises from 0 to V _DD , the other cell data node / DN is transitioned from V _DD to 0. During this time, the voltage drop across the conduction PMOS transistor causes the / DN voltage of the 8T cell to be much lower to ground. Since the gate of the conduction transistor of the 8T cell is tied to the ground, the voltage rise of the internal node representing 0 is limited to V _DD - V _TN - | V _TP | Here, V _TN and V _TP are the threshold voltages of the NMOS access transistor and the PMOS conduction transistor, respectively. It also provides near ideal voltage transfer characteristics for robust SRAM cell designs. At 1.2V and 100 ° C, the 6T cell has an SNM of 180mV, while the 8T cell has an SNM of 382mV and a 112% higher dummy read SNM.

The dummy read stability for the other process corners is evaluated in FIG. Under typical conditions (TT, 25 ° C), worst-case (FF, -40 ° C) and worst-case (SS, 100 ° C) conditions, the 8T cell's dummy read static noise margin is nearly 100% higher than the 6T cell. At the FS (low V _TN , high V _TP ) corner, the logic threshold voltage of the cell inverter will decrease and the stability will deteriorate accordingly. Similarly, at the SF (high V _TN , low V _TP ) corner, the logic threshold voltage will rise and thus the stability will improve. V _DD = 1.2V, the SNR of the dummy read between extreme corners (FS, SF) at room temperature is as low as 62mV at 8T cells compared to 99mV at 6T cells, indicating improved process variation immunity.

Writing ability

The write capability of the bit cell indicates how easy or difficult it is to write the cell. In the present invention, the write margin (WM) is defined as the difference between the word line voltage required to flip the cell contents when V _DD and the bit line pair are set to V _DD and 0V, respectively. The larger the voltage difference, the easier the cell write.

Figure 11 shows simulated write capability at 1.2V, TT, room temperature conditions. Plots for the 8T cell were obtained when the negative CAL bias voltage V _CAL was -0.48V. The write margin represents values of 446mV and 537mV for the 6T cell and the 8T cell, respectively, and the intensity of the access transistor within the tolerance range of the bit region can be increased in the 8T cell of the present invention. Through a negative voltage biased conduction transistor with a strong access transistor, the node storing a '1' in the 8T cell is phased out at a much lower WL voltage and provides a higher write margin (WM). Compared with the conventional 6T cell, the 8T cell has better read stability as well as write capability.

FIG. 12 shows the simulation result of the write margin by temperature for different supply voltages. The PMOS load transistor is weaker than the NMOS access transistor as the temperature rises, so that the write capability at high temperature is improved. As V _DD increases, the write margin increases. The negative bias of the conducting transistor during the write transition allows the 8T cell to obtain improved write performance at lower supply voltages. As a result, the write margin of the 8T cell remains higher than 6T for all voltage ranges. Furthermore, it can be seen that the variation of the write margin at the process corners (FS, SF) distorted at 1.2V, -40 ° C is 201 mV in the 6T cell, while 162mV in the 8T cell shows the improved process variation tolerance.

Leakage power consumption

The bit cell structure according to the present invention also reduces the total leakage power. For the 6T SRAM cell and the 8T SRAM cell in the standby mode, the access transistor is cut off and the bit line pair is charged to V _DD . In the 8T cell, the gate of the conduction transistor is tied to the ground. For each cell, the total leakage current is the sum of the leakage below the threshold voltage, gate induced drain leakage (GIDL), gate tunneling leakage, and junction leakage of all transistors.

13 shows a simulation result of the WAIT power consumption of the conventional 6T cell and the 8T cell of the present invention. As shown in Fig. 13A, the power consumption exponentially increases as the supply voltage rises. As shown in FIG. 13B, when the temperature rises, the leakage power exponentially increases as well. V _DD = 1.2 V, the leakage power consumed by the 8T cell at room temperature is reduced by 45% compared to the conventional 6T cell structure. 13B shows leakage power dissipation consumed in each cell transistor. Small driving transistors also contribute to this reduction in atmospheric leakage, but a major part of the atmospheric leakage reduction is due to reduced leakage of the access transistor and load transistor. 14, the internal node (PN) of the 8T cell rises to a specific voltage higher than the ground during the standby mode, and the leakage current path from the access transistor and the load transistor to the data 'LOW' Experience stacking effects. Furthermore, in the 8T cell, the access transistor can be turned off more reliably due to the negative voltage V GS and the substrate bias effect. The overall result significantly reduces the component below the threshold voltage of the leakage current, which is more pronounced at high temperatures, as can be seen in Figure 13a.

As described above, an optimal embodiment has been disclosed in the drawings and specification. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

MP1, MP2: Load transistor MN1, MN2:
MN3, MN4: Access transistor MP3, MP4: Conductive transistor
BL, / BL: bit line WL: word line
PN, / PN: internal node DN, / DN: cell data node
M5: Pre-bias transistor CAL: Column auxiliary line
110: Thermal decoding gate 120: Capacitor driver
130: boosting capacitor 140: negative level shifter

Claims (16)

An SRAM cell comprising two access transistors cross-coupled to each other, the two inverters including a load transistor and a driving transistor, and allowing access from the bit line to the respective inverter,
Wherein the SRAM cell includes a conduction transistor connected between the access transistor and the driving transistor, and a gate electrode of the conduction transistor is controlled by a column direction auxiliary line. The method according to claim 1,
Wherein the conduction transistor is a PMOS transistor. The method according to claim 1,
And a node connecting the conduction transistor and the driving transistor is used as a cell data node. The method according to claim 1,
Wherein the column direction auxiliary line falls to a first negative voltage in a read operation and falls to a second negative voltage in a write operation. 5. The method of claim 4,
Wherein the first negative voltage and the second negative voltage have different voltage values. 6. The method of claim 5,
Wherein the magnitude of the first negative voltage is determined in consideration of a read speed and a static noise margin in a read operation. 6. The method of claim 5,
Wherein a magnitude of the second negative voltage is determined in consideration of a write margin and power consumption. 5. The method of claim 4,
And the column direction auxiliary line is formed in parallel with the bit line. 9. The method of claim 8,
And the column direction auxiliary line receives a voltage from the negative voltage generator. 10. The method of claim 9,
Wherein the negative voltage generator is connected to a column decoder to apply the first negative voltage only to a predetermined number of interleaved rows selected by the column decoder. 11. The method of claim 10,
Only the interleaved column selected by the column decoder among the cells in the row selected by the word line in the read operation is activated to perform the read operation and the cells in the remaining columns are held in the ground in the column direction auxiliary line to perform the dummy read operation Wherein the semiconductor memory device is a semiconductor memory device. 12. The method of claim 11,
The negative voltage generator
A column decoding gate that operates when a column predecoding signal is input and outputs first and second row signals;
A negative level shifter for changing an applied voltage to a negative voltage when the first row signal is input;
A capacitor driving unit operated by the second row signal;
A boosting capacitor connected between the capacitor driver and the column-direction auxiliary line node;
A pre-bias transistor whose gate is controlled by the output signal of the negative level shifter, and whose drain is connected to the boosting capacitor and the column-direction auxiliary line node, and whose source is connected to the ground. 13. The method of claim 12,
Wherein a negative voltage level of the column direction auxiliary line node is determined by a capacitance ratio of the boosting capacitor and the column direction auxiliary line node. The method of claim 3,
Wherein in the standby mode, the column direction auxiliary line is maintained at ground, whereby the conduction transistor remains in the normally on state, and the two cell data nodes hold the bistable data. 15. The method of claim 14,
At the start of read access, the bit line pair is precharged to the supply voltage and the column direction auxiliary line is lowered to the first negative voltage, and when the word line is transitioned to " HIGH ", the access transistor, And the voltage distributed in series suppresses a voltage rise of the cell data node having a value of zero. 15. The method of claim 14,
In the write operation, when the column direction auxiliary line falls to the second negative voltage and the cell data node having the content 0 is to write 1,
The bit line BL is set to zero and the bit line / BL of the opposite polarity is set to the supply voltage. When the word line transitions to HIGH, the internal node between the load transistor and the conduction transistor changes from the supply voltage to zero And the voltage drop of the corresponding cell data node triggers the inverter to change the contents of the cell.

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