JP2006269023A - Semiconductor memory apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory apparatus provided with optimum memory cells, a sub-word driver, or the like for stable operation since an SRAM cell constituted of 6 transistors is not operated stably by miniaturizing them and reducing voltage. <P>SOLUTION: The SRAM cell is constituted of a first inverter circuit whose output is a memory node V1, a second inverter circuit whose output is a memory node V2, an access transistor N3 connected between a read-out bit line and the memory node V1, and an access transistor N4 connected between a write-in bit line and the memory node V2. The first and the second inverter circuits are connected in a loop, threshold voltage of the second inverter circuit is set to higher than threshold voltage of the first inverter circuit. Further, pre-charge voltage of the read-out bit line is lower than power source voltage and VDD2 is higher than the threshold voltage of the second inverter circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which prevents destruction of stored data at the time of reading and operates at an ultra-high speed and an ultra-low voltage.

  Recent semiconductor devices have been scaled up and speeded up, and many functions have been incorporated into a system. Transistors are miniaturized to increase the scale and speed, and the operating speed is improved while lowering the power supply voltage. In addition, various function blocks including a CPU and various storage devices are mixed for systemization. Similarly, storage devices embedded in these system LSIs are required to operate at a high speed and with a low power supply voltage. For example, static random access memories (SRAMs) embedded in applications such as cache memories. In the same manner, high-speed operation and operation with a low power supply voltage are also required in the following description.

  A conventional SRAM will be described with reference to FIG. FIG. 1 shows a conventional SRAM memory cell composed of six transistors (hereinafter referred to as an SRAM cell). When the word line WL is at a low potential, two CMOS (Complementary Metal Oxide Semiconductor) inverters form a loop so that data can be stably held. That is, one CMOS inverter receives the storage node V1 as an input and outputs inverted data of the data stored in the storage node V1 to the storage node V2. The other CMOS inverter receives the storage node V2 as an input and the storage node V2 The inverted data of the data stored in is output to the storage node V1.

  When the word line WL is accessed and is at a high potential, the access transistors N3 and N4 are turned on, so that the data stored in the storage nodes V1 and V2 is read out to the bit lines BLT and BLN, which results in a memory read operation. The memory write operation is performed by writing the data from the bit lines BLT and BLN to the storage nodes V1 and V2.

  However, the conventional SRAM cell has a problem that stored data is destroyed when a read operation is performed at a low power supply voltage.

  The destruction of stored data during the read operation will be described. The word line WL becomes high level, the access transistors N3 and N4 become conductive, the storage nodes V1 and V2 are connected to the bit lines BLT and BLN, respectively, and try to rise to the bit line level. For example, when the storage node V1 is stored at a low level, the storage node V1 is slightly raised by the bit line BLT, but the drive transistor N1 is in the on state, and the potential is lowered. However, when this increased potential exceeds the threshold level of the opposite drive transistor N2, the drive transistor N2 is turned on, the level of the storage node V2 is lowered, and the on-current of the drive transistor V1 is decreased. The storage node V1 further rises and the stored data is destroyed.

  Generally, in an SRAM cell, a static noise margin (SNM) is used as an index for measuring the stability of data retention when accessed. As shown in FIG. 2, the SRAM cell is divided into two inverters, and the DC (direct current) characteristics of each inverter are obtained, and the DC characteristic output of one inverter becomes the DC characteristic input of the other inverter. Thus, when two DC characteristics are superimposed, a butterfly curve is drawn. The SNM is defined as one side of the largest square inscribed in this butterfly curve. When SNM is 0 mV or higher, normal read operation is performed. When SNM is 0 mV or less, the inverted data is overwritten during the read operation.

  About this SNM, the future prediction is performed in the following nonpatent literature 1. That is, when the channel length of the transistor used is reduced as shown in FIG. 3 and the channel length of the transistor shifts from 250 nm to 50 nm, the SNM not only decreases the average value but also the SNM deviation. Increase. Therefore, the worst value of SNM is significantly deteriorated. At the illustrated 50 nm, the worst value of the SNM becomes “0” or less, so that the stored data is destroyed when the word line WL becomes a high potential accompanying the read operation.

  Various studies have been made on these problems, and prior literatures have been disclosed. Patent Document 1 discloses a two-port memory that performs reading and writing by changing the power supply voltage level. Patent Document 2 discloses a technology in which a drive transistor has a silicide structure and an access transistor uses a non-silicide and a transistor to increase the current drive capability of the transistor. Patent Document 3 discloses a technique for expanding the SNM by controlling the GND line of the SRAM cell to vary the threshold voltage of the inverter circuit.

A. J. Bhavnagarwala “The impact of intrinsic device fluctuations on CMOS SRAM cell stability” IEEE Journal of Solid State Circuit, Vol. 36, No. 4, Apr. 2001 (Figures 5 and 10) JP 05-166375 A JP 2004-040119 A JP 2003-086713 A

  As described above, the conventional SRAM cell composed of six transistors is miniaturized and the voltage is reduced, so that the SNM is reduced and the stable operation is not performed. Patent Document 3 describes a technique for increasing the SNM for an SRAM cell, but does not describe optimization of the SRAM cell and an optimal peripheral circuit. Further, there is a problem that the area of the sense amplifier is increased in order to control the GND line of the SRAM cell. There is a demand for further optimization of memory cells that can operate at a high speed at a low voltage and prevent destruction of stored data during a read operation, and to develop an optimal peripheral circuit and a semiconductor memory device including these.

  The present invention has been made to remedy the above problems, and an object of the present invention is to provide a memory cell capable of preventing destruction of stored data during a read operation in an ultrahigh-speed operation or an ultra-low voltage operation. And a peripheral circuit thereof, and a semiconductor memory device including these.

  The semiconductor memory device of the present application includes a first inverter circuit that outputs a first storage node, a second inverter circuit that outputs a second storage node, a read bit line, and the first storage node. And a second access transistor connected between a write bit line and the second storage node, and the first and second inverter circuits. Are connected in a loop to each other, and the load transistors of the first and second inverter circuits and the first and second access transistors have substantially the same driving capability, respectively, and the second inverter circuit The drive capability of the first inverter circuit is made smaller than the drive capability of the drive transistor of the first inverter circuit, and the threshold voltage of the second inverter circuit is Characterized by comprising a serial first inverter circuit is set high memory cell than the threshold voltage of the.

  In the semiconductor memory device of the present application, the read bit line is precharged to a precharge voltage value that is higher than a threshold voltage of the second inverter circuit and lower than a power supply voltage of the first inverter circuit. And

  In the semiconductor memory device of the present application, the precharge voltage is lower than the power supply voltage by a threshold voltage value of the first access transistor.

  In the semiconductor memory device of the present application, the write bit line is precharged to a ground potential.

  In the semiconductor memory device of the present application, the write bit line is connected to a ground potential.

  The semiconductor memory device of the present application includes a first inverter circuit that outputs a first storage node, a second inverter circuit that outputs a second storage node, a read bit line, and the first storage node. And a second access transistor connected between a write bit line and the second storage node, the memory cell comprising: a first access transistor connected between the first storage transistor and a second access transistor connected between the second storage node; The second inverter circuits are loop-connected to each other, the threshold voltage of the second inverter circuit is set higher than the threshold voltage of the first inverter circuit, and the read bit line is the threshold voltage of the second inverter circuit It is precharged to a precharge voltage value higher than that of the power supply voltage of the second inverter circuit.

  In the semiconductor memory device of the present application, the sense amplifier that performs data transmission with the memory cell includes a read bit line and a write bit line, a data line that performs data transmission with the input / output circuit, an inverted write data line, and the read bit. A NOR circuit that inverts and outputs data from the line; data reading means that transmits the output of the NOR circuit to the data line; and writing means that transmits data from the data line to the read bit line by a write signal; The write bit line is connected to the inverted write data line.

  In the semiconductor memory device of the present application, the sense amplifier includes a precharge unit that precharges the read bit line by a precharge signal, and a high level of the read bit line when the read bit line is at a high level in a read operation. And reinforcing means for maintaining the level.

  In the semiconductor memory device of the present application, the precharge means precharges the read bit line to a voltage value lower than a power supply voltage by a threshold voltage of the transistor.

  In the semiconductor memory device of the present application, the NOR circuit receives an inverted read enable signal and transmits data from the read bit line to the data line at the time of reading.

  In the semiconductor memory device of the present application, the sense amplifier that transmits data to and from the memory cell is precharged to a read bit line that is lower than the power supply voltage by a threshold voltage of the transistor and to a ground potential. It is connected to the write line, and at the time of reading, the data of the memory cell read to the read bit line is read to the data line via the NOR circuit controlled by the inverted read signal, and at the time of writing, the data from the data line is read The write signal is transmitted to the read bit line, the inverted data from the inverted write data line is transmitted to the write bit line, and the memory cell is written from the read bit line and the write bit line.

  In the semiconductor memory device of the present application, a read word line signal is generated by the inverted main word signal, the read block signal and the inverted read block signal, and writing is performed by the inverted main word signal, the write block signal and the inverted write block signal. A sub word driver circuit for generating a word line signal is further provided.

  In the semiconductor memory device of the present application, the sub-word driver circuit includes a first inverter circuit that receives the inverted main word signal and outputs the read word line signal, and a first inverter circuit connected to the output of the first inverter circuit. 1 transistor, the first inverter circuit is formed between the read block signal and a ground potential, and the drain, source, and gate of the first transistor are output from the first inverter circuit, respectively. , Ground potential, and connected to the inverted read block signal.

  In the semiconductor memory device of the present application, the sub word driver circuit includes a second inverter circuit that receives the inverted main word signal as an input and outputs the write word line signal, and a second inverter circuit connected to the output of the second inverter circuit. And the second inverter circuit is formed between the write block signal and a ground potential, and the drain, source, and gate of the second transistor are output from the second inverter circuit, respectively. , Ground potential, and connected to the inverted write block signal.

  In the semiconductor memory device of the present application, the memory cells are arranged in a matrix of m rows and n columns (m and n are positive integers) and m subword drivers on one side in the vertical direction around the memory cell array. N sense amplifiers are arranged on one side in the horizontal direction, and the sub-word driver generates a read word line signal from the inverted main word signal, the read block signal and the inverted read block signal, and further, the inversion A write word line signal is generated by a main word signal, a write block signal, and an inverted write block signal, and is supplied to the memory cell. The sense amplifier is a NOR circuit that inverts and outputs data from the read bit line, and Data reading means for transmitting the output of the NOR circuit to the data line, and the data by the write signal. Wherein the data from the line with a writing means for transmitting to said read bit line.

  In the semiconductor memory device of the present application, the read bit line is precharged to a precharge voltage that is higher than a threshold voltage of the second inverter circuit and lower than a power supply voltage of the first inverter circuit. The generation circuit for generating the memory cell is divided and arranged in a control unit which is an intersection of the sub word driver and the sense amplifier arranged around the memory cell array.

  In the semiconductor memory device of the present application, an inverter circuit that inverts the inverted read block signal and the inverted write block signal input to the sub word driver and generates the read block signal and the write block signal includes: The read block signal and the write block signal are provided to the sub-word driver in the memory cell block. The read block signal and the write block signal are provided in a control unit that is an intersection of the sense amplifiers.

  The SRAM cell includes a first inverter circuit that outputs the storage node V1, a second inverter circuit that outputs the storage node V2, and an access transistor N3 connected between the read bit line and the storage node V1. And an access transistor N4 connected between the write bit line and the storage node V2. The first and second inverter circuits are connected in a loop, and the threshold voltage of the second inverter circuit is set higher than the threshold voltage of the first inverter circuit. The precharge voltage of the read bit line is set to VDD2 lower than the power supply voltage and higher than the threshold voltage of the second inverter circuit, and high speed operation is possible to perform read from the read bit line and write operation from the read bit line and the write bit line An SRAM cell and a semiconductor memory device are obtained.

  An SRAM cell of a semiconductor memory device that operates at an ultra-high speed with a low power supply voltage and its peripheral circuit will be described in detail with reference to the drawings.

  As Example 1, an SRAM cell 1 used in the present invention will be described with reference to FIGS. FIG. 4 is a diagram showing a circuit configuration of the SRAM cell 1. FIG. 5 is an explanatory diagram of SNMs in various SRAM cells. FIG. 6 shows operation waveforms at the time of (a) “0” read, (b) “1” read, (c) “0” write, and (d) “1” write in the SRAM cell 1.

  The SRAM cell 1 shown in FIG. 4 includes six load PMOS transistors P1 and drive NMOS transistors N1, PMOS transistor P2 and drive NMOS transistor N2, and NMOS transistors N3 and N4 as access means, which respectively form CMOS inverters. A transistor is used.

  The first CMOS inverter circuit is composed of a PMOS transistor P1 and an NMOS transistor N1, receives data from the storage node V2, and outputs data to the storage node V1. The second CMOS inverter circuit is composed of a PMOS transistor P2 and an NMOS transistor N2, receives data from the storage node V1 as input, and outputs data to the storage node V2. Two inverter circuits are connected in a loop.

  The drain, source, and gate of the PMOS transistor P1, which is a load transistor, are connected to the storage node V1, the power supply voltage, and the storage node V2, respectively. The drain, source, and gate of the NMOS transistor N1 that is a drive transistor are connected to the storage node V1, the ground potential, and the storage node V2, respectively. The drain, source, and gate of the PMOS transistor P2, which is a load transistor, are connected to the storage node V2, the power supply voltage, and the storage node V1, respectively. The NMOS transistor N2, which is a drive transistor, has its drain, source, and gate connected to the storage node V2, the ground potential, and the storage node V1, respectively.

  The NMOS transistor N3, which is a read / write access transistor, is connected between the read bit line RBL and the storage node V1, and the read word line RWL is connected to the gate thereof. The NMOS transistor N4, which is a write access transistor, is connected between the write bit line WBL and the storage node V2, and the write word line WWL is connected to the gate thereof.

  The characteristics of the SRAM cell 1 of this embodiment will be compared with a memory cell composed of ordinary six transistors. As a configuration, the word line is divided into a read word line RWL and a write word line WWL to be two. The bit line includes a read bit line RBL for both reading and writing, and a write bit line WBL dedicated to writing. In reading, the read word line RWL is set to the high level, the access transistor N3 is turned on, and the data of the storage node V1 is transmitted to the sense amplifier via the read bit line RBL.

  In writing, both the read word line RWL and the write word line WWL are set to the high level, both the access transistor N3 and the access transistor N4 are made conductive, and complementary data from the read bit line RBL and the write bit line WBL are stored in the storage nodes V1 and V2. Write.

  Here, the load transistors of the first and second inverter circuits and the first and second access transistors have substantially the same drive capability. Furthermore, the drive capability of the drive transistor of the second inverter circuit is made smaller than the drive capability of the drive transistor of the first inverter circuit. By varying the drive capability of the drive transistor, the threshold voltages of the first and second inverter circuits constituting the flip-flop are varied. The threshold voltage of the second inverter circuit is set higher than the threshold voltage of the first inverter circuit. In order to increase the threshold voltage, the drive capability of the drive transistor may be reduced. For example, the threshold voltage of the transistor is increased by increasing the channel length L of the transistor N2, decreasing the channel width W, or increasing the impurity concentration.

  At this time, the driving capability of the transistors P2 and N4 is the same as that of the paired transistors P1 and N3, so that the writing speed can be made equal. For example, when the drive capability of the access transistor N4 is reduced, the writing speed to the storage node V2 is reduced. Therefore, it is important to reduce the drive capability of only the transistor N2 and increase the threshold voltage of the inverter circuit.

  Further, VDD2 = VDD−Vth (N), in which the precharge voltage of the read bit line RBL is lowered from the power supply voltage VDD by the threshold voltage of the transistor. For example, as a circuit for generating the precharge voltage VDD2, there is a circuit shown in FIG. If the threshold value of the transistor N31 in FIG. 13 is a positive threshold voltage, VDD2 = VDD−Vth (N), and a precharge voltage lower than the power supply voltage VDD is obtained. A transistor having the same characteristics as the access transistor of the memory cell can be used as the transistor N31. However, the precharge voltage VDD2 is not particularly limited, and may be lower than the power supply voltage VDD and higher than the threshold voltage of the second inverter circuit.

  As described above, the precharge voltage VDD2 of the read bit line is made lower than the power supply voltage VDD, thereby suppressing a temporary increase in potential at the storage node V1 at the time of “0” reading shown in FIG. be able to. Furthermore, since the threshold voltage of the inverter circuit composed of the transistors P2 and N2 is set high, the second inverter circuit outputs “1” to the storage node V2 to prevent the situation where the stored data is destroyed. ing. Further, since the precharge voltage VDD2 of the read bit line is higher than the threshold voltage of the second inverter circuit, the second inverter circuit is connected to the storage node V2 at the time of “1” reading shown in FIG. 6B. By maintaining the state in which “0” is output, a situation in which stored data is destroyed is prevented.

  The SNM of these SRAM cells 1 will be described with reference to FIG. FIG. 5A shows a holding state in the SRAM cell (FIG. 1) that is configured by the conventional six transistors, and the two inverter circuits and the access transistor are symmetrical. FIG. 5B shows the SRAM cell in FIG. A read state by two bit lines is shown. 5C and 5D show a six-transistor configuration in which the inverter circuit is symmetric but the word lines are separated, and the holding state (c) and the reading state (d) in the SRAM cell for reading data from the reading bit line on one side Indicates. FIG. 5E shows a holding state of the SRAM cell 1 of the present application, and FIG. 5F shows a read state from the SRAM cell 1 of the present application.

  In the holding state shown in FIG. 5A, the first and second inverter circuits and the access transistor that are configured are symmetrical, and the input / output characteristics of each inverter circuit are symmetrical. (B) shows a read state by two bit lines (dual end) in this SRAM. At the time of reading, the SNM of the SRAM cell is reduced by temporarily rising the storage node storing “0” by the two bit lines precharged to the high level. Here, when the low level is stored in the storage node V1, the “0” state of the SRAM cell is defined, and when the high level is stored as the “1” state of the SRAM cell, the “0” margin, “ Both 1 "margin will be smaller.

  FIG. 5C shows the holding state of the SRAM cell in which the word line is separated in the 6-transistor configuration and the input / output characteristics of the two inverter circuits are symmetric, and FIG. 5D is the state in the SRAM cell of FIG. A read state by one bit line (single end) on one side is shown. In the holding state shown in FIG. 5C, the same SNM as in FIG. However, in the case of reading by single end, when the storage node V1 stores a low level, the SNM becomes small by increasing the low level. On the other hand, when the storage node V2 stores the low level, the SNM does not change, and the “0” margin in the SNM becomes small as shown in FIG. 5D, but the “1” margin does not change.

  FIG. 5E shows a holding state of the SRAM cell 1 of the present application, and FIG. 5F shows a read state of the SRAM cell 1 of the present application. In FIG. 5 (e), by increasing the threshold voltage of the inverter circuit composed of the transistors P2 and N2, the input / output characteristics are shifted to the right, so that the “0” margin is large and the “1” margin is small. And the symmetry disappears.

  In the reading of FIG. 5F, when the “0” level is stored in the storage node V1 for the single-ended reading by the reading bit line, the SNM becomes narrow and the “0” margin becomes small. When the “0” level is stored in the storage node V2, the SNM does not change and the “1” margin is the same. However, by increasing the threshold voltage of the inverter circuit 2, the original “0” margin is widened, so that the “0” margin after fluctuation can be sufficiently wide.

  Further, in the SRAM cell 1 of the present embodiment, when the precharge voltage of the read bit line RBL is set to VDD2 which is lower than the power supply voltage by the threshold voltage of the transistor, the “0” level is stored in the storage node V1. The voltage rising from the low level becomes smaller, and the “0” margin can be further expanded.

  The operation waveforms at the time of (a) “0” read, (b) “1” read, (c) “0” write, and (d) “1” write in these SRAM cells 1 will be described with reference to FIG. To do. In FIGS. 6A, 6B, 6C, and 6D, the precharge voltage of the write bit line WBL while the write word line WWL is at the low level is set to the ground potential GND. It is not a thing.

  In the “0” reading shown in FIG. 6A, the read word line RWL becomes high level, and the access transistor N3 becomes conductive. The potential of read bit line RBL precharged to precharge voltage VDD2 is lowered by access transistor N3 and drive transistor N1. At this time, the potential of the storage node V1 rises temporarily, but the rise potential is small because the precharge voltage of the read bit line is as low as VDD2. Furthermore, since the threshold voltage of the inverter circuit composed of the transistors P2 and N2 is set high, the inverter circuit outputs a high level without exceeding the threshold voltage.

  The potential of the read bit line is pulled down by the access transistor N3 and the drive transistor N1, becomes low level, and "0" reading is performed. The read word line RWL becomes low level again, the read bit line RBL is precharged, and the read operation ends. At this time, the write word line WWL and the write bit line WBL of the write system do not change.

  In the “1” reading shown in FIG. 6B, the read word line RWL becomes high level, and the read access transistor N3 is turned on. At this time, since the precharge level of the read bit line RBL is higher than the threshold voltage of the second inverter circuit, the second inverter circuit is in the ON state and at the “0” level, and the first inverter circuit is at the “1” level. Maintain and output. Therefore, the read bit line RBL can read the “1” level of the storage node V1 as it is. The read word line RWL becomes low level again, the read bit line RBL is precharged, and the read operation ends. At this time, the write word line WWL and the write bit line WBL do not change.

  In the “0” write shown in FIG. 6C, the read bit line RBL becomes low level and the write bit line WBL becomes high level by the write data from the sense amplifier, and the read word RWL and write word line WWL become high level. It becomes. Due to the conduction of the access transistors N3 and N4, the low level of the read bit line RBL and the high level of the write bit line WBL are written to the respective storage nodes V1 and V2. The read word RWL and the write word line WWL become low level again, the read bit line RBL and the write bit line WBL are precharged, and the “0” write operation is completed.

  In (d) “1” writing shown in FIG. 6, the read bit line RBL becomes high level and the write bit line WBL becomes low level by the write data from the sense amplifier, and the read word RWL and write word line WWL become high level. It becomes. Due to the conduction of the access transistors N3 and N4, the high level of the read bit line RBL and the low level of the write bit line WBL are written to the respective storage nodes V1 and V2. The read word RWL and the write word line WWL become low level again, the read bit line RBL and the write bit line WBL are precharged, and the “1” write operation is completed.

  In the above-described “1” write and “0” write, the access transistors N3 and N4 are turned on, and write data from the read bit line RBL and the write bit line WBL is written into the memory cell. Since the drive capabilities of the access transistors N3 and N4 in this embodiment are equal, both “1” write and “0” write can be written at high speed in the same time.

  In this embodiment, the SRAM cell 1 includes a first inverter circuit that outputs the storage node V1, a second inverter circuit that outputs the storage node V2, and a read bit line and the storage node V1. The access transistor N3 is connected, and the access transistor N4 is connected between the write bit line and the storage node V2. The first and second inverter circuits are connected in a loop. The load transistors of the first and second inverter circuits and the first and second access transistors have substantially the same drive capability. The threshold voltage of the second inverter circuit is set higher than the threshold voltage of the first inverter circuit by making the drive capability of the drive transistor of the second inverter circuit smaller than the drive capability of the drive transistor of the first inverter circuit. To do.

  Further, the precharge voltage of the read bit line is set to VDD2 lower than the power supply voltage and higher than the threshold voltage of the second inverter circuit. With these structures, memory cells are prevented from being destroyed during reading, and high-speed reading is performed. Furthermore, high speed writing can be performed by setting the access transistors to have the same drive capability. An imbalanced SRAM cell capable of preventing a memory cell from being destroyed during reading and capable of performing high-speed reading and writing is obtained.

  As a second embodiment of the present application, a sense amplifier for exchanging data with an SRAM cell and an input / output circuit will be described with reference to FIGS. 7 shows a circuit diagram of the sense amplifier SA1, FIG. 8 shows a circuit diagram of the sense amplifier SA2, and FIG. 9 shows operation waveforms of the sense amplifiers SA1 and SA2.

  The sense amplifier SA1 in FIG. 7 performs data transmission with the memory cell through the read bit line RBL and the write bit line WBL, and performs data transmission with the input / output circuit through the read data line RDL, the write data line WDL, and the inverted write data line WDLB. To do. A write enable signal WE, a precharge signal PC, and an inverted precharge signal PCB are input as control signals.

  The output of the NOR circuit NR1 to which the read bit line RBL and the inverted precharge signal PCB are input is input to the gate of the transistor N12. The NOR circuit NR1 outputs a low level when the inverted precharge signal PCB is at a high level, and turns off the transistor N12. When the inverted precharge signal PCB is at a low level, the read data of the read bit line RBL is inverted and output, and the transistor N12 is turned on / off. The read transistor N12 has a drain connected to the read data line RDL and a source connected to the ground potential. The read transistor N12 is turned on / off by an output from the NOR circuit NR1 to transmit read data to the read data line RDL.

  The write enable signal WE is input to the gate of the write transistor N13 connected to the write data line WDL and the read bit line RBL. The write transistor N13 transmits the data on the write data line WDL to the read bit line RBL according to the high level of the write enable signal WE. The inverted write data line WDLB is directly connected to the write bit line WBL and transmits the data to the write bit line WBL. The write data line WDL and the inverted write data line WDLB have a complementary relationship.

  The drain, source, and gate of the precharge transistor N14 are connected to the precharge voltage VDD2, the read bit line RBL, and the inverted precharge signal PCB, respectively. The drain, source, and gate of the precharge transistor P12 are connected to the read bit line RBL, the precharge voltage VDD2, and the precharge signal PC, respectively. The precharge transistors N14 and P12 precharge the read bit line RBL to the precharge voltage VDD2 when the precharge signal PC is at a low level (the inverted precharge signal PCB is at a high level).

  The drain, source, and gate of the transistor P13 are connected to the read bit line RBL, the power supply potential VDD, and the inverted precharge signal PCB, respectively. The transistor P13 is a transistor that reinforces the high level of the read bit line RBL to prevent malfunction when the inverted precharge signal PCB is at the low level.

  At the time of reading data from the SRAM cell, the NOR circuit NR1 has the inverted precharge signal PCB at the low level, inverts the data of the read bit line RBL, and outputs it to the gate of the read transistor N12. Data in the SRAM cell is read by transmitting data to the read data line RDL by turning on and off the read transistor N12.

  On the other hand, at the time of writing, the write enable signal WE is at a high level, the data on the write data line WDL is transmitted to the read bit line RBL by the write transistor N13, and the inverted data is transmitted to the write bit line WBL connected to the inverted data line WDLB. Communicate and write to SRAM cell.

  The precharge transistors P12 and N14 precharge the read bit line RBL to the precharge voltage VDD2 when the precharge signal PC when the read or write is not performed is low level and the inverted precharge signal PCB is high level. Charge. Of the two precharging transistors, N14 can be omitted. The write bit line WBL is precharged to a ground potential by a transistor (not shown) by an inverted write enable signal WEB. Here, the precharge voltage of the write bit line WBL while the write word line WWL is at the low level is the ground potential GND. However, the present invention is not limited to this.

  The transistor P13 is a transistor that reinforces the high level of the read bit line RBL to prevent malfunction when the inverted precharge signal PCB is at the low level. However, since the current flows even when the read bit line RBL is at the low level, the channel length of the transistor is increased, the drive capability is decreased, and the read bit line RBL is set so as not to increase the low level.

  Further, the data line can be a data line DL for input / output by combining the read data line and the write data line. At this time, the read transistor N12 and the write transistor N13 may be connected to the data line instead of the read data line and the write data line.

  Next, the sense amplifier SA2 will be described. SA2 is an improved version of the sense amplifier SA1, and the sense amplifier SA2 has a transistor P15 added to the configuration of the sense amplifier SA1. The transistor P15 has a drain, a source, and a gate connected to the source of the transistor P13, the power supply voltage VDD, and the output of the NOR circuit NR1, respectively. In the sense amplifier SA1, in the case of reading “0” of the SRAM cell, a slight current flows from the transistor P13. When the read bit line RBL is at a low level, the output from the NOR circuit is fed back and the transistor P15 is turned off to cut off the current from the transistor 13. The transistor P15 is inserted to reinforce the high level when the read bit line RBL is high level, and when the read bit line RBL is low level, it is turned off and the current is cut off. Further, the position where the transistor P15 is inserted may be exchanged with P13.

  The sense amplifier SA2 has the same circuit configuration as that of the sense amplifier SA1 except that the transistor P15 is added. Also in the operation, a small current flows in the sense amplifier SA1 when the read bit line is at a low level. The only difference is in the point of complete interruption, and the other operations are the same, so that the description of the circuit configuration and its operation is omitted.

  FIG. 9 shows operation waveforms of (a) “0” read, (b) “1” read, (c) “0” write, and (d) “1” write of the sense amplifiers SA1 and SA2. In FIGS. 9A, 9B, 9C, and 9D, the precharge voltage of the write bit line WBL while the write word line WWL is at the low level is the ground potential GND. However, the present invention is not limited to this. Absent. As a modification of the sense amplifiers SA1 and SA2, the read data line RDL and the write data line can be combined into a data line. In this configuration, the read data line RDL at the time of reading may be replaced with the data line DL, and the write data line WDL at the time of writing may be replaced with the data line DL.

  In “0” reading shown in FIG. 9A, the precharge signal PC changes to a high level and the inverted precharge signal PCB changes to a low level. The read word line RWL changes to high level, and the access transistor N3 becomes conductive. The read bit line RBL is discharged through the drive transistor N1 of the SRAM cell, and decreases from the precharge voltage VDD2 to a low level. The NOR circuit outputs a high level, the read transistor N12 is turned on, and data “0” is read to the read data line RDL.

  The read word line RWL changes to low level, the precharge signal PC changes to low level, the inverted precharge signal PCB changes to high level, the read bit line RBL is precharged to VDD2, and the read data line RDL is precharged to VDD. . The write enable signal WE and the write word line WWL for the write system do not operate in the read cycle.

  In the “1” reading shown in FIG. 9B, the precharge signal PC changes to a high level and the inverted precharge signal PCB changes to a low level. The read word line RWL changes to high level, and the access transistor N3 becomes conductive. At this time, the storage node V1 is at the high level, and the read bit line RBL is not changed and the “1” level is read as it is. Here, the read bit line RBL is gradually pulled up by the transistor P13 of the sense amplifier and changes from the precharge voltage VDD2 to the power supply voltage VDD. The NOR circuit NR1 outputs a low level, the read transistor N12 is OFF, the read data line RDL maintains the precharge voltage VDD, and data “1” is read.

  The read word line RWL changes to low level, the precharge signal PC changes to low level, the inverted precharge signal PCB changes to high level, the read bit line RBL is precharged to VDD2, and the read data line RDL is precharged to VDD. . The write enable signal WE and the write word line WWL for the write system do not operate in the read cycle.

  In the “0” writing shown in FIG. 9C, the precharge signal PC changes to high level and the inverted precharge signal PCB changes to low level. The write enable signal WE changes to high level, the write transistor N13 becomes conductive, the data “0” of the write data line WDL is the read bit line RBL, and the data “1” of the inverted write data line WDLB is the direct write bit line WBL. Is transmitted to. As the read word line RWL and the write word line WWL change to high level, the data of the read bit line RBL and the write bit line WBL are written to the storage nodes V1 and V2 of the SRAM cell.

  The write enable signal WE, the read word line RWL, and the write word line WWL change to a low level. The precharge signal PC changes to low level, the inverted precharge signal PCB changes to high level, the read bit line RBL is precharged to VDD2, the write bit line WBL is precharged to ground potential, and the read data line RDL is precharged to VDD. .

  In the “1” writing shown in FIG. 9D, the precharge signal PC changes to high level and the inverted precharge signal PCB changes to low level. The write enable signal WE changes to a high level, the write transistor N13 becomes conductive, the data “1” of the write data line WDL becomes the read bit line RBL, and the data “0” of the inverted write data line WDLB becomes the direct write bit line WBL. Is transmitted to. As the read word line RWL and the write word line WWL change to high level, the data of the read bit line RBL and the write bit line WBL are written to the storage nodes V1 and V2 of the SRAM cell.

  The write enable signal WE, the read word line RWL, and the write word line WWL change to a low level. The precharge signal PC changes to low level, the inverted precharge signal PCB changes to high level, the read bit line RBL is precharged to VDD2, the write bit line WBL is precharged to ground potential, and the read data line RDL is precharged to VDD. .

  In this embodiment, it is possible to operate the SRAM cell at a low voltage and at a high speed, and obtain a sense amplifier that reads data by a read bit line and writes data by a read bit line and a write bit line.

  Another sense amplifier will be described as a third embodiment of the present invention with reference to FIGS. 10 shows a circuit diagram of the sense amplifier SA3, FIG. 11 shows a circuit diagram of the sense amplifier SA4, and FIG. 12 shows operation waveforms of the sense amplifiers SA3 and SA4.

  FIG. 10 shows a circuit configuration of the sense amplifier SA3. As compared with the sense amplifier SA1 in the second embodiment, the sense amplifier SA3 is added with an inverted read enable signal REB as a control signal. Of the input of the NOR circuit NR1 to which the precharge signal PC is input in the sense amplifier SA1, the gate of the precharge transistor N14, and the gate of the transistor P13, an additional inversion is added to the input of the NOR circuit NR1 and the gate of the transistor P13. A read enable signal REB is input instead.

  By using the inverted read enable signal REB as a control signal instead of the inverted precharge signal PCB, the operation of the NOR circuit NR1 and the transistor P13 during writing is stopped. The NOR circuit outputs a low level at the time of writing, the reading transistor N12 is turned off, and as a result, the reading data line RDL is not discharged. Further, the transistor P13 is also off, and an effect of reducing the current during writing can be obtained.

  As a circuit configuration of the sense amplifier SA3, an inverted read enable signal REB and a read bit line RBL are input to the NOR circuit NR1. The inverted read enable signal REB is at a low level during reading and is at a high level other than reading. The NOR circuit NR1 inverts the data of the read bit line RBL at the time of reading and outputs it to the transistor N12 to control on / off, and otherwise outputs a low level to turn off the transistor N12.

  The transistor P13 receives the inverted read enable signal REB at its gate and is turned on only at the time of reading, and works to raise the read bit line RBL to a high level. Since the connection of other circuit elements is the same as that of the sense amplifier SA1, detailed description of the circuit connection is omitted.

  The operation of the sense amplifier SA3 will be described. At the time of reading data from the SRAM cell, the inverted read enable signal REB is at a low level, and the NOR circuit NR1 inverts the data on the read bit line RBL and outputs it to the gate of the read transistor N12. By turning on / off the read transistor N12, data is transmitted to the read data line RDL to read data of the SRAM cell. On the other hand, at the time of writing, the write enable signal WE is at a high level, the data on the write data line WDL is transmitted to the read bit line RBL by the write transistor N13, and the inverted data is transmitted to the write bit line WBL connected to the inverted data line WDLB. Is transmitted and written to the SRAM cell from each bit line.

  The precharge transistors P12 and N14 have a precharge signal PC at a low level and an inverted precharge signal PCB at a high level when reading and writing are not performed, and precharge the read bit line RBL to VDD2. Of the two precharging transistors, N14 can be omitted. In this case, the inverted precharge signal PCB can also be omitted.

  In the read operation, the inverted read enable signal REB is at a low level, the transistor P13 is turned on, and the transistor for reinforcing the high level of the read bit line RBL to prevent malfunction. However, since the current flows even when the read bit line RBL is at the low level, the channel length of the transistor is increased, the driving capability is decreased, and the low level of the read bit line RBL is not increased. . Further, the read data line RDL and the write data line WDL can be integrated into an input / output data line DL. At this time, the read transistor N12 and the write transistor N13 may be connected to the data line DL instead of the read data line RDL and the write data line WDL.

  Next, the sense amplifier SA4 will be described. SA4 is an improved version of the sense amplifier SA3. In the sense amplifier SA4, a transistor P15 is added to the configuration of the sense amplifier SA3. The transistor P15 has a drain, a source, and a gate connected to the source of the transistor P13, the power supply voltage VDD, and the output of the NOR circuit NR1, respectively. In the sense amplifier SA1, a current also flows from the transistor P13 when the SRAM cell is “0” read. When the read bit line RBL is at a low level, the output from the NOR circuit is fed back to turn off the transistor P15, thereby cutting off the current from the transistor P13. The transistor P15 is inserted to reinforce the high level when the read bit line RBL is at a high level, and is turned off when the read bit line RBL is at a low level, thereby cutting off the current. Further, the position where the transistor P15 is inserted may be exchanged with P13.

  The sense amplifier SA4 has the same circuit configuration as that of the sense amplifier SA3 except that the transistor P15 is added. Also in the operation, a small current flows in the sense amplifier SA3 when the read bit line is at a low level. The only difference is in the point of complete interruption, and the other operations are the same, so that the description of the circuit configuration and its operation is omitted.

  FIG. 12 shows (a) “0” read, (b) “1” read, (c) “0” write, and (d) “1” write operation waveforms of the sense amplifiers SA3 and SA4. In FIGS. 12A, 12B, 12C, and 12D, the precharge voltage of the write bit line WBL while the write word line WWL is at the low level is the ground potential GND. However, the present invention is not limited to this. Absent. As a modification of the sense amplifiers SA3 and SA4, the read data line RDL and the write data line can be combined into a data line. In this configuration, the read data line RDL at the time of reading may be replaced with the data line DL, and the write data line WDL at the time of writing may be replaced with the data line DL.

  In “0” reading shown in FIG. 12A, the precharge signal PC changes to a high level, and the inverted precharge signal PCB and the inverted read enable signal REB change to a low level. The read word line RWL changes to high level, and the access transistor N3 becomes conductive. The read bit line RBL is discharged through the drive transistor N1 of the SRAM cell and falls from the precharge voltage VDD2 to a low level. The NOR circuit outputs a high level, the read transistor N12 is turned on, and data “0” is read to the read data line RDL.

  The read word line RWL changes to low level, the precharge signal PC changes to low level, the inverted precharge signal PCB and the inverted read enable signal REB change to high level, the read bit line RBL changes to VDD2, and the read data line RDL changes to Precharged to VDD. The write enable signal WE and the write word line WWL for the write system do not operate in the read cycle.

  In “1” reading shown in FIG. 12B, the precharge signal PC changes to a high level, and the inverted precharge signal PCB and the inverted read enable signal REB change to a low level. The read word line RWL changes to high level, and the access transistor N3 becomes conductive. At this time, the storage node V1 is at the high level, and the read bit line RBL is not changed and the “1” level is read as it is. Here, the read bit line RBL is gradually pulled up by the transistor P13 of the sense amplifier and changes from the precharge voltage VDD2 to the power supply voltage VDD. The NOR circuit NR1 outputs a low level, the read transistor N12 is OFF, the read data line RDL maintains the precharge voltage VDD, and data “1” is read.

  The read word line RWL changes to low level, the precharge signal PC changes to low level, the inverted precharge signal PCB and the inverted read enable signal REB change to high level, the read bit line RBL changes to VDD2, and the read data line RDL changes to Precharged to VDD. The write enable signal WE and the write word line WWL for the write system do not operate in the read cycle.

  In “0” writing shown in FIG. 12C, the precharge signal PC changes to a high level and the inverted precharge signal PCB changes to a low level. The write enable signal WE changes to high level, the write transistor N13 becomes conductive, the data “0” of the write data line WDL is the read bit line RBL, and the data “1” of the inverted write data line WDLB is the direct write bit line WBL. Is transmitted to. As the read word line RWL and the write word line WWL change to high level, the data of the read bit line RBL and the write bit line WBL are written to the storage nodes V1 and V2 of the SRAM cell.

  The write enable signal WE, the read word line RWL, and the write word line WWL change to a low level. The precharge signal PC changes to low level, the inverted precharge signal PCB changes to high level, the read bit line RBL is precharged to VDD2, the write bit line WBL is precharged to ground potential, and the read data line RDL is precharged to VDD. . The inverted read enable signal REB, which is a read signal, does not change during this time.

  In the “1” writing shown in FIG. 12D, the precharge signal PC changes to a high level and the inverted precharge signal PCB changes to a low level. The write enable signal WE changes to a high level, the write transistor N13 becomes conductive, the data “1” of the write data line WDL becomes the read bit line RBL, and the data “0” of the inverted write data line WDLB becomes the direct write bit line WBL. Is transmitted to. As the read word line RWL and the write word line WWL change to high level, the data of the read bit line RBL and the write bit line WBL are written to the storage nodes V1 and V2 of the SRAM cell.

  The write enable signal WE, the read word line RWL, and the write word line WWL change to a low level. The precharge signal PC changes to low level, the inverted precharge signal PCB changes to high level, the read bit line RBL is precharged to VDD2, the write bit line WBL is precharged to ground potential, and the read data line RDL is precharged to VDD. . The inverted read enable signal REB, which is a read signal, does not change during this time.

  In this embodiment, it is possible to operate the SRAM cell at a low voltage and at a high speed, and obtain a sense amplifier that reads data by a read bit line and writes data by a read bit line and a write bit line.

  As Embodiment 4 of the present application, the configuration of a precharge voltage VDD2 generation circuit, a sub word driver circuit, and a semiconductor memory device including these will be described with reference to FIGS. FIG. 13 is a circuit diagram of the VDD2 generating circuit, and FIG. 14 is an overall view (a) and a memory block diagram (b) of the semiconductor memory device. FIG. 15 is a circuit diagram of the sub word driver SWD1, and FIG. 16 is a memory block diagram to which the sub word driver SWD1 is applied. FIG. 17 is a circuit diagram of the sub word driver SWD2, and FIG. 18 is a memory block diagram to which the sub word driver SWD2 is applied.

  The VDD2 generation circuit shown in FIG. 13 generates a precharge voltage VDD2. The precharge voltage VDD2 is lower than the power supply voltage VDD by the threshold voltage of the transistor. The advantage of setting the precharge voltage to VDD2 is that the potential rise of the storage node V1 is suppressed and the SNM is improved at the time of reading “0” of the SRAM cell, and the potential difference to the threshold voltage of the NOR circuit of the sense amplifier is further reduced. This makes it possible to operate at high speed.

  In the VDD2 generation circuit, transistors N31 and N32 are connected between the power supply voltage VDD and the ground potential GND, and the drain, source, and gate of the transistor N31 are connected to the power supply voltage VDD, the drain of the transistor N32, and the power supply voltage VDD, respectively. The The drain, source, and gate of the transistor N32 are connected to the source of the transistor N31, the ground potential GND, and the power supply voltage VDD, respectively. The precharge voltage VDD2 is output from the source of the connected transistor N31 and the drain of N32.

  At this time, the transistor N32 is a transistor for maintaining the level, and since the driving capability is not required, the channel length L is increased. In this embodiment, the threshold voltage VDD2 is lowered by one step from the power supply voltage. However, any voltage value lower than the power supply voltage VDD and higher than the threshold voltage of the second inverter circuit constituting the SRAM cell may be used. For example, the threshold voltage may be a positive voltage. For example, a transistor having the same threshold as that of the access transistor N3 can be used as N31.

  The output voltage VDD2 of the VDD2 generation circuit is wired over the entire chip. For this reason, the VDD2 generation circuit can be divided and arranged in a large number of transistors. For example, it can be distributed and arranged in the control unit 14 of the memory block of the semiconductor memory device of FIG.

  Next, the overall configuration (a) and memory block (b) of the semiconductor memory device shown in FIG. 14 will be described. The semiconductor memory device includes a main word driver 2, a Y decoder / data input / output unit 3 and a control block 4 around a memory array in which M blocks and N columns are arranged in a memory block 1 having an (m word) x (n bit) configuration. Consists of The memory block 1 includes a sub-word driver 12, a sense amplifier 13, and a control unit 14 around the memory cell array 11 of (m words) × (n bits).

  The inverted main word line WLB is wired as a main wiring to all the memory blocks in the horizontal direction in the figure, and at the intersection of the inverted read block signal RPB and the inverted write block signal WPB wired in the vertical direction by the sub word driver circuit. A sub word line dedicated to each memory block is generated and supplied to the gate of the access transistor of the SRAM cell. Further, the signal precharge signal PC for the sense amplifier, the write enable signal WE, and the like are also wired to all the memory blocks as the horizontal main wiring.

  The sub word drivers 12 arranged in m are inputted with the inverted main word line WLB from the main word driver 2, the inverted read block signal RPB, and the inverted write block signal WPB, and select one word line of the memory cell array 11. To do. The n sense amplifiers 13 are arranged to amplify a signal of a bit line connected to the memory cell array 11 and transmit it to the data line of the Y decoder / data input / output unit 3 at the time of reading. Conversely, when writing, a signal from the data line is written into the memory cell array. The control unit 14 is provided with a wiring portion of a precharge signal PC, a write enable signal WE, an inverted write enable signal WEB, an inverted read block signal RPB, and an inverted write block signal WPB, or an amplifier circuit for these control signals.

  Now, the sub word driver SWD1 shown in FIG. 15 will be described. The sub word driver SWD1 receives the inverted main word signal WLB, the inverted read block signal RPB, and the inverted write block signal WPB, and outputs the read word line RWL and the write word line WWL. When the inverted main word signal WLB and the inverted read block signal RPB are input to the NOR circuit NR11 and both are input at the low level, the one read word line RWL is set to the high level as the selected sub word line, and the input signal is When the level is high, the read word line RWL is output as a low level.

  When the inverted main word signal WLB and the inverted write block signal WPB are input to the NOR circuit NR12 and both are input at the low level, the one write word line WWL is set to the high level as the selected sub word line, and the input signal is In the case of the high level, the write word line WWL is outputted as the low level.

  FIG. 16 shows a memory block to which the sub word driver SWD1 is applied. Here, the SRAM cell 1 according to the first embodiment of the present invention is used as the memory cell, and the sense amplifier is, for example, the SA4 of the present application. However, it is not limited to the configuration of the present embodiment, and it is needless to say that various combinations are possible.

  There are m subword drivers SWD1, and an inverted main word signal having each address address, an inverted read block signal RPB, and an inverted write block signal WPB are input. When the respective address addresses match, one read word line RWL is selected for reading, one read word line RWL and one write word line WWL are selected for writing, and one word line is selected. The N sense amplifiers SA4 are arranged to exchange data with n SRAM cells connected to the selected word line. At the time of reading, the data of the SRAM cell is read to the data line, and at the time of writing, the data from the data line is written to the SRAM cell.

  Next, another embodiment of the sub word driver will be described. The sub-word driver SWD2 shown in FIG. 17 is configured by removing one of the load transistors of the NOR circuit constituting the sub-word driver and configuring the NOR circuit with three transistors. The NOR circuit for generating the read word line RWL is composed of three transistors: a load transistor P21 and drive transistors N21 and N22. The NOR circuit for generating the write word line WWL is composed of three transistors: a load transistor P23 and drive transistors N23 and N24.

  The drain, source, and gate of the transistor P21 are connected to the read word line RWL, the read block signal RP, and the inverted main word signal WLB, respectively. The drain, source, and gate of the transistor N21 are connected to the read word line RWL, the ground potential GND, and the inverted main word signal WLB, respectively. The drain, source, and gate of the transistor N22 are connected to the read word line RWL, the ground potential, and the inverted read block signal RPB, respectively. The drains of the three transistors are connected in common to generate a read word line RWL.

  The drain, source, and gate of the transistor P23 are connected to the write word line WWL, the write block signal WP, and the inverted main word signal WLB, respectively. The drain, source, and gate of the transistor N23 are connected to the write word line WWL, the ground potential GND, and the inverted main word signal WLB, respectively. The drain, source, and gate of the transistor N24 are connected to the write word line WWL, the ground potential GND, and the inverted read block signal RPB, respectively. The drains of the three transistors are connected in common to generate an output read word line RWL.

  When the read word line RWL is read, one word line is selected when both the inverted main word signal WLB including the address address and the inverted read block signal RPB are at the low level and the read block signal RP is at the high level. At the time of writing, one word line is selected as the write word line WWL when both the inverted main word signal WLB including the address address and the inverted write block signal WPB are at the low level and the write block signal WP is at the high level.

  Here, the read block signal RP and the write block signal WP are signals obtained by inverting the inverted read block signal RPB and the inverted write block signal WPB by the inverter circuits IV11 and IV12, respectively. FIG. 18 shows a memory block to which the sub word driver SWD2 is applied.

  In FIG. 18, the sub-word driver SWD2 is wired to each memory block using the inverted read block signal RPB and the inverted write block signal WPB as the main wiring, and is an inverter that inverts the inverted read block signal RPB and the inverted write block signal WPB. The circuits IV11 and IV12 are arranged in the control unit 34 of each memory block, and a read enable signal RE and a write enable signal WE dedicated to each memory block are supplied to the sub word driver of the memory block. At this time, the VDD2 generation circuit for generating the precharge voltage is divided and arranged in the control unit 34 of each memory block.

  In FIG. 18, SWD2 is applied as a sub-word driver, and an inverter circuit that generates a read block signal RP and a write block signal WP used for SWD2 is arranged in the control unit 34 of each memory block, and is read into each memory block. A block signal RP and a write block signal WP are supplied. Other arrangements and signal wirings are the same as those in FIG.

  In this embodiment, a semiconductor memory device capable of operating at high speed with a low power supply voltage without data destruction during reading can be obtained by optimally combining memory cells, sense amplifiers, and sub-decoder driver circuits.

  As Example 5, an SRAM cell 2 used in the present invention will be described with reference to FIGS. FIG. 19 is a diagram showing a circuit configuration of the SRAM cell 2. FIG. 20 shows operation waveforms at the time of (a) “0” read, (b) “1” read, (c) “0” write, and (d) “1” write in the SRAM cell 2.

  The SRAM cell 2 shown in FIG. 19 is different from the SRAM cell 1 of the first embodiment in that the write bit line WBL is fixed at the ground potential GND. The SRAM cell 2 includes a first inverter circuit that outputs the storage node V1, a second inverter circuit that outputs the storage node V2, and an access transistor N3 connected between the read bit line and the storage node V1. And an access transistor N4 connected between the ground potential and the storage node V2. The first and second inverter circuits are connected in a loop.

  The load transistors of the first and second inverter circuits and the first and second access transistors have substantially the same drive capability. The threshold voltage of the second inverter circuit is set higher than the threshold voltage of the first inverter circuit by making the drive capability of the drive transistor of the second inverter circuit smaller than the drive capability of the drive transistor of the first inverter circuit. To do. Further, the precharge voltage of the read bit line is set to VDD2 lower than the power supply voltage and higher than the threshold voltage of the second inverter circuit. Since the constituent elements of the first embodiment are the same, the same reference numerals as those of the first embodiment are used, and the detailed description thereof is omitted.

  The operation will be described with reference to FIG. FIG. 20 shows operation waveforms of (a) “0” read, (b) “1” read, (c) “0” write, and (d) “1” write. In the case of FIG. 20 (a) “0” read and (b) “1” read, “0” or “1” of the storage node V1 using the read word line RWL, read bit line RBL, and access transistor N3. Is read to the read bit line RBL. In the read operation of the SRAM cell 1 of the first embodiment, the write bit line WBL is not operating. For this reason, the read operation of the SRAM cell 2 of the present embodiment shown in FIGS. 20A and 20B is the same as the read operation of the SRAM cell 1 of the first embodiment shown in FIGS. 6A and 6B. Therefore, the description thereof is omitted.

  In the write operation of the first embodiment, data is written in the SRAM cell 1 by complementary data input from the read bit line RBL and the write bit line WBL. However, in the write operation of the fifth embodiment, since the write bit line WBL is fixed to the ground potential, the write word line WWL is set to a short one-shot pulse, and the storage node V2 is reset to the low level “0” before reading. This is done by writing the write level of the bit line RBL to the storage node V1.

  In the case of “0” writing in FIG. 20C, both the read word line RWL and the write word line WWL are activated and become high level “1”. The access transistors N3 and N4 are both turned on, the storage node V1 and the read bit line RBL are conducted, and the low level “0” of the read bit line RBL is written into the storage node V1. On the other hand, the storage node V2 is at an intermediate level because the transistor P2 and the transistor N4 are turned on together. Here, the write word line WWL which is a one-shot pulse becomes low level “0”, and the transistor N4 is turned off, whereby the storage node V2 is pulled up to high level “1”, the storage node V1 is set to “0”, and the storage node V2 "1" is written in After the writing is completed, the read word line RWL becomes low level “0”, and then the read bit line RBL is precharged to high level “1”, and the “0” write operation is completed.

  In the case of writing “1” in FIG. 20D, both the read word line RWL and the write word line WWL are activated and become high level “1”. The access transistors N3 and N4 are both turned on, the storage node V1 and the read bit line RBL become conductive, and the high level “1” of the read bit line RBL is written into the storage node V1. On the other hand, the storage node V2 is set to the ground potential GND by the access transistor N4, and a low level “0” is written to the storage node V2. Here, since the transistor P2 is in the OFF state, the storage node V2 is written with the low level “0” without being raised to the intermediate level.

  During the period when the write word line WWL is at the high level, “1” is written to the storage node V1 and “0” is written to the storage node V2. Only the write word line WWL is set to the low level “0” to turn off the transistor N4. Subsequently, the read word line RWL is set to the low level “0”, the read bit line RBL is precharged to the high level “1”, and the “1” write operation is completed.

  The SRAM cell 2 of the present embodiment is a memory cell in which the write bit line WBL is fixed to the ground potential in the SRAM cell 1 of the first embodiment, and the write operation and the read operation are performed only by the read bit line RBL. For this reason, sense amplifiers used in the SRAM cell 2 are modified sense amplifiers of the sense amplifiers SA1 and SA2 of the second embodiment and the sense amplifiers SA3 and SA4 of the third embodiment. As the sense amplifier used in the SRAM cell 2, a sense amplifier in which the write bit line WBL and the inverted write data line WDLB are omitted from the circuit of the sense amplifiers SA1, 2, 3, 4 can be used.

  In the sense amplifier in which the write bit line WBL and the inverted write data line WDLB are omitted, data from the memory cell is transmitted from the NOR circuit NR1 to the read data line RDL at the time of reading. At the time of writing, data from the write data line WDL can be written via the read bit line RBL. Similarly, it is needless to say that the configurations of the precharge voltage VDD2 generation circuit, the sub word driver circuit, and the memory circuit device described in the fourth embodiment are applicable. It will be understood that the peripheral circuits of the second, third, and fourth embodiments can be used as they are or in a modification thereof in the SRAM cell 2 of the present embodiment.

  In this embodiment, the SRAM cell 2 includes a first inverter circuit that outputs the storage node V1, a second inverter circuit that outputs the storage node V2, and a read bit line and the storage node V1. The access transistor N3 is connected, and the access transistor N4 is connected between the ground potential and the storage node V2. The first and second inverter circuits are connected in a loop, and the load transistors of the first and second inverter circuits and the first and second access transistors have substantially the same drive capability. The threshold voltage of the second inverter circuit is set higher than the threshold voltage of the first inverter circuit by making the drive capability of the drive transistor of the second inverter circuit smaller than the drive capability of the drive transistor of the first inverter circuit. To do.

  Further, the precharge voltage of the read bit line is set to VDD2 lower than the power supply voltage and higher than the threshold voltage of the second inverter circuit. With these structures, memory cells are prevented from being destroyed during reading, and high-speed reading is performed. Furthermore, high speed writing can be performed by setting the access transistors to have the same drive capability. An imbalanced SRAM cell capable of preventing a memory cell from being destroyed during reading and capable of performing high-speed reading and writing is obtained.

  Although the present invention has been specifically described above based on the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof.

It is a circuit diagram of a conventional 6-transistor SRAM cell. It is explanatory drawing of SNM which shows the stable operation | movement in the conventional SRAM cell. It is a figure which shows the channel length dependence of the transistor of SNM in the conventional SRAM cell. It is a circuit diagram of SRAM cell 1 of the present application. It is explanatory drawing of SNM by the difference in a SRAM cell system. It is an operation waveform of the SRAM cell 1 in the present application, and shows (a) “0” read, (b) “1” read, (c) “0” write, and (d) “1” write. It is a circuit diagram of sense amplifier SA1 of this application. It is a circuit diagram of sense amplifier SA2 of the present application. It is an operation waveform of the sense amplifiers SA1 and SA2 of the present application, and shows (a) “0” read, (b) “1” read, (c) “0” write, and (d) “1” write. It is a circuit diagram of sense amplifier SA3 of the present application. It is a circuit diagram of sense amplifier SA4 of the present application. It is an operation waveform of the sense amplifiers SA3 and SA4 of the present application, and shows (a) “0” read, (b) “1” read, (c) “0” write, and (d) “1” write. It is a circuit diagram of a VDD2 generation circuit. 1A is a general view of a semiconductor memory device, and FIG. It is a circuit diagram of subword driver SWD1. It is a memory block diagram to which a sub word driver SWD1 is applied. It is a circuit diagram of subword driver SWD2. It is a memory block diagram to which a sub word driver SWD2 is applied. It is a circuit diagram of SRAM cell 2 of the present application. It is an operation waveform of the SRAM cell 2 in the present application, and shows (a) “0” read, (b) “1” read, (c) “0” write, and (d) “1” write.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory block 2 Main word driver 3 Y decoder 4 Control block 14, 34 Control block 11 Memory cell array 12, 22, 32 Sub word driver 13 Sense amplifier P1, P2, P12, P13, P15, P21, P23 PMOS transistor N1, N2, N3, N4, N12, N13, N14, N21, N22, N23, N24 NMOS transistor V1, V2 Storage node IV11, IV12 Inverter circuit NR1, NR11, NR12 NOR circuit

Claims (17)

  In a semiconductor memory device, a first inverter circuit that outputs a first storage node, a second inverter circuit that outputs a second storage node, and between a read bit line and the first storage node And a second access transistor connected between a write bit line and the second storage node, and the first and second inverter circuits are connected to each other. Are connected in a loop, and the load transistors of the first and second inverter circuits and the first and second access transistors have substantially the same drive capability, respectively, and the drive of the second inverter circuit The drive capability of the transistor is made smaller than the drive capability of the drive transistor of the first inverter circuit, and the threshold voltage of the second inverter circuit is The semiconductor memory device characterized by comprising a serial set high memory cell than the threshold voltage of the first inverter circuit.   The read bit line is precharged to a precharge voltage value higher than a threshold voltage of the second inverter circuit and lower than a power supply voltage of the first inverter circuit. Semiconductor memory device.   3. The semiconductor memory device according to claim 2, wherein the precharge voltage is lower than the power supply voltage by a threshold voltage value of the first access transistor.   3. The semiconductor memory device according to claim 2, wherein the write bit line is precharged to a ground potential.   The semiconductor memory device according to claim 2, wherein the write bit line is connected to a ground potential.   In a semiconductor memory device, a first inverter circuit that outputs a first storage node, a second inverter circuit that outputs a second storage node, and between a read bit line and the first storage node And a second access transistor connected between a write bit line and the second storage node, the first and second memory cells having a first access transistor connected to the first storage transistor, and a second access transistor connected between the write bit line and the second storage node. Are connected to each other in a loop, the threshold voltage of the second inverter circuit is set higher than the threshold voltage of the first inverter circuit, and the read bit line is higher than the threshold voltage of the second inverter circuit. A semiconductor memory device, wherein the semiconductor memory device is precharged and precharged to a precharge voltage value that is high and lower than a power supply voltage of the second inverter circuit.   A sense amplifier that transmits data to and from the memory cell inverts and outputs data from a read bit line and a write bit line, a data line that transmits data to and from an input / output circuit, and an inverted write data line. A NOR circuit; data read means for transmitting an output of the NOR circuit to the data line; and write means for transmitting data from the data line to the read bit line by a write signal, the write bit line 7. The semiconductor memory device according to claim 1, wherein is connected to the inverted write data line.   The sense amplifier includes precharge means for precharging the read bit line by a precharge signal, and reinforcing means for maintaining the read bit line at a high level when the read bit line is at a high level in a read operation. The semiconductor memory device according to claim 7, further comprising:   9. The semiconductor memory device according to claim 8, wherein the precharge means precharges the read bit line to a voltage value lower than a power supply voltage by a threshold voltage of the transistor.   8. The semiconductor memory device according to claim 7, wherein the NOR circuit receives an inverted read enable signal and transmits data from the read bit line to the data line at the time of reading.   A sense amplifier that transmits data to and from the memory cell is connected to a read bit line that is precharged to a voltage value lower than the power supply voltage by a threshold voltage of the transistor and a write line that is precharged to a ground potential. Sometimes the memory cell data read to the read bit line is read to the data line via the NOR circuit controlled by the inverted read signal, and at the write time, the data from the data line is read to the read bit line by the write signal. 7. The transfer according to claim 1, wherein inverted data from an inverted write data line is transmitted to the write bit line, and data is written to the memory cell from the read bit line and the write bit line. Semiconductor memory device.   A sub word driver that generates a read word line signal from the inverted main word signal, the read block signal, and the inverted read block signal, and generates a write word line signal from the inverted main word signal, the write block signal, and the inverted write block signal The semiconductor memory device according to claim 1, further comprising a circuit.   The sub-word driver circuit includes a first inverter circuit that receives the inverted main word signal and outputs the read word line signal, and a first transistor connected to an output of the first inverter circuit, The first inverter circuit is formed between the read block signal and a ground potential, and the drain, source, and gate of the first transistor are the output of the first inverter circuit, the ground potential, and the inverted read block, respectively. The semiconductor memory device according to claim 12, wherein the semiconductor memory device is connected to a signal.   The sub-word driver circuit includes a second inverter circuit that receives the inverted main word signal and outputs the write word line signal, and a second transistor connected to the output of the second inverter circuit, The second inverter circuit is formed between the write block signal and the ground potential, and the drain, source, and gate of the second transistor are the output of the second inverter circuit, the ground potential, and the inverted write block, respectively. The semiconductor memory device according to claim 12, wherein the semiconductor memory device is connected to a signal.   The memory cells are arranged in a matrix of m rows and n columns (m and n are positive integers), and m subword drivers are arranged on one side in the vertical direction and n are arranged on one side in the horizontal direction. A plurality of sense amplifiers are arranged, and the sub-word driver generates a read word line signal from the inverted main word signal, the read block signal and the inverted read block signal, and further, the inverted main word signal and the write block signal Then, a write word line signal is generated according to the inverted write block signal and supplied to the memory cell, and the sense amplifier inverts and outputs the data from the read bit line, and outputs the NOR circuit to the data line. Data read means for transmitting and data from the data line by the write signal are read out. The semiconductor memory according to claim 1 or claim 6 characterized by comprising a writing means for transmitting bets line, the.   The read bit line is precharged to a precharge voltage higher than a threshold voltage of the second inverter circuit and lower than a power supply voltage of the first inverter circuit, and the generation circuit for generating the precharge voltage is the memory 16. The semiconductor memory device according to claim 15, wherein the semiconductor memory device is divided and arranged in a control unit serving as an intersection where the sub word driver and the sense amplifier arranged around the cell array are arranged. An inverter circuit that inverts the inverted read block signal and the inverted write block signal input to the sub word driver and generates the read block signal and the write block signal is an intersection where the sub word driver and the sense amplifier are arranged. The semiconductor memory device according to claim 15, wherein the read block signal and the write block signal are supplied to the sub-word driver in a memory cell block.

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