JP2009048671A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device which improves both write characteristics and tolerance against disturb caused by variations of threshold voltage or the like and reduction of voltage, and suppresses increase in area, increase in power and deterioration of speed property. <P>SOLUTION: The semiconductor storage device is provided with: a memory cell containing a first inverter IV1 to which an input end and output end are connected to cross respectively and a second inverter IV2; a reference supply wiring VSSCL which supplies reference voltage VSSC to the first inverter IV1; a reference supply wiring VSSCR which supplies reference voltage VSSC to the second inverter IV2; bit lines BL and /BL connected to the memory cell; and transfer gates TL1 and TL2 and transfer gates TR1 and TR2 which control impedance in the reference supply wirings VSSCL and VSSCR according to voltages of bit lines BL and /BL respectively. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, for example, a static random access memory (hereinafter referred to as SRAM).

  Current SRAM memory cells (hereinafter, SRAM cells) are mainly CMOS 6-transistor cells composed of 6 MOS transistors. This consists of a flip-flop composed of two CMOS inverters and two transfer gates connecting both nodes of the flip-flop to a bit line pair. The SRAM is characterized in that data storage can be stably performed because data storage is performed statically by a flip-flop.

  However, in order to improve the performance of an LSI (Large Scale Integrated circuit) and increase the number of mounted elements, the miniaturization of elements has progressed, and the power supply voltage has been scaled accordingly. Further, with the miniaturization of elements, the phenomenon that the threshold voltage Vth of the transistor to be uniformly controlled varies randomly for each element has become remarkable.

  One of indexes indicating the operation margin of the SRAM is a static noise margin (SNM). SNM is a so-called SRAM cell spectacle in which input / output characteristics of two inverters constituting a flip-flop are overlapped when a cell word line is in a selected state, that is, a transfer gate transistor is turned on. It is well known as a characteristic and is a voltage margin during operation. Even if the input / output characteristics are deviated due to noise, there is a margin for SNM before the spectacle characteristics are destroyed and the data is destroyed. The greater the SNM, the more stable the data retention characteristics of the cell. The difference from normal inverter characteristics is that when the word line is turned on, the potential on the low (“L”) level is raised by the level of the bit line (usually high (“H”) level) connected via the transfer gate In other words, the intermediate potential is determined by the ratio of the driving forces between the transfer gate and the driver (N-channel MOS transistor constituting the inverter).

  As described above, when the power supply voltage is scaled, the eyeglass characteristics are also scaled as a whole, and the SNM is naturally reduced. Furthermore, if the characteristics of the six transistors constituting the cell vary due to random variations in the threshold voltage Vth, the two inverter characteristics constituting the flip-flop will deviate from each other. As a result, the spectacle characteristics become asymmetric, and the SNM of the SRAM cell is determined by the smaller one of the spectacle characteristics. If the power supply voltage is scaled, and the variation of the threshold voltage Vth becomes larger than a certain level and varies with a distribution, as a result, there will be a cell in which the SNM is not ensured, that is, the glasses characteristic is not applied. The probability increases as the capacity of the SRAM increases, that is, as the number of SRAM cells increases. In such a cell, if the word line is in a selected state and the transfer gate is turned on, the stored data may be destroyed by that alone, causing a problem that normal operation as a memory cannot be performed.

  There are various possible array architectures in SRAM. In order to provide flexibility in I / O width in a compilable SRAM mixed in ASIC or the like and having flexibility in the number of bits and configuration, it is shown in FIG. As described above, it is general that the array is configured for each I / O in consideration of area efficiency, speed and power performance. In such a case, when a certain row is selected, the cell at the cross point with the column selected for each I / O becomes the actually selected cell, and data is written and read. Therefore, in a cell that is in the same row as the selected cell but whose column is not selected, the word line is turned on, but data reading / writing is not performed, and data must be retained.

  Consider a case where there is a cell in which the SNM has failed as described above. First, at the time of writing, since new data is written in the selected cell in the selected column, the original data becomes unnecessary, and as a result, there is no worry about data destruction. However, all the cells in the non-selected column with the word line turned on may cause data destruction. On the other hand, at the time of reading, data may be destroyed in all cells that are in the selected row and the word line is turned on regardless of whether the column is selected or not. These are called disturb failures.

  In order to avoid these problems, a proposal (for example, Non-Patent Document 1) for controlling a cell-related voltage has been made. This proposal is to change the power supply voltage VDDC of the inverter constituting the flip-flop of the cell depending on the mode and the column selection state.

In Non-Patent Document 1, an example is given in which the power supply voltage VDDC is higher than the voltage VDD in order to avoid disturb. However, when there is no problem with the disturb characteristics and the write characteristics are severe, read and write In the non-selected column, the power supply voltage VDDC is set to the voltage VDD level, and the power supply voltage VDDC of the selected column can be lowered only during writing. As such an example, there is one proposed by Non-Patent Document 2. In this case, the power supply voltage VDDC of the selected column is opened at the time of writing. Since the current is discharged from the power supply voltage VDDC by the write cell, the voltage level is lowered and the write characteristic is improved. However, in this case, the power supply voltage VDDC of the inverter on the node side which is set to “1” level after writing is not supplied with power, so that data inversion for writing is facilitated, but cell latching is not possible. There is concern that it will become stable. In addition, in order to reduce power and maintain speed performance, it is necessary to reduce the capacity of the node to be charged / discharged and to reduce the voltage level difference to be changed when the power supply voltage VDDC level decreases during writing. What is desirable is the same as in Non-Patent Document 1.
K. Zhang et al., “A 3-GHz 70Mb SRAM in 65nm CMOS Technology with Integrated Column-Based Dynamic Power Supply,” ISSCC 2005 Digest of Technical Papers, pp.474-475, 611. Masanao Yamaoka et al., “Low-Power Embedded SRAM Modules with Expanded Margins for Writing,” ISSCC 2005 Digest of Technical Papers, pp. 480-481, 611.

  The present invention achieves both improved resistance to disturbance caused by various variations of threshold voltage and lowering of voltage and improvement of write characteristics, and suppresses area increase, power increase and speed characteristic deterioration caused thereby. An object of the present invention is to provide a semiconductor memory device capable of performing

According to one embodiment of the present invention, a semiconductor memory device includes a memory cell including first and second inverters each having an input terminal and an output terminal connected to each other, and a first power source that supplies power to the first inverter. Power supply wiring, and second power supply wiring for supplying power to the second inverter,
A first and second bit line connected to the memory cell; and a control circuit for controlling impedances of the first and second power lines in accordance with a voltage of the first and second bit lines. It is characterized by doing.

  According to the present invention, it is possible to achieve both improvement in resistance to disturbances caused by various variations in threshold voltage and lowering of voltage and improvement in write characteristics, and suppress the increase in area, power and deterioration in speed characteristics. It is possible to provide a semiconductor memory device that can be used.

  Prior to describing the embodiments of the present invention, the related art of the present invention will be described.

  The inventor has proposed that the power levels of the left and right flip-flops of the cell are controlled independently on the left and right in accordance with the write data for the selected column at the time of writing (Japanese Patent Application No. 2006-146521). In this proposal, the power supply VDDCL, VDDCR, VSSCL, VSSCR (see FIG. 1) of both the left and right inverters of the SRAM cell which were controlled in common is controlled by controlling the voltage level of only one according to the write data (see FIG. 2 or FIG. 3 and FIG. 4 show control examples) to improve writing. As shown in FIG. 1, the SRAM cell is composed of load transistors LL and LR, driver transistors DL and DR, and pass transistors PL and PR. As shown in FIGS. 2, 3 and 4, the cell array has SRAM cells arranged in an array. In the figure, W is a write signal, add is a column selection signal, and D and / D are data complementary signals. By improving the writing characteristics, the potential difference in voltage control is reduced, leading to avoiding overhead in terms of power and speed characteristics.

  By the way, the above proposal is based on the premise that the flip-flop power supply of the cell is a separate wiring between the left and right inverters. FIG. 5 shows a connection example of the ground layout of the SRAM cell and the array wiring. In the figure, there is a PMOS transistor for the left and right inverters in the center, and the source thereof is the power supply voltage VDDC. In this example, the left and right power supply voltages VDDC are the same node, so they can be connected in common. It is.

  Considering this connection, in a miniaturized cell, a branch wiring is formed in one central second-layer metal, and is connected by extending left and right. This is because when the connection is made with the first layer metal from the source of the PMOS transistor to immediately below the second layer metal in the center, the portion indicated by A in FIG. This is because the distance is very close and NG. In this case, the layout of the second layer metal is as shown in FIG. However, in this case, the power supply voltage wiring VDDC of the second-layer metal is a bumpy wiring because it connects to the respective sources of the left and right PMOS transistors. As miniaturization progresses, especially when the pitch is strict and a plurality of wirings are wired in one direction as in a cell array, it is difficult to process bumpy wirings as shown in FIG. Proper processing, such as the proximity effect at the time of exposure, shorting of the convex part, opening of the concave part, shortening of the convex part, and increasing the risk of causing contact failure with the source part of the PMOS transistor Because it becomes difficult. Therefore, restrictions such as a wider line spacing may be imposed than the minimum design rule.

  Therefore, in order to arrange the fine wirings at a narrow pitch, as shown in FIG. 7B, the left and right power supply voltage wirings VDDC are wired independently, and regular together with the other bit lines and the reference power supply wiring VSS. If the vertical wiring is used, the processing is easier and the wiring can be formed with the minimum pitch. As a result, the total cell width may be able to be reduced in spite of the fact that there is more single wiring than in FIG. 7 (a), and this tendency is increasing with miniaturization. Therefore, as shown in FIG. 7B, in the cell in which the left and right power supply voltage wirings VDDC are originally separated, the previous proposal example is realized without specially changing the cell area or the wiring in the array. it can.

  In the cell layouts of FIGS. 7A and 7B, the reference power supply wiring VSS is connected separately from the reference power supply wiring VSSC connected to the left and right inverters of one cell. The power supply wiring VSSC is shared between the left and right adjacent cells. However, in order to secure the cell current, there are some cells in which the driver width of the NMOS transistor and the transfer transistor width (W) are increased. That is, this corresponds to an increase in the diffusion region width of the driver transistors DR and DL and the pass transistors PR and PL in FIG. In that case, as the transistor width is increased, the cell width is increased, and the layout may be such that the reference power supply line VSS is separated from the adjacent cells, as shown in FIGS. 8A and 8B. As shown.

  However, in these cases, a separate power supply level such as the power supply VDDH / L is required, or a control circuit in which logic is configured with write data or an address is added, and overhead due to increase in area and power due to this is not avoided.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

  In the above-described proposal, the cell power supply level is controlled by using a logic circuit for address and write data in order to avoid disturb and improve the write characteristics. In order to suppress the area and power overhead due to this, in the embodiment of the present invention, the impedance of the cell power supply is controlled using the voltage level of the bit line.

[First Embodiment]
First, a semiconductor memory device having an SRAM cell according to the first embodiment of the present invention will be described. In the present embodiment, an example of controlling the reference power supply wiring VSSCL / VSSCR supplied with the reference voltage VSSC of the SRAM cell will be described.

  FIG. 9A and FIG. 9B are circuit diagrams showing the configuration of the SRAM cell of the first embodiment.

  This SRAM cell has a first inverter circuit IV1, a second inverter circuit IV2, transfer gate transistors PL and PR, transfer gates TL1, TL2, TR1 and TR2, and a reference voltage (for example, ground voltage) VSSC supplied thereto. Power supply lines VSSCL and VSSCR and bit lines BL and / BL are provided.

  The first inverter circuit IV1 includes a load transistor LL composed of a P-channel MOS field effect transistor (hereinafter referred to as PMOS transistor) and a driver transistor DL composed of an N-channel MOS field effect transistor (hereinafter referred to as NMOS transistor). The drain of the load transistor LL is connected to the drain of the driver transistor DL. A power supply voltage VDD is supplied to the source of the load transistor LL. The source of the driver transistor DL is connected to the reference power supply line VSSCL. A reference voltage VSSC is supplied to the reference power supply wiring VSSCL via transfer gates TL1 and TL2.

  The transfer gates TL1 and TL2 are each composed of an NMOS transistor. The drains of the transfer gates TL1 and TL2 are connected to each other and connected to the source of the driver transistor DL of the first inverter, and the sources of the transfer gates TL1 and TL2 are connected to each other and connected to the reference voltage VSSC terminal. Further, the bit line / BL is connected to the gate of the transfer gate TL1, and the power supply voltage VDD end is connected to the gate of the transfer gate TL2.

  The second inverter circuit IV2 includes a load transistor LR made of a PMOS transistor and a driver transistor DR made of an NMOS transistor. The drain of the load transistor LR is connected to the drain of the driver transistor DR. A power supply voltage VDD is supplied to the source of the load transistor LR. The source of the driver transistor DR is connected to the reference power supply line VSSCR. A reference voltage VSSC is supplied to the reference power supply wiring VSSCR via transfer gates TR1 and TR2.

  Transfer gates TR1 and TR2 are each composed of an NMOS transistor. The drains of these transfer gates TR1 and TR2 are connected to each other and connected to the source of the driver transistor DR of the second inverter, and the sources of the transfer gates TR1 and TR2 are connected to each other and connected to the reference voltage VSSC terminal. Further, the bit line BL is connected to the gate of the transfer gate TR1, and the power supply voltage VDD end is connected to the gate of the transfer gate TR2.

  The output node of the first inverter IV1 is connected to the input node of the second inverter IV2, and is connected to the bit line BL via the current path of the transfer gate transistor PL. The output node of the second inverter IV2 is connected to the input node of the first inverter IV1, and is also connected to the bit line / BL via the current path of the transfer gate transistor PR. A signal complementary to the signal of the bit line BL is supplied to the bit line / BL. Further, a word line WL (not shown) is connected to the gates of the transfer gate transistors PL and PR.

  In other words, transfer gates (hereinafter referred to as NMOS transfer) TL1 and TL2 made of NMOS transistors and NMOS transfers TR1 and TR2 are inserted into respective supply paths (reference power supply wirings VSSCL and VSSCR) from the reference voltage VSSC. The size of the NMOS transfer TL1 is set larger than the size of the NMOS transfer TL2 so that the current transfer capability of the NMOS transfer TL1 is larger than that of the NMOS transfer TL2. The bit line / BL is connected to the gate of the NMOS transfer TL1, and the power supply voltage VDD terminal is connected to the NMOS transfer TL2, so that the NMOS transfer TL2 is normally on.

  The size of the NMOS transfer TR1 is set larger than the size of the NMOS transfer TR2 so that the current transfer capability of the NMOS transfer TR1 is larger than that of the NMOS transfer TR2. The bit line BL is connected to the gate of the NMOS transfer TR1, the power supply voltage VDD terminal is connected to the NMOS transfer TR2, and the NMOS transfer TR2 is in a normally-on state.

  Usually, since the bit line pair (BL, / BL) of the SRAM cell is precharged to the “H” level, the NMOS transfer TL1, TR1 having a large size is turned on in this state, and the NMOS transfer TL1, TR1. By taking a sufficient size, the impedances of the reference power supply wirings VSSCL and VSSCR are made sufficiently small to such an extent that the operation is not hindered even when a cell is selected. The small NMOS transfers TL2 and TR2 are for holding the cell data of the unselected cells even when the large NMOS transfers TL1 and TR1 are turned off. Since the data retention margin is large because the word line WL is closed (the word line is “L”) without flowing, the sizes of the NMOS transfers TL2 and TR2 may be small.

  Next, the operation of the SRAM cell of the first embodiment will be described.

  First, the reading operation in the SRAM cell will be described. At the time of reading, the word line WL of the selected cell is turned on (“H”), and in FIG. 9A, the voltage level of the bit line / BL connected to the right inverter IV2 storing “L” data. Are discharged by the cell current. At this time, since the voltage level of the bit line BL is kept at the precharge level “H”, the NMOS transfer TR1 connected to the right reference power supply line VSSCR through which the cell current flows is kept sufficiently on. The For this reason, the read characteristics are not deteriorated due to a decrease in cell current or the like.

  On the other hand, as for the reference power supply wiring VSSCL, the driving force of the NMOS transfer TL1 decreases as the voltage of the bit line / BL decreases. However, there is no problem because the output node of the left inverter IV1 holds “H”. Rather, this corresponds to a relative decrease in the driving force of the left driver transistor DL, which has the effect of canceling data retention deterioration due to variations in threshold voltage and improving current data retention characteristics. This effect can be obtained only when the voltage level of the bit line is lowered. However, the problem of data inversion due to cell disturb is that it takes some time for the flip-flop to invert after the word line WL is opened. appear. For this reason, it can be expected that the inversion problem is less likely to occur when the data retention characteristic is improved with time.

  Next, the operation at the time of writing in the SRAM cell will be described. As shown in FIG. 9B, when the data of the output node of the right inverter IV2 is rewritten from “H” to “L”, the bit line / BL is pulled to “L”, and “ H "is input. As a result, the impedance of the reference power supply wiring VSSCL increases, while the impedance of the reference power supply wiring VSSCR does not change. In other words, the wiring resistance of the reference power supply wiring VSSCL increases, while the wiring resistance of the reference power supply wiring VSSCR does not change. This is equivalent to the change in the impedance of the left and right reference power supply lines VSSCL and VSSCR to which the reference voltage VSS is supplied so that new data can be easily written in the flip-flop, and the data writing characteristics are greatly improved. The As described above, the deterioration of the writing characteristics caused by the variation in the threshold voltage of the transistors constituting the SRAM cell is improved, and the writing speed is also improved.

  As described above, this first embodiment does not require a power supply of a different voltage level as described in the conventional example, and does not require a logical operation with an address and write data and a switching of the power supply level by that. The transfer gate connected to the reference power supply wiring to which the reference voltage VSSC is supplied is controlled using the voltage level of the bit line. As a result, it is possible to take measures to improve both the cell disturb problem due to the variation of the threshold voltage and the problem of deterioration of the write characteristics. Note that this example is based on the case of the SRAM cell as shown in FIGS. 8A and 8B in which the reference power supply wiring VSSC is independently wired in two on the left and right.

[Second Embodiment]
Next explained is a semiconductor memory device having an SRAM cell according to the second embodiment of the invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In the first embodiment, the example of controlling the reference voltage VSSC has been described. In the second embodiment, the case of controlling the power supply voltage VDDC will be described. Note that the first embodiment is based on the premise that the reference voltage VSSC is divided into two power supplies on the left and right, and therefore only in the case of an SRAM cell as shown in FIGS. 8A and 8B. Although not applicable, the wiring in which the power supply voltage VDDC to which the second embodiment can be applied is separated into two on the left and right sides is an SRAM cell as shown in FIG.

  FIG. 10A and FIG. 10B are circuit diagrams showing the configuration of the SRAM cell of the second embodiment.

  The SRAM cell includes a first inverter circuit IV1, a second inverter circuit IV2, transfer gate transistors PL and PR, transfer gates TL3, TL4, TR3 and TR4, power supply voltage wirings VDDCL and VDDCR to which a power supply voltage VDDC is supplied, And bit lines BL and / BL.

  The first inverter circuit IV1 includes a load transistor LL made of a PMOS transistor and a driver transistor DL made of an NMOS transistor. The drain of the load transistor LL is connected to the drain of the driver transistor DL. The source of the load transistor LL is connected to the power supply voltage line VDDCL. A power supply voltage VDDC is supplied to the power supply voltage wiring VDDCL via transfer gates TL3 and TL4. A reference voltage VSS is supplied to the source of the driver transistor DL.

  The transfer gate TL3 is composed of an NMOS transistor, and the transfer gate TL4 is composed of a PMOS transistor. The source of the transfer gate TL3 and the drain of the transfer gate TL4 are connected to the source of the load transistor LL of the first inverter, and the drain of the transfer gate TL3 and the source of the transfer gate TL4 are connected to supply voltage. Connected to the VDDC end. Further, the bit line BL is connected to the gate of the transfer gate TL3, and the reference voltage VSS terminal is connected to the gate of the transfer gate TL4.

  The second inverter circuit IV2 includes a load transistor LR made of a PMOS transistor and a driver transistor DR made of an NMOS transistor. The drain of the load transistor LR is connected to the drain of the driver transistor DR. The source of the load transistor LR is connected to the power supply voltage wiring VDDCR. A power supply voltage VDDC is supplied to the power supply voltage wiring VDDCR via transfer gates TR3 and TR4. A reference voltage VSS is supplied to the source of the driver transistor DR.

  The transfer gate TR3 is composed of an NMOS transistor, and the transfer gate TR4 is composed of a PMOS transistor. The source of the transfer gate TR3 and the drain of the transfer gate TR4 are connected and connected to the source of the load transistor LR of the second inverter, and the drain of the transfer gate TR3 and the source of the transfer gate TR4 are connected to supply voltage. Connected to the VDDC end. Further, the bit line / BL is connected to the gate of the transfer gate TR3, and the reference voltage VSS terminal is connected to the gate of the transfer gate TR4.

  In other words, an NMOS transfer TL3, a transfer gate (hereinafter referred to as a PMOS transfer) TL4 composed of a PMOS transistor, an NMOS transfer TR3, and a PMOS transfer TR4 are respectively connected to supply paths (power supply voltage wirings VDDCL and VDDCR) from the power supply voltage VDDC. insert. The size of the NMOS transfer TL3 is set larger than the size of the PMOS transfer TL4 so that the current transfer capability of the NMOS transfer TL3 is larger than that of the PMOS transfer TL4. The bit line BL is connected to the gate of the NMOS transfer TL3, the reference voltage VSS terminal is connected to the PMOS transfer TL4, and the PMOS transfer TL4 is in a normally-on state.

  The size of the NMOS transfer TR3 is set larger than the size of the PMOS transfer TR4 so that the current transfer capability of the NMOS transfer TR3 is larger than that of the PMOS transfer TR4. The bit line / BL is connected to the gate of the NMOS transfer TR3, the reference voltage VSS terminal is connected to the PMOS transfer TR4, and the PMOS transfer TR4 is in a normally-on state.

  Normally, since the bit line pair (BL, / BL) of the SRAM cell is precharged to the “H” level, the NMOS transfer TL3, TR3 is turned on in this state. However, since the NMOS transfer TL3 and TR3 are both “H” (= VDD), the voltage levels of the power supply voltage wirings VDDCL and VDDCR are charged only to the “VDD−Vth” (NMOS) level. Therefore, PMOS transfers TL4 and TR4 are added so that charging is performed up to the power supply voltage VDD level. Further, even when the voltage level of the bit line BL is “L” and the NMOS transfer TL3 is turned off, the PMOS transfer TL4 holds the power supply voltage wiring VDDCL at the “H” level and holds the cell data of the non-selected cells. It is necessary to be able to do it. The PMOS transfer TR4 can hold the power supply voltage wiring VDDCR at the “H” level and hold the cell data of the non-selected cells even when the voltage level of the bit line / BL is “L” and the NMOS transfer TR3 is turned off. It is necessary to do so. However, in the power supply of the SRAM cell, since the current driving force is not required on the power supply voltage VDD side compared to the reference voltage VSS side through which the cell current flows, the size of the PMOS transfer TL4, TR4 may be smaller.

  Next, the operation of the SRAM cell of the second embodiment will be described.

  First, the reading operation in the SRAM cell will be described. At the time of reading, the word line WL of the selected cell becomes “H”, and in FIG. 10A, the voltage level of the bit line / BL connected to the right inverter IV2 storing “L” data is the cell current. It is discharged at. At this time, since the voltage level of the bit line BL holds the precharge level “H”, the NMOS transfer TL3 connected to the power supply voltage wiring VDDCL on the side holding the “H” data is sufficiently turned on. Is retained. For this reason, the deterioration of the “H” data retention characteristic of the cell including the inverter IV1 does not occur.

  On the other hand, for the power supply voltage wiring VDDCR, as the voltage of the bit line / BL decreases, the driving force of the NMOS transfer TR3 decreases. However, there is no problem because the output node of this inverter IV1 holds “L”. Rather, this corresponds to a relative decrease in the driving force of the load transistor LR consisting of the right PMOS transistor, and the effect of canceling data retention deterioration due to variations in threshold voltage and improving current data retention characteristics. There is. This effect can be obtained only when the voltage level of the bit line is lowered. However, the problem of data inversion due to cell disturb is that it takes some time for the flip-flop to invert after the word line WL is opened. appear. For this reason, it can be expected that the inversion problem is less likely to occur when the data retention characteristic is improved with time.

  Next, the operation at the time of writing in the SRAM cell will be described. As shown in FIG. 10B, when the data at the output node of the right inverter IV2 is rewritten from “H” to “L”, the bit line / BL is pulled to “L”, and “ H "is input. Then, the impedance of the power supply voltage wiring VDDCR increases, while the impedance of the power supply voltage wiring VDDCL does not change. In other words, the wiring resistance of the power supply voltage wiring VDDCR increases, while the wiring resistance of the power supply voltage wiring VDDCL does not change. This is equivalent to a change in the impedance of the left and right power supply voltage wirings VDDCL and VDDCR to which the power supply voltage VDDDC is supplied so that new data can be easily written in the flip-flop, and the data writing characteristics are greatly improved. The As described above, the deterioration of the writing characteristics caused by the variation in the threshold voltage of the transistors constituting the SRAM cell is improved, and the writing speed is also improved.

  As described above, the second embodiment does not require a power supply of a different voltage level as described in the conventional example, and does not require a logical operation with an address and write data and a switching of the power supply level by the logical operation. The transfer gate connected to the power supply voltage line to which the power supply voltage VDDC is supplied is controlled using the voltage level of the bit line. As a result, it is possible to take measures to improve both the cell disturb problem due to the variation of the threshold voltage and the problem of deterioration of the write characteristics.

[Third Embodiment]
Next explained is a semiconductor memory device having an SRAM cell according to the third embodiment of the invention. The same parts as those in the second embodiment are denoted by the same reference numerals, and the description thereof is omitted. In the second embodiment, NMOS transistors are used for the transfer gates connected to the power supply voltage wirings VDDCL and VDDCR. Therefore, the power supply by the NMOS transistors is only a voltage dropped by the threshold voltage Vth. There may be restrictions on the gate size setting. Therefore, in the third embodiment shown in FIGS. 11A and 11B, all transfer gates connected to the power supply wiring are configured by PMOS transistors, and the gate input of the transfer gate on the larger size side is It is controlled by a signal obtained by inverting the bit line potential on the opposite side.

  FIG. 11A and FIG. 11B are circuit diagrams showing the configuration of the SRAM cell of the third embodiment.

  A power supply voltage VDDC is supplied to the power supply voltage wiring VDDCL via transfer gates TL5 and TL6. Transfer gates TL5 and TL6 are each composed of a PMOS transistor. The size of the transfer gate TL5 is set larger than the size of the transfer gate TL6 so that the current driving capability of the transfer gate TL5 is larger than that of the transfer gate TL6. The drain of the transfer gate TL5 and the drain of the transfer gate TL6 are connected and connected to the source of the load transistor LL of the first inverter IV1, and the source of the transfer gate TL5 and the source of the transfer gate TL6 are connected to supply power. It is connected to the voltage VDDC terminal. Further, the bit line / BL is connected to the gate of the transfer gate TL5 via the inverter IV3, and the reference voltage VSS terminal is connected to the gate of the transfer gate TL6.

  A power supply voltage VDDC is supplied to the power supply voltage wiring VDDCR via transfer gates TR5 and TR6. Transfer gates TR5 and TR6 are each composed of a PMOS transistor. The size of the transfer gate TR5 is set larger than the size of the transfer gate TR6 so that the current driving capability of the transfer gate TR5 is larger than that of the transfer gate TR6. The drain of the transfer gate TR5 and the drain of the transfer gate TR6 are connected to the source of the load transistor LR of the second inverter IV2, and the source of the transfer gate TR5 and the source of the transfer gate TR6 are connected to supply power. It is connected to the voltage VDDC terminal. Further, the bit line BL is connected to the gate of the transfer gate TR5 via the inverter IV4, and the reference voltage VSS terminal is connected to the gate of the transfer gate TR6.

  In the third embodiment configured as described above, the same effect as that of the second embodiment described above can be obtained for the impedance control of the power supply voltage wirings VDDCL and VDDCR during operation. Further, since there is no drop of the threshold voltage Vth in the power supply in the state where the large PMOS transfers TL5 and TR5 are turned on, there is an advantage that the degree of freedom of size setting is increased. However, in a state where the bit line potential is at an intermediate potential, since the through current flows in the inverter, the technology is based on the premise that the bit line is fully swung quickly.

  In the embodiment of the present invention, in the SRAM, the noise margin at the time of read and write operations, the disturb tolerance, and the improvement of the write characteristics, which are concerned about deterioration due to the miniaturization of the SRAM cell and the reduction of the power supply voltage, are realized. For this purpose, a technique to realize by voltage control related to the cell array is proposed. Further, according to the embodiment of the present invention, due to a variation in the static noise margin of the SRAM cell, which is a problem, as the threshold voltage of the transistor increases due to the lower voltage of the power source and the miniaturization of the SRAM cell. A solution is provided to avoid disturb failures that lead to data corruption and deterioration of write characteristics. Specifically, the strength of the power supplied to the flip-flop power of the SRAM cell is controlled using the voltage level of the bit line.

  In addition, each of the above-described embodiments can be implemented not only independently but also in an appropriate combination. Furthermore, the above-described embodiments include inventions at various stages, and the inventions at various stages can be extracted by appropriately combining a plurality of constituent elements disclosed in the embodiments.

It is a circuit diagram of an SRAM cell. It is a figure which shows the 1st structural example of the cell array of SRAM. It is a figure which shows the 2nd structural example of the cell array of SRAM. It is a figure which shows the 3rd structural example of the cell array of SRAM. It is a figure which shows the 4th structural example of the cell array of SRAM. It is a figure which shows the layout of a SRAM cell, and the connection of a metal layer. It is a figure which shows the layout of the 2nd layer metal in a SRAM cell. It is a figure which shows the other layout of the 2nd layer metal in a SRAM cell. 1 is a circuit diagram showing a configuration of an SRAM cell according to a first embodiment of the present invention. FIG. It is a circuit diagram which shows the structure of the SRAM cell of 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the SRAM cell of 3rd Embodiment of this invention. It is a figure which shows the structure of the cell array in SRAM.

Explanation of symbols

  BL, / BL ... bit line, DL, DR ... driver transistor, IV1 ... first inverter circuit, IV2 ... second inverter circuit, IV3, IV4 ... inverter, LL, LR ... load transistor, PL, PR ... transfer gate Transistor, TL1, TL2, TL3, TL4, TL5, TL6, TR1, TR2, TR3, TR4, TR5, TR6 ... Transfer gate, VDD, VDDDC ... Power supply voltage, VDDCL, VDDCR Power supply voltage wiring, VSS, VSSC ... Reference voltage ( For example, ground voltage), VSSCL, VSSCR ... reference power supply wiring, WL ... word line.

Claims (5)

A memory cell including first and second inverters each having an input terminal and an output terminal connected to each other in a cross;
First power supply wiring for supplying power to the first inverter;
A second power supply wiring for supplying power to the second inverter;
First and second bit lines connected to the memory cell;
A control circuit for controlling the impedance of the first and second power supply lines in accordance with the voltage of the first and second bit lines;
A semiconductor memory device comprising: The first power supply wiring is connected to a source of an N-channel MOS transistor included in the first inverter, and the second power supply wiring is connected to a source of an N-channel MOS transistor included in the second inverter,
The first bit line is connected to an output node of the first inverter and an input node of the second inverter, and the second bit line is connected to an output node of the second inverter and the first inverter. Connected to the input node,
The control circuit includes first and second transfer gates connected to the first power supply wiring and third and fourth transfer gates connected to the second power supply wiring;
The gate of the first transfer gate is supplied with the voltage of the second bit line, and the second transfer gate is controlled to be in a normally-on state,
The voltage of the first bit line is supplied to the gate of the third transfer gate, and the fourth transfer gate is controlled to be in a normally-on state. Semiconductor memory device. The first power supply line is connected to a source of a P-channel MOS transistor included in the first inverter, and the second power supply line is connected to a source of a P-channel MOS transistor included in the second inverter,
The first bit line is connected to an output node of the first inverter and an input node of the second inverter, and the second bit line is connected to an output node of the second inverter and the first inverter. Connected to the input node,
The control circuit includes first and second transfer gates connected to the first power supply wiring and third and fourth transfer gates connected to the second power supply wiring;
The gate of the first transfer gate is supplied with the voltage of the first bit line, and the second transfer gate is controlled to be in a normally-on state,
The voltage of the second bit line is supplied to the gate of the third transfer gate, and the fourth transfer gate is controlled to be in a normally-on state. Semiconductor memory device. The first power supply line is connected to a source of a P-channel MOS transistor included in the first inverter, and the second power supply line is connected to a source of a P-channel MOS transistor included in the second inverter,
The first bit line is connected to an output node of the first inverter and an input node of the second inverter, and the second bit line is connected to an output node of the second inverter and the first inverter. Connected to the input node,
The control circuit includes first and second transfer gates connected to the first power supply wiring and third and fourth transfer gates connected to the second power supply wiring;
The voltage of the second bit line is supplied to the gate of the first transfer gate via a third inverter, and the second transfer gate is controlled to be in a normally-on state,
A voltage of the first bit line is supplied to a gate of the third transfer gate via a fourth inverter, and the fourth transfer gate is controlled to be in a normally-on state. The semiconductor memory device according to claim 1.   5. The semiconductor memory device according to claim 2, wherein the first transfer gate is sized so that a current driving force is larger than that of the second transfer gate. 6.

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