JP2009110594A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which has a simple structure and can provide a large operation margin and improved operational characteristics. <P>SOLUTION: A threshold voltage (Vth) of a transistor (N1) included in a latch portion in a memory cell is dynamically controlled to dynamically control operational characteristics of the transistor, thereby improving data write characteristics. A bias signal is applied to the body of the transistor (N1) so as to control the threshold voltage. A signal on a bit line (WBL) is used as the bias signal. A bias is applied to the body of the transistor (N1) in the memory cell based on a write data signal previously transferred through the bit line (WBL) during data write operation, thereby reducing the threshold value (Vth) of the transistor (N1). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device (for example, 7T-SRAM) having a cell structure including a latch portion for storing data, a read port, and a write port.

  With the recent miniaturization of semiconductor manufacturing processes, it has become difficult to stably operate conventional SRAMs. As one method for solving this problem, there is a 7T-SRAM memory cell in which an SRAM cell is composed of seven transistors (see, for example, Non-Patent Documents 1 and 2).

  The 7T-SRAM memory cell has a circuit configuration in which a data write port and a data read port are provided in addition to a latch portion for storing data. FIG. 13 shows a configuration of a conventional 7T-SRAM memory cell. As shown in the figure, the 7T-SRAM memory cell includes transistors N1, N2, P1, and P2, which constitute a latch unit for storing data, an access transistor N3 for writing data, and an access transistor N4 for reading data. The driver transistor N5 is composed of a total of seven transistors.

  A general SRAM is required to retain data during reading while destroying data in a memory cell during writing. In this way, both requests conflict at the time of writing and at the time of reading. For this reason, in the general SRAM, the operation voltage is limited so that the data is not destroyed at the time of data reading, so that the operation margin cannot be increased.

  On the other hand, since the 7T-SRAM memory cell is provided with a read-only port, no current flows directly from the read bit line (RBL) to the inverter unit 10 that holds data. For this reason, the 7T-SRAM memory cell can prevent data destruction associated with the read operation, and can secure a larger operation margin than a general SRAM.

"A Stable SRAM Cell Design Against Simultaneously R / W Destributed Access", Toshikazu Suzuki, et al., 2006 Symposium on VLSI Circuits Digest of Technical papers "Improved Write Margin for 90nm SOI-7T-SRAM by Look-Ahead Dynamic Threshold Voltage Control", Masaaki Iijima, et al., IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2007) (August 5-8, 2007)

  The conventional 7T-SRAM memory cell can prevent data destruction in the read operation, but has a problem that the write characteristics are deteriorated by the transistors N3 to N5 added to the inverter loop. That is, since data is written using only a single write bit line (WBL), the write margin and write speed are greatly reduced. In particular, it becomes difficult to write data “1” due to the voltage drop due to the threshold value (Vth) of the access transistor N3. It is possible to alleviate this problem by boosting the ground potential in the memory cell. However, in that case, it is necessary to provide a separate circuit, which increases the circuit area and requires a design with multiple power supplies. Or

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor memory device that can secure a large operation margin and has improved operation characteristics with a simple configuration.

  The present invention proposes a cell structure in which the threshold voltage of a transistor in a memory cell is dynamically controlled and the operation characteristic of the transistor is dynamically controlled to improve the data writing characteristic. Here, a bias signal is applied to the body of the transistor in order to control the threshold voltage. A bit line signal is used as the bias signal. A body bias is applied to the transistors in the memory cell based on the write data signal transmitted in advance by the bit line.

Specifically, the semiconductor memory device according to the present invention has the following configuration.
A first semiconductor memory device according to the present invention includes a plurality of memory cells for storing data, a write word line for selecting a memory cell for writing data, a read word line for selecting a memory cell for reading data, A write bit line for transmitting write data and a read bit line for transmitting read data information are provided.

  The memory cell is read by a latch unit that stores data, a write access transistor that transmits a signal of a write bit line to the latch unit, a driver transistor that reads data stored in the latch unit, and a driver transistor And a read access transistor for transmitting a data signal to the read bit line. The latch unit operates in a complementary manner to the first inverter composed of a P-channel transistor and an N-channel transistor connected in series, and the first inverter composed of a P-channel transistor and an N-channel transistor connected in series. 2 inverters.

  At least one of the first and second inverters controls the body potential of either the P-channel transistor or the N-channel transistor during data writing based on the signal potential of the write bit line.

  A second semiconductor memory device according to the present invention transmits a plurality of memory cells for storing data, a word line for selecting a memory cell from which data is read or written, and information on write data to the memory cell. Including bit lines. The memory cell includes two sets of inverters which are composed of P-channel transistors and N-channel transistors connected in series and operate complementarily. In at least one of the two sets of inverters, the body of one of the P-channel transistor and the N-channel transistor is connected to the bit line.

  According to the present invention, at the time of data writing, a high voltage is applied to the body of the transistor in the latch portion using the signal of the bit line, and the threshold value is dynamically reduced. As a result, the operation characteristics of the transistor that performs the data write operation are instantaneously improved. Thereby, a semiconductor memory device having a large operation margin and capable of realizing high-speed data writing can be provided. In addition, since the bias control of the body of the transistor is performed using the signal of the bit line, it is not necessary to newly provide a signal for body bias control or a plurality of power supplies, and the semiconductor having the above-described advantages with an easy configuration. A device can be realized.

  Hereinafter, embodiments of a semiconductor memory device according to the present invention will be described with reference to the accompanying drawings. In a semiconductor memory device described below, a part of transistors operating at the time of reading and writing is body-biased using a signal of a bit line and / or a word line, and a threshold voltage of the transistor is lowered. The operating characteristics of the transistor are improved by the lowering of the threshold voltage, so that the operation margin can be expanded and the data writing / reading speed can be improved.

(Embodiment 1)
1. Configuration Figure 1 shows the configuration of a memory cell of a semiconductor memory device according to the first embodiment of the present invention. The memory cell has a so-called 7T-SRAM memory cell structure composed of seven transistors.

  The semiconductor memory device includes two inverters INV1 and INV2, which constitute a latch unit for storing data, an access transistor N3 for writing data, an access transistor N4 for reading data, and a driver transistor N5.

  The inverters INVR and INVL are each configured by a series circuit of P-channel transistors P1 and P2 and N-channel transistors N1 and N2. In the inverters INVR and INVL, the gates of the P-channel transistors P1 and P2 and the gates of the N-channel transistors N1 and N2 are connected. In the inverter INVL, the connection point between the transistor P2 and the transistor N2 is the storage node V1, and in the inverter INVR, the connection point between the transistor P1 and the transistor N1 is the storage node V2. Storage node V2 is connected to a connection point between the gate of transistor P2 and the gate of transistor N2 in inverter INVL. Similarly, the storage node V1 is connected to a connection point between the gate of the transistor P1 and the gate of the transistor N1 in the inverter INVR. With this configuration, the inverter INVL and the inverter INVR operate complementarily.

  The drain of the write access transistor N3 is connected to the write bit line WBL, and its gate is connected to the write word line WWL.

  The source of the read driver transistor N5 is connected to the ground, and the drain thereof is connected to the source of the read access transistor N4. The drain of the read access transistor N4 is connected to the read bit line RBL, and the gate thereof is connected to the read word line RWL.

  Further, in the present embodiment, the body of the write access transistor N3 is connected to the write word line WWL. The bodies of the read access transistor N4 and the driver transistor N5 are connected to the read word line RWL. Thus, by body biasing the access transistors N3, N4 and the driver transistor N5 using the write word line WWL and the read word line RWL, the body potentials of these transistors N3, N4, N5 are controlled, The threshold voltage is changed to improve the operating characteristics.

2. The data write operation to the operation above 7T-SRAM memory cell will be described.
When writing data, the write word line WWL is activated ("High"), and the write bit line WBL is connected to the latch portion (inverters INV1 and INV2) by the access transistor N3. At this time, data is stored in the storage nodes V1 and V2 in accordance with the signal of the write bit line WBL.

  On the other hand, when reading data, the read bit line RBL is raised to the power supply voltage in advance and disconnected from the power supply, and then the read word line RWL is activated (that is, the read word line RWL is changed from “Low”). To “High”). At this time, the data stored in the memory cell is determined by the current flowing into the memory cell from the read bit line RBL via the read access transistor N4 and the driver transistor N5. Here, since the driver transistor N5 is controlled by the data stored in the storage node V1, the read current from the read bit line RBL is detected only when the storage node V1 is in the “High” state.

  When the write word line WWL is activated (High) during the write operation, the threshold value of the access transistor N3 decreases. This increases the cell current and improves the data write characteristics. On the other hand, when the read word line RWL becomes active (High) during the read operation, the threshold values of the access transistor N4 and the driver transistor N5 are both lowered, and the charge discharge of the read bit line RBL) is accelerated, and the read speed is increased. Will improve.

  Note that when the bodies of the transistors N3 to N5 are connected to the power supply and the body potential is fixed to the “High” state, there is a problem in that current always flows from the bodies of the transistors N3 to N5 to the source, and power is consumed. Therefore, in this embodiment, the transistors N3 to N5 are subjected to body bias control using a signal on the word line, and the body potential is increased only during the write or read operation, thereby suppressing an increase in power consumption.

3. Layout FIG. 2 shows an example of the layout of the 7T-SRAM memory cell shown in FIG. In the figure, the area within the broken line frame is the unit cell area. Actually, the unit cell regions are developed symmetrically in the vertical and horizontal directions in the figure.

  Referring to FIG. 2, in order to apply the potential of write word line WWL only to the body of access transistor N3, complete isolation portion 11a is provided (details of the complete isolation portion will be described later), and between access transistor N3 and transistor N2 Are electrically separated. The body of the transistor N2 is fixed to the ground potential for each cell by being connected to the ground (GND) through the common contact 15a. Further, in order to control the body potentials of the access transistor N4 and the driver transistor N5 with the potential of the read word line RWL, a complete isolation portion 11b for electrically isolating from the read word line RWL of an adjacent cell is provided. is doing.

  The transistor P1 and the transistor P2 are connected by the same partial separation unit (details of the partial separation unit will be described later), and the body potential is fixed every several to several tens of cells in a repeated arrangement of cells. Can do. In FIG. 8 described later, as a structure for fixing the body potential of the transistor P1, the active layer and the body are connected to the power supply voltage Vcc through a common contact. Using this connection method, the body potentials of the transistors P1 and P2 can be connected to the power supply voltage Vcc by using the Vcc contacts of the transistors P1 and P2 as a common contact for each cell.

  FIG. 3 shows a cross-sectional structure taken along line Y-Y ′ of FIG. 2, and FIG. 4 shows a cross-sectional structure taken along line Z-Z ′. In FIG. 3, a buried oxide film 22 and an active layer are formed on a silicon substrate 20. In the active layer, a gate and a source of a transistor are formed, and an isolation oxide film for electrical isolation is formed. In the figure, the portion where the isolation oxide film is formed so as to reach the buried oxide film 22 as shown in the region A is called a complete isolation portion, and the isolation oxidation is performed leaving the thin Si layer 30 as shown in the region B. The part where the film is formed is called a partial separation part.

  FIG. 3 shows an example in which, for example, the body potential of the transistor N2 is controlled to the ground potential, the common contact 15a having a common contact with the partial isolation portion 32 and the active layer 31 is connected to the ground wiring (GND) 17. Yes. 4 shows an example in which a contact 15d is formed in the partial isolation portion 33 as a common contact between the gate of the access transistor N4 and the read word line RWL (13). In FIG. 4, the thin Si layer 34 is connected to the body of the transistor N4, and is connected to the read word line RWL by a contact 15d. Therefore, the body of the access transistor N4 is connected to the read word line RWL.

  As described above, in this embodiment, the bodies of the access transistors N3 and N4 and the driver transistor N5 are connected to the word line WWL or RWL. Thereby, by lowering the threshold values of the access transistors N3 and N4 and the driver transistor N5 that are operated at the time of writing or reading, the operating characteristics of those transistors are improved and the operating margin is improved.

(Embodiment 2)
In the present embodiment, a configuration for speeding up the writing of data “1” will be described. In this embodiment, the bias of the body of the transistor N1 is controlled using the write bit line WBL.

  FIG. 5 shows the configuration of the memory cell of the semiconductor memory device according to this embodiment. In the present embodiment, in addition to the configuration shown in FIG. 1, a write bit line WBL is connected to the body of the transistor N1 in the inverter INVR.

  The operation at the time of writing will be described. In the present embodiment, when data “1” is written, the potential of the write bit line WBL is controlled to “High”, and when data “0” is written, the potential of the write bit line WBL is “Low”. "Is controlled in the same way in the following embodiments).

  In the case of writing data “1”, since the potential of the write bit line WBL is controlled to “High”, the threshold voltage of the transistor N1 is lowered, and the charge discharge from the storage node V2 is accelerated. In this way, the write operation becomes faster due to the look-ahead of the data signal to be written. The write operation of data “0” has the same characteristics as in the first embodiment. However, as for the write operation, the operation margin is more severe in writing data “1” than in writing normal data “0”, and thus the above configuration is sufficiently advantageous in terms of high-speed operation. Note that in order to increase the speed of the data “0” write operation, the write bit line WBL may be connected not to the body of the transistor N1 but to the body of the transistor P1. At that time, the body of the transistor N1 is fixed to the ground.

  Here, it is not preferable to connect both bodies of the N-channel transistor and the P-channel transistor to the write bit line WBL in the same inverter for the following reason. For example, when the write bit line WBL is “High”, a current flows between the write bit line WBL and the source via the body of the transistor N1. On the other hand, when the write bit line WBL is “Low”, a current flows between the write bit line WBL and the power supply Vcc through the body of the transistor P1. That is, regardless of the potential state of the write bit line WBL, current continues to flow through the transistor N1 or the transistor P1, and power is consumed. Therefore, in the present embodiment, only one of the bodies of both the transistor N1 and the transistor P1 is connected to the write bit line WBL.

  Further, at the time of standby of the semiconductor memory device, it is preferable to perform the following control from the viewpoint of power saving. That is, when the write bit line WBL is connected to the body of the transistor N1, the write bit line WBL is fixed to “Low” during standby. On the other hand, when the write bit line WBL is connected to the body of the transistor P1, the write bit line WBL is fixed to “High” during standby. By performing such control, current flowing between the write bit line WBL and the ground or the power supply during standby can be prevented, and power consumption in the transistor N1 or P1 during standby can be suppressed.

  FIG. 6 shows a layout of the memory cell shown in FIG. The body potential of the transistor N1 is controlled through the body contact BN1. Although not shown in FIG. 6, the connection between the write bit line WBL and the body contact BN1 is realized by an upper layer wiring (second metal, third metal, fourth metal, etc.) of the first metal wiring. . The transistors P1 and P2 have the same layout as in FIG. 2, and the body potential is fixed as in FIG.

(Embodiment 3)
In the present embodiment, in addition to the body bias control shown in FIG. 5, body bias control using an inverted bit line signal (WBLB) is added to the transistor P2 of the inverter INVL. The inverted bit line signal WBLB is generated by inverting the signal of the write bit line WBL.

  FIG. 7 shows the configuration of this embodiment. 7 includes an inverting element 7 for inverting the signal of the write bit line WBL, and a selector 5 that selects and outputs the inverted bit line signal WBLB or the write bit line RBL based on the write control signal WE. .

  Based on the write control signal WE, the selector 5 selects the inverted bit line signal WBLB during the write operation and selects and outputs the read bit line RBL during the read operation. That is, based on the write control signal WE, the selector 5 connects the inverted bit line signal WBLB to the transistor P2 during the write operation, and connects the read bit line RBL to the drain of the access transistor N4 during the read operation.

  That is, at the time of reading (WE = “Low”), the memory cell is connected to the read bit line RBL as usual by the selector 5 and the read operation is executed. On the other hand, at the time of writing (WE = “High”), since the memory cell is connected to the inverted bit line signal WBLB, a body bias corresponding to the inverted bit line signal WBLB is applied to the inverter INVL.

  In the case of writing data “1”, since the inverted bit line signal WBLB is “Low”, the threshold voltage of the transistor P2 is lowered and the storage node V1 is charged at high speed. In the write operation of data “0”, the operation characteristics are the same as those in the first embodiment shown in FIG. However, with respect to the write operation, writing “1” is usually more advantageous in terms of high-speed operation of the cell because writing “1” has a stricter operating margin.

  As described above, the write characteristics are further improved by the body bias using the two complementary bit line signals (WBL, WBLB) as the look-ahead signal. In this embodiment, in order to prevent an increase in standby power due to forward biasing of the body diodes of the transistor N1 and the transistor P2 during standby, the write bit line WBL is set to “Low” and the read bit is set during standby. It is preferable to keep the line RBL "High".

  FIG. 8 shows an example of the layout of the memory cell of this embodiment. The body portions of the transistors P1 and P2 are electrically separated by the complete separation portion. The body potential of the transistor P1 is fixed to the power supply potential Vcc by a common contact with the active layer. A body contact BP2 is formed for controlling the body potential of the transistor P2. Further, the body potential of the transistor N1 is controlled via the body contact BN1, and the body potential of the transistor N2 is fixed to the ground potential GND by a common contact with the active layer. Although not shown in FIG. 8, the signal of the read bit line RBL is connected to the body contact BP2 by the upper layer wiring of the first metal wiring, and the body potential of the transistor P2 is controlled. Further, the body potential of the transistor N1 is also controlled by applying the signal of the read bit line WBL to the body contact BN1 through the upper layer wiring of the first metal wiring.

(Embodiment 4)
In the third embodiment, bias control to the body of the transistor N1 is performed by a signal on the write bit line WBL. In this embodiment, the body potential of the transistor P1 is controlled by the write bit line WBL. FIG. 9 shows the configuration of the memory cell of this embodiment. The output of the selector 5 is connected to the body of the transistor P1, and the body of the transistor N1 is connected to the ground.

  At the time of data writing, the selector 5 selects and outputs the inverted bit line signal WBLB. In the case of writing data “1”, since the inverted bit line signal (WBLB) is “Low”, the threshold voltage of the transistor P2 is lowered and the storage node V1 is charged at high speed. On the other hand, in the write operation of the data “0”, the signal “Low” of the write bit line WBL is applied to the body of the transistor P1, the threshold value of the transistor P1 decreases, and “High” to the storage node V2 becomes “High”. Writing is performed at high speed. In this way, it is possible to realize high speed in writing both data “0” and “1”. In the present embodiment, it is preferable to hold both the bit lines WBL and RBL at “High” during standby so that the standby power does not increase.

  FIG. 10 shows an example of the layout of the memory cell of this embodiment. The body potentials of the transistors P1 and P2 are controlled via body contacts BP1 and BP2, respectively. In this layout, the read bit line RBL and the body contact BP2, and the write bit line WBL and the body contact BP1 can be connected by the first metal wiring. In this embodiment, since it is not necessary to individually control the body potential of the transistor N1, the body potentials of the transistors N1 of adjacent cells are collectively fixed to the ground GND by a common partial separation layer. Can do. Alternatively, the body potential of the transistor N1 may be fixed to the ground GND for each cell by using a common contact with the active layer as in the case of fixing the body potential of the transistor N2.

(Embodiment 5)
In the fourth embodiment, the body bias control is performed on the P-channel transistors P1 and P2 in the inverters INVR and INVL. On the other hand, in the present embodiment, the body bias control is performed on the N-channel transistors N1 and N2 in the inverters INVR and INVL. That is, the transistor N1 is body biased by the write bit line WBL, and the transistor N2 is body biased by the inverted bit line signal WBLB.

  FIG. 11 shows the configuration of the memory cell of this embodiment. As shown in FIG. 11, in this embodiment, the write bit line WBL is connected to the body of the transistor N1, and the output of the selector 5 (inverted bit line signal WBLB) is connected to the body of the transistor N2.

  At the time of data writing, the selector 5 selects and outputs the inverted bit line signal WBLB. In the case of writing data “0”, since the inverted bit line signal WBLB is “High”, the threshold voltage of the transistor N2 is lowered and the storage node V1 is discharged at high speed. On the other hand, in the write operation of data “1”, the “High” signal of the write bit line WBL is applied to the body of the transistor N1, thereby lowering the threshold value of the transistor N1 and discharging the storage node V2. Accelerated. In this way, it is possible to realize high speed in writing both data “0” and “1”. Also in this embodiment, it is preferable to control so that the standby power does not increase. For example, during standby, the selector 5 may be controlled to select the read bit line RBL and both the bit lines WBL and RBL may be held at “Low”.

  FIG. 12 shows an example of the layout of the memory cell of this embodiment. The body potentials of the transistors N1 and N2 are controlled via body contacts BN1 and BN2, respectively. Although not shown in FIG. 12, the output signal of the selector 5 is connected to the body contact BN2 by the upper layer wiring of the first metal wiring, and the body potential of the transistor N2 is controlled. The body potential of the transistor N1 is also controlled by applying the signal of the write bit line WBL to the body contact BN1 via the upper layer wiring of the first metal wiring.

  Since the transistors P1 and P2 are connected by the same partial isolation layer, the body potential can be fixed for every several to several tens of cells in a repeated arrangement of cells. Further, by using the method shown in FIG. 8 as the structure for fixing the body potential of the transistor P1, that is, the method of connecting the active layer and the body portion to the power supply potential Vcc with a common contact, the transistor P1, It is also possible to connect the body potentials of the transistors P1 and P2 to the power source Vcc by using the Vcc contact of P2 as a common contact.

(Summary)
As described above, the electric characteristics of the word lines WWL and RWL and the bit lines WBL and RBL are appropriately given to the body of the transistor in the memory cell, thereby improving the operating characteristics of the transistor and increasing the operating margin of the 7T-SRAM memory cell. Can be expanded to achieve high-speed operation.

  Note that the combination of transistors for performing body bias control is not limited to the example shown in the above embodiment. If body bias control using a word line or a bit line is performed on at least one of the access transistors N3, N4, the driver transistor N5, and the transistors N1, N2, P1, and P2 in the inverter, the operation margin can be increased and the processing can be performed. The effect of speeding up can be obtained. Moreover, you may combine the structure shown to each of said Embodiment 1 thru | or 5 suitably.

  In the above embodiment, the example of the body bias control based on the word line and / or the bit line has been described with respect to the structure of the 7T-SRAM memory cell. However, it goes without saying that the concept of body bias control described in the above embodiment can be applied to a general SRAM memory cell.

The figure which showed the structure of 7T-SRAM memory cell of Embodiment 1 of this invention Layout diagram of 7T-SRAM memory cell of the first embodiment The figure which shows the cross-section of the 7T-SRAM memory cell of Embodiment 1 (Y-Y ') FIG. 3 is a diagram (Z-Z ′) showing a cross-sectional structure of the 7T-SRAM memory cell of the first embodiment The figure which showed the structure of 7T-SRAM memory cell of Embodiment 2 of this invention 7T-SRAM memory cell layout diagram of the second embodiment The figure which showed the structure of 7T-SRAM memory cell of Embodiment 3 of this invention 7T-SRAM memory cell layout diagram of the third embodiment The figure which showed the structure of 7T-SRAM memory cell of Embodiment 4 of this invention Layout diagram of 7T-SRAM memory cell of Embodiment 4 The figure which showed the structure of 7T-SRAM memory cell of Embodiment 5 of this invention. Layout diagram of 7T-SRAM memory cell according to the fifth embodiment The figure which showed the structure of the conventional 7T-SRAM memory cell.

Explanation of symbols

11a to 11d Separation layer 13 Read word line 15a to 15d Contact 31 Si layer INV1, INV2 Inverter (data latch unit)
N1-N2, P1-P2 Transistors N3, N4 Access transistor N5 Driver transistor RBL Read bit line RWL Read word line WBL Write bit line WWL Write word line N1, N2 Storage node

Claims (14)

A plurality of memory cells for storing data; and
A write word line for selecting a memory cell to which data is written, and
A read word line for selecting a memory cell from which data is read; and
A write bit line for transmitting write data;
A read bit line for transmitting read data information,
The memory cell is
A latch unit for storing data;
A write access transistor for transmitting a signal of the write bit line to the latch unit;
A driver transistor for reading data stored in the latch unit;
A read access transistor that transmits a signal of data read by the driver transistor to the read bit line;
The latch unit operates in a complementary manner to the first inverter including a P-channel transistor and an N-channel transistor connected in series, and the P-channel transistor and the N-channel transistor connected in series. And a second inverter
At least one of the first and second inverters controls the body potential of one of a P-channel transistor and an N-channel transistor during data writing based on the signal potential of the write bit line. Semiconductor memory device.   2. The semiconductor memory device according to claim 1, wherein a body of the write access transistor is connected to the write word line.   2. The semiconductor memory device according to claim 1, wherein a body of the read access transistor and / or the driver transistor is connected to the read bit line.   2. The semiconductor memory device according to claim 1, wherein a body of the N-channel transistor is connected to the write bit line in at least one of the first and second inverters.   2. The semiconductor memory device according to claim 1, wherein a body of the P-channel transistor is connected to the write bit line in at least one of the first and second inverters.   2. The semiconductor memory device according to claim 1, wherein a body of the N-channel transistor is connected to a signal obtained by inverting a signal of the write bit line in at least one of the first and second inverters. .   2. The semiconductor memory device according to claim 1, wherein the body of the P-channel transistor is connected to a signal obtained by inverting the signal of the write bit line in at least one of the first and second inverters. .   In the first inverter, the body of the N-channel transistor is connected to the write bit line, and in the second inverter, the body of the P-channel transistor is connected to a signal obtained by inverting the signal of the write bit line. The semiconductor memory device according to claim 1.   In the first inverter, the body of the P channel transistor is connected to the write bit line, and in the second inverter, the body of the P channel transistor is connected to a signal obtained by inverting the signal of the write bit line. The semiconductor memory device according to claim 1.   In the first inverter, the body of the N channel transistor is connected to the write bit line, and in the second inverter, the body of the N channel transistor is connected to a signal obtained by inverting the signal of the write bit line. The semiconductor memory device according to claim 1.   The memory cell further includes inverting means for inverting the signal of the write bit line, and a selector for selecting and outputting either the output of the inverting means or the signal of the read bit line based on a write control signal. The semiconductor memory device according to claim 6, further comprising:   11. The semiconductor memory device according to claim 4, wherein the potential of the write bit line is controlled to be “Low” during standby.   10. The semiconductor memory device according to claim 5, wherein the potential of the write bit line is controlled to be “High” during standby. A plurality of memory cells for storing data; and
A word line for selecting a memory cell from which data is read or written;
A bit line for transmitting information of write data to the memory cell,
The memory cell includes two sets of inverters which are composed of a P-channel transistor and an N-channel transistor connected in series and operate complementarily.
A semiconductor memory device, wherein in at least one of the two sets of inverters, the body of one of a P-channel transistor and an N-channel transistor is connected to the bit line.

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