JP2008065863A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve data holding stability in a memory cell. <P>SOLUTION: This semiconductor memory device includes inverter circuits IC1 and IV2 constituted of MOS transistors; a storage node N1 connected to the output terminal of the inverter circuit IV1 and the input terminal of the inverter circuit IV2; a storage node N0 connected to the input terminal of the inverter circuit IV1 and the output terminal of the inverter circuit IV2; a first writing path with which the storage node N1 and a bit line BL0 are connected during data writing and which is controlled by a column selection signal; a writing path with which the storage node N0 are a bit line BL1 are connected during data writing and which is controlled by the column selecting signal; and a reading path through which data stored in the storage node N1 or N0 are transferred to the bit line BL0 during data writing. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to an SRAM (Static Random Access Memory).

  An SRAM is known as a kind of semiconductor memory device. For example, an SRAM cell (6Tr. Type SRAM cell) composed of six MOS (Metal Oxide Semiconductor) transistors is used as a memory cell constituting the SRAM.

  6Tr. The type SRAM cell includes two sets of inverter circuits, and has a structure in which the output terminal of one inverter circuit is connected to the input terminal of the other inverter circuit. Further, two transfer gates for connecting the data storage node of the inverter circuit to the bit line at the time of reading and writing of data are provided.

  As an index indicating the operation margin of the SRAM, there is a static noise margin (SNM). SNM is a superposition of the input / output characteristics of two inverter circuits when a word line is selected and a bit line is precharged to a power supply voltage. The length of one side of a square that can be written between these curves. It corresponds to.

  In recent years, the size of transistors used in memory cells and the like has been reduced in order to improve the degree of integration of semiconductor memory devices. In addition, the threshold voltage of the transistor also decreases in response to the decrease in power supply voltage. As a result, there is a problem that the threshold voltage variation of the transistors constituting the memory cell becomes large.

  For this reason, the SNM is lowered due to the influence of the threshold voltage variation of the transistors constituting the memory cell, and there is a problem that some memory cells have insufficient SNM.

  Therefore, in a memory cell having low data retention stability due to the low SNM, when the word line connected to the memory cell is activated to read data from the memory cell, the storage state of the inverter pair storing the data There is a problem that the data is reversed and the data is destroyed.

As this type of related technology, an SRAM cell that can cope with low power consumption is disclosed (Non-Patent Document 1). 6Tr. In the type SRAM cell, there is a problem that in the memory cell of the selected row and the non-selected column, a cell current flows when reading and writing data, and extra power is consumed. Although the said nonpatent literature 1 has taken the countermeasure, the problem regarding the said SNM remains.
Hiroki Morimura et al., “A Shared-Bitline SRAM Cell Architecture for 1-V Ultra Low-Power Word-Bit Configurable Macrocells”, NTT Lifestyle and Environmental Technology Laboratories, ISLPED99, San Diego, CA, USA, pp.12-17

  The present invention provides a semiconductor memory device capable of improving the stability of data retention in a memory cell.

  A semiconductor memory device according to a first aspect of the present invention includes first and second inverter circuits configured by MOS transistors, an output terminal of the first inverter circuit, and an input terminal of the second inverter circuit. A first storage node connected to the first storage circuit; a second storage node connected to an input terminal of the first inverter circuit; and an output terminal of the second inverter circuit; Connecting the storage node and the first bit line and connecting the second storage node and the second bit line at the time of data writing with a first write path controlled by a column selection signal; and The second write path controlled by the column selection signal, and the data stored in the first storage node or the second storage node at the time of data reading are stored in the first bit. A memory cell including a read path for transferring the.

  According to the present invention, it is possible to provide a semiconductor memory device capable of improving the stability of data retention in a memory cell.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

(First embodiment)
FIG. 1 is a circuit diagram centered on the memory cell MC of the SRAM according to the first embodiment of the present invention. The memory cell MC shown in FIG. 1 has a 9Tr. Type SRAM cell.

  The memory cell MC includes a first inverter circuit IV1 and a second inverter circuit IV2. The first inverter circuit IV1 includes a load transistor L0 made up of a P-channel MOS transistor (PMOS transistor) and a drive transistor D0 made up of an N-channel MOS transistor (NMOS transistor). The load transistor L0 and the drive transistor D0 are connected in series between a power supply voltage Vdd (for example, a power supply terminal to which the power supply voltage Vdd is applied) and a ground potential Vss (for example, a ground terminal to which the ground potential Vss is applied). ing.

  The second inverter circuit IV2 includes a load transistor L1 made of a PMOS transistor and a drive transistor D1 made of an NMOS transistor. The load transistor L1 and the drive transistor D1 are connected in series between the power supply terminal and the ground terminal.

  Specifically, the power supply voltage Vdd is applied to the source terminal of the load transistor L0. The drain terminal of the load transistor L0 is connected to the drain terminal of the drive transistor D0 via the storage node N0. The gate terminal of the load transistor L0 is connected to the gate terminal of the drive transistor D0. The ground potential Vss is applied to the source terminal of the driving transistor D0.

  A power supply voltage Vdd is applied to the source terminal of the load transistor L1. The drain terminal of the load transistor L1 is connected to the drain terminal of the drive transistor D1 via the storage node N1. The gate terminal of the load transistor L1 is connected to the gate terminal of the drive transistor D1. A ground potential Vss is applied to the source terminal of the drive transistor D1.

  The gate terminal of the load transistor L0 is connected to the storage node N1. The gate terminal of the load transistor L1 is connected to the storage node N0. In other words, the output terminal of the first inverter circuit IV1 is connected to the input terminal of the second inverter circuit IV2, and the output terminal of the second inverter circuit IV2 is connected to the input terminal of the first inverter circuit IV1. .

  The storage node N1 is electrically connected to the write path. The write path electrically connects the storage node N1 and the bit line BL when writing data. The write path includes a column selection transistor TC1 made of an NMOS transistor and a write transfer gate T1 made of an NMOS transistor.

  Specifically, the storage node N1 is connected to the connection node SBL via the column selection transistor TC1. The gate terminal of the column selection transistor TC1 is connected to the write column selection line YSELW. The connection node SBL is connected to the bit line BL via the write transfer gate T1. The gate terminal of the write transfer gate T1 is connected to the word line WL.

  The storage node N0 is electrically connected to the write path. The write path electrically connects the storage node N0 and the bit line BL of the adjacent memory cell when writing data. The write path includes a column selection transistor TC0 made of an NMOS transistor and a write transfer gate T1 made of an NMOS transistor.

  Specifically, the storage node N0 is connected to the connection node / SBL via the column selection transistor TC0. The gate terminal of the column selection transistor TC0 is connected to the write column selection line YSELW. The connection node / SBL is connected to the bit line BL of the adjacent memory cell via the write transfer gate T1 of the adjacent memory cell. The gate terminal of the write transfer gate T1 of the adjacent memory cell is connected to the word line WL.

  Furthermore, the storage node N0 is electrically connected to the read path. The read path is provided for reading a potential corresponding to data to the bit line BL when reading data. The read path includes a read transistor composed of a read drive transistor RD1 made of an NMOS transistor and a read transfer gate RT1 made of an NMOS transistor.

  Specifically, the storage node N0 is connected to the gate terminal of the read driving transistor RD1. A ground potential Vss is applied to the source terminal of the read driving transistor RD1. The drain terminal of the read driving transistor RD1 is connected to the bit line BL via the read transfer gate RT1. The gate terminal of the read transfer gate RT1 is connected to the word line WL.

  In the memory cell MC shown in FIG. 1, a read path for transferring data of the storage node N0 to the bit line BL at the time of data reading, a write path for transferring data of the bit line BL to the storage node N1 at the time of data writing, and data A separate write path for transferring the data of the bit line BL of the adjacent memory cell to the storage node N0 at the time of writing is provided.

  Next, the configuration of the memory cell array included in the SRAM will be described. FIG. 2 is a circuit diagram mainly showing two memory cells MC1 and MC2 included in the memory cell array. FIG. 2 shows two adjacent memory cells MC1 and MC2 in the same row.

  The configurations of the memory cells MC1 and MC2 are the same as those in FIG. When a memory cell array is formed using the memory cell MC shown in FIG. 1, the connection node / SBL of one memory cell of two adjacent memory cells in the same row is connected to the connection node SBL of the other memory cell. Connected. In this way, a memory cell array is formed.

  Memory cells MC1 and MC2 are connected to the same word line WL. A bit line BL0 and a write column selection line YSELW0 are connected to the memory cell MC1. A bit line BL1 and a write column selection line YSELW1 are connected to the memory cell MC2.

  In the memory cell array configured as described above, the write transfer gate T1 and the bit line BL1 included in the memory cell MC2 are shared by two adjacent memory cells MC1 and MC2 in the same row. That is, regarding the memory cell MC1, the bit lines BL0 and BL1 constitute a pair of bit lines. Therefore, the number of wirings other than the power supply lines running in the column direction on the memory cell array per memory cell is two, that is, the bit line BL and the write column selection line YSELW, and is composed of six MOS transistors. Conventional 6Tr. Since the type SRAM cell has two bit lines BL and / BL, there is an advantage that the number of wirings does not increase.

  Hereinafter, the data write operation and data read operation of the SRAM will be described with reference to FIG. FIG. 3 is a timing chart for explaining the data write operation and read operation of the SRAM.

  First, the data write operation of the SRAM will be described. An example will be described in which the memory cell MC1 is selected and data is written to the selected memory cell MC1. At this time, the memory cell MC2 is in a non-selected state.

  The word line WL of the selected row is set to the high level. One of the pair of bit lines BL0 and BL1 in the selected column is set to a high level (power supply voltage Vdd) and the other is set to a low level according to data to be written. The word lines WL of unselected rows not shown in FIG. 2 are set to a low level, and the bit lines of unselected columns (that is, bit lines other than BL0 and BL1) are set to a high level. Further, the write column selection signal YSELW0 for the selected column is set to a high level, and the write column selection signal for non-selected columns including YSELW1 is set to a low level.

  By such a data write operation, the data set in the bit lines BL0 and BL1 is written into the selected memory cell MC1. Note that the write transfer gates T1 of all the memory cells connected to the same row word line WL as the selected memory cell MC1 are turned on. However, the column selection transistors TC0 and TC1 are turned off for the non-selected memory cells (memory cell MC2 and the like) connected to the word line WL of the selected row. For this reason, the problem of write disturb is avoided in the non-selected memory cell.

  Next, the data read operation of the SRAM will be described. Note that, similarly to the data write operation, a case where the memory cell MC1 is selected and data of the selected memory cell MC1 is read will be described as an example.

  The word line WL of the selected row is set to the high level, and the bit line BL0 of the selected column is set to the high level. The unselected row word line WL is set to the low level, and the bit lines of the unselected column including the bit line BL1 are set to the high level. Further, all the write column selection signals YSELW (YSELW0, YSELW1, etc.) are set to a low level.

  By such a data read operation, the read transfer gate RT1 of the selected memory cell MC1 is turned on, and the read drive transistor RD1 is turned on or off according to the data of the storage node N0. Therefore, the voltage of the bit line BL0 of the selected column becomes a high level or a low level according to data. As a result, the data of the selected memory cell MC1 can be read.

  Further, the write transfer gate T1 of all the memory cells connected to the word line WL in the same row as the selected memory cell MC1 is turned on. However, with respect to all the memory cells MC, the storage node and the bit line are not connected through the write path, and the read disturb problem is avoided with respect to the memory cells (MC2 etc.) of the non-selected column.

  FIG. 4 is a diagram illustrating the static noise margin. The two curves shown in FIG. 4 are obtained by superimposing the input / output characteristics of the first and second inverter circuits IV1 and IV2. At this time, the word line WL is set to the high level, and the bit line pair BL0, BL1 is set to the high level.

  The length of one side of the maximum square inscribed in the area surrounded by two curves is defined as a static noise margin (SNM). This SNM serves as an index indicating the stability of stored data. In general, the larger the SNM, the higher the stability of data stored in the SRAM cell, and data destruction due to power supply voltage noise in the chip is less likely to occur. Therefore, taking a large SNM is an important point in designing an SRAM cell.

  In the memory cell array shown in FIG. 2, any of the source / drain terminals of the read transistor (consisting of the read drive transistor RD1 and the read transfer gate RT1) used when reading data from the memory cell is used. It is not connected to storage nodes N0 and N1 that store data. For this reason, as shown in FIG. 4, since the static noise margin (SNM) is improved, the stability of data retention can be improved. As a result, it is possible to prevent data from being destroyed when data is read.

  As described above in detail, according to the present embodiment, the static noise margin (SNM) of the selected memory cell can be improved at the time of data reading. Thus, stability of data retention can be improved, so that it is possible to sufficiently cope with variations in threshold voltage of transistors due to miniaturization and a reduction in power supply voltage.

  Further, at the time of data writing, it is possible to prevent the memory cells of all unselected columns connected to the activated word line WL from being subjected to write disturb. In addition, when data is read, it is possible to prevent the memory cells of all unselected columns connected to the activated word line WL from being read disturbed.

  Note that, in the configuration of the memory cell array shown in FIG. 2, the gate terminal of the read driving transistor RD1 is not the storage node N0 common to the gate terminal of the driving transistor D1, but the memory common to the gate terminal of the driving transistor D0. A configuration of a memory cell array modified to be connected to the node N1 is also conceivable. Even in such a configuration, the same effect as the memory cell array of FIG. 2 can be obtained by changing the logic at the time of data reading.

(Second Embodiment)
In the second embodiment, the memory cell is configured such that a word line used for data writing and a word line used for data reading are separated. FIG. 5 is a circuit diagram showing mainly SRAM memory cells MC according to the second embodiment of the present invention.

  The configuration of the memory cell MC in FIG. 5 is that the read word line RWL and the write word line WWL are provided instead of the word line WL, and the gate of the column select transistor is not the write column select line YSELW (write The memory cell MC in FIG. 1 is different from the memory cell MC in FIG. The gate terminal of the write transfer gate T1 is connected to the write word line WWL. The gate terminal of the read transfer gate RT1 is connected to the read word line RWL.

  Next, the configuration of the memory cell array included in the SRAM will be described. FIG. 6 is a circuit diagram mainly showing two memory cells MC1 and MC2 included in the memory cell array. FIG. 6 shows two adjacent memory cells MC1 and MC2 in the same row.

  The configurations of the memory cells MC1 and MC2 are the same as those in FIG. When the memory cell array is formed using the memory cell MC shown in FIG. 5, the connection node / SBL of one memory cell of two adjacent memory cells in the same row is connected to the connection node SBL of the other memory cell. Connected. In this way, a memory cell array is formed.

  The memory cells MC1 and MC2 are connected to the same read word line RWL and the same write word line WWL. A bit line BL0 and a column selection line YSEL0 are connected to the memory cell MC1. A bit line BL1 and a column selection line YSEL1 are connected to the memory cell MC2.

  Hereinafter, the data write operation and data read operation of the SRAM will be described with reference to FIG. FIG. 7 is a timing chart for explaining the data write operation and read operation of the SRAM.

  First, the data write operation of the SRAM will be described. An example will be described in which the memory cell MC1 is selected and data is written to the selected memory cell MC1.

  The write word line WWL for the selected row is set to the high level. One of the pair of bit lines BL0 and BL1 in the selected column is set to a high level and the other is set to a low level according to data to be written. The unselected row write word line WWL is set to the low level, and the bit lines of the unselected columns (that is, bit lines other than BL0 and BL1) are set to the high level.

  Further, the column selection signal YSEL0 for the selected column is set to a high level, and the column selection signals for the unselected columns including the column selection signal YSEL1 are set to a low level. All the read word lines RWL are set to a low level.

  By such a data write operation, the data set in the bit lines BL0 and BL1 is written into the selected memory cell MC1. Note that the write transfer gate T1 of all memory cells connected to the write word line WWL in the same row as the selected memory cell MC1 is turned on. However, the column selection transistors TC0 and TC1 are turned off with respect to non-selected memory cells (memory cell MC2 and the like) connected to the write word line WWL of the selected row. For this reason, it is possible to prevent unselected memory cells from undergoing write disturb.

  Next, the data read operation of the SRAM will be described. Note that, similarly to the data write operation, a case where the memory cell MC1 is selected and data of the selected memory cell MC1 is read will be described as an example.

  The read word line RWL of the selected row is set to the high level, and the bit line BL0 of the selected column is set to the high level. The read word line RWL of the non-selected row is set to the low level, and the bit lines of the non-selected column including the bit line BL1 are set to the high level.

  Further, the column selection signal YSEL0 for the selected column is set to a high level, and the column selection signals for the unselected columns including the column selection signal YSEL1 are set to a low level. All the write word lines WWL are set to a low level.

  By such a data read operation, the read transfer gate RT1 of the selected memory cell MC1 is turned on, and the read drive transistor RD1 is turned on or off according to the data of the storage node N0. Therefore, the voltage of the bit line BL0 of the selected column becomes a high level or a low level according to data. As a result, the data of the selected memory cell MC1 can be read. Note that the column selection transistors TC0 and TC1 of the selected memory cell MC1 are turned on. However, since the write transfer gate T1 is off, the storage node and the bit line are not connected through the write path. In such a data read operation, the read disturb problem is avoided for the memory cells (MC2 and the like) of the non-selected column.

  In addition, the source / drain terminals of the read transistors (configured by the read drive transistor RD1 and the read transfer gate RT1) used when reading data from the memory cell are all storing data. It is not connected to the nodes N0 and N1. For this reason, since a static noise margin (SNM) improves, the stability of data retention can be improved. As a result, it is possible to prevent data from being destroyed when data is read.

  Further, the column selection transistors TC0 and TC1 are turned off for the non-selected memory cells (memory cell MC2 and the like) connected to the read word line RWL of the selected row. For this reason, it is possible to prevent unselected memory cells from undergoing read disturb.

  Note that, in the configuration of the memory cell array shown in FIG. 6, the gate terminal of the read drive transistor RD1 is not shared with the gate node of the drive transistor D1, but with the gate terminal of the drive transistor D0. A configuration of a memory cell array modified to be connected to the node N1 is also conceivable. Even in such a configuration, the same effect as the memory cell array of FIG. 6 can be obtained by changing the logic at the time of data reading.

(Third embodiment)
In the third embodiment, a memory cell is configured so that a bit line used at the time of data writing and a bit line used at the time of data reading are separated. FIG. 8 is a circuit diagram showing mainly SRAM memory cells MC according to the third embodiment of the present invention.

  The configuration of the memory cell MC in FIG. 8 is different from the memory cell MC in FIG. 1 in that a read bit line RBL and a write bit line WBL are provided instead of the bit line BL. One of the source / drain terminals of the read transfer gate RT1 is connected to the read bit line RBL. One of the source / drain terminals of the write transfer gate T1 is connected to the write bit line WBL.

  Next, the configuration of the memory cell array included in the SRAM will be described. FIG. 9 is a circuit diagram mainly showing two memory cells MC1 and MC2 included in the memory cell array. FIG. 9 shows two adjacent memory cells MC1 and MC2 in the same row.

  The configuration of the memory cells MC1 and MC2 is the same as that in FIG. When a memory cell array is formed using the memory cell MC shown in FIG. 8, the connection node / SBL of one memory cell of two adjacent memory cells in the same row is connected to the connection node SBL of the other memory cell. Connected.

  Memory cells MC1 and MC2 are connected to the same word line WL. A write bit line WBL0, a read bit line RBL0, and a write column selection line YSELW0 are connected to the memory cell MC1. A write bit line WBL1, a read bit line RBL1, and a write column selection line YSELW1 are connected to the memory cell MC2.

  Hereinafter, the data write operation and data read operation of the SRAM will be described with reference to FIG. FIG. 10 is a timing chart for explaining the data write operation and read operation of the SRAM.

  First, the data write operation of the SRAM will be described. An example will be described in which the memory cell MC1 is selected and data is written to the selected memory cell MC1.

  The word line WL of the selected row is set to the high level. One of the pair of write bit lines WBL0 and WBL1 in the selected column is set to the high level and the other is set to the low level according to the data to be written. The word line WL of the non-selected row is set to the low level, and the write bit line (that is, the write bit line other than WBL0 and WBL1) of the non-selected column is set to the high level.

  Further, the write column selection signal YSELW0 for the selected column is set to a high level, and the write column selection signal for non-selected columns including YSELW1 is set to a low level. All the read bit lines RBL are set to a high level.

  By such a data write operation, the data set in the write bit lines WBL0 and WBL1 is written into the selected memory cell MC1. Note that the write transfer gates T1 of all the memory cells connected to the same row word line WL as the selected memory cell MC1 are turned on. However, the column selection transistors TC0 and TC1 are turned off for the non-selected memory cells (memory cell MC2 and the like) connected to the word line WL of the selected row. For this reason, it is possible to prevent unselected memory cells from undergoing write disturb.

  Next, the data read operation of the SRAM will be described. Note that, similarly to the data write operation, a case where the memory cell MC1 is selected and data of the selected memory cell MC1 is read will be described as an example.

  The word line WL of the selected row is set to the high level, and the read bit line RBL0 of the selected column is set to the high level. The unselected row word line WL is set to the low level, and the read bit lines of the unselected column including the read bit line RBL1 are set to the high level.

  Further, all the write column selection signals YSELW (YSELW0, YSELW1, etc.) are set to a low level. All the write bit lines WBL are set to a high level.

  By such a data read operation, the read transfer gate RT1 of the selected memory cell MC1 is turned on, and the read drive transistor RD1 is turned on or off according to the data of the storage node N0. Therefore, the voltage of the read bit line RBL0 of the selected column becomes a high level or a low level according to data. As a result, the data of the selected memory cell MC1 can be read. Other effects are the same as those of the first embodiment.

  Note that, in the configuration of the memory cell array shown in FIG. 9, the gate terminal of the read drive transistor RD1 is not the same storage node N0 as the gate terminal of the drive transistor D1, but the same memory as the gate terminal of the drive transistor D0. A configuration of a memory cell array modified to be connected to the node N1 is also conceivable. Even in such a configuration, the same effect as the memory cell array of FIG. 9 can be obtained by changing the logic at the time of data reading.

(Fourth embodiment)
The fourth embodiment is a modification of the first embodiment, and reduces the cell current flowing through the read transistor (configured by the read drive transistor RD1 and the read transfer gate RT1). Therefore, power consumption is reduced.

  FIG. 11 is a circuit diagram mainly showing an SRAM memory cell MC according to the fourth embodiment of the present invention. The source terminal of the read drive transistor RD1 is connected to the read column selection line / YSELR. An inverted signal / YSELR of the read column selection signal YSELR is supplied to the read column selection line. Other configurations are the same as those of the memory cell MC of FIG.

  Next, the configuration of the memory cell array included in the SRAM will be described. FIG. 12 is a circuit diagram mainly showing two memory cells MC1 and MC2 included in the memory cell array. In FIG. 12, two adjacent memory cells MC1 and MC2 in the same row are shown.

  The configuration of the memory cells MC1 and MC2 is the same as that in FIG. Memory cells MC1 and MC2 are connected to the same word line WL. A bit line BL0, a read column selection line / YSELR0, and a write column selection line YSELW0 are connected to the memory cell MC1. A bit line BL1, a read column selection line / YSELR1, and a write column selection line YSELW1 are connected to the memory cell MC2.

  Hereinafter, the data write operation and data read operation of the SRAM will be described with reference to FIG. FIG. 13 is a timing chart for explaining the data write operation and read operation of the SRAM.

  First, the data write operation of the SRAM will be described. An example will be described in which the memory cell MC1 is selected and data is written to the selected memory cell MC1.

  The word line WL of the selected row is set to the high level. One of the pair of bit lines BL0 and BL1 in the selected column is set to a high level and the other is set to a low level according to data to be written. The word line WL of the non-selected row is set to the low level, and the bit lines of the non-selected column (that is, bit lines other than BL0 and BL1) are set to the high level.

  Further, the write column selection signal YSELW0 for the selected column is set to a high level, and the write column selection signal for non-selected columns including YSELW1 is set to a low level. Further, the inversion signal / YSELR of the read column selection signal is set to the same level as that of the bit line BL connected one-to-one via the read transistor (configured by RD1 and RT1).

  By such a data write operation, the data set in the bit lines BL0 and BL1 is written into the selected memory cell MC1. Further, the bit lines BL and the read column selection line / YSELR that are connected in a one-to-one relationship via the read transistors composed of RD1 and RT1 are all at the same level. Therefore, the cell current does not flow through the read transistor when data is written. As a result, power consumption during data writing can be reduced.

  Next, the data read operation of the SRAM will be described. Note that, similarly to the data write operation, a case where the memory cell MC1 is selected and data of the selected memory cell MC1 is read will be described as an example.

  The word line WL of the selected row is set to the high level, and the bit line BL0 of the selected column is set to the high level. The unselected row word line WL is set to the low level, and the bit lines of the unselected column including the bit line BL1 are set to the high level.

  Further, the inversion signal / YSELR0 of the read column selection signal for the selected column is set to a low level, and the inversion signal of the read column selection signal for the non-selected columns including / YSELR1 is set to a high level. All the write column selection signals YSELW are set to a low level.

  By such a data read operation, the read transfer gate RT1 of the selected memory cell MC1 is turned on, and the read drive transistor RD1 is turned on or off according to the data of the storage node N0. Therefore, the voltage of the bit line BL0 of the selected column becomes a high level or a low level according to data. As a result, the data of the selected memory cell MC1 can be read.

  At this time, in the memory cells other than the selected memory cell MC1, both the bit line BL and the read column selection line / YSELR are at the high level. Therefore, even when the read driving transistor RD1 is turned on according to the data of the storage node N0, the read transistor does not flow a cell current. As a result, power consumption during data reading can be reduced.

  Note that the effect of preventing write disturb and read disturb and the effect of improving the static noise margin (SNM) are the same as those in the first embodiment.

  Further, with respect to the configuration of the memory cell array shown in FIG. 12, the gate terminal of the read driving transistor RD1 is not shared with the gate node of the driving transistor D1, but is shared with the gate terminal of the driving transistor D0. You may change so that it may connect with the node N1. Even in such a configuration, the same effect as the memory cell array of FIG. 12 can be obtained by changing the logic at the time of data reading.

(Fifth embodiment)
The fifth embodiment is a modified example of the second embodiment, and reduces the power consumption by reducing the cell current flowing through the read transistor (comprising RD1 and RT1). I have to.

  FIG. 14 is a circuit diagram centering on an SRAM memory cell MC according to the fifth embodiment of the present invention. The source terminal of the read drive transistor RD1 is connected to the column selection line / YSEL. The column selection line is supplied with an inverted signal / YSEL of the column selection signal YSEL. Other configurations are the same as those of the memory cell MC of FIG.

  Next, the configuration of the memory cell array included in the SRAM will be described. FIG. 15 is a circuit diagram mainly showing two memory cells MC1 and MC2 included in the memory cell array. FIG. 15 shows two adjacent memory cells MC1 and MC2 in the same row.

  The configuration of the memory cells MC1 and MC2 is the same as that in FIG. The memory cells MC1 and MC2 are connected to the same read word line RWL and the same write word line WWL. Bit line BL0, column select line YSEL0, and column select line / YSEL0 are connected to memory cell MC1. A bit line BL1, a column selection line YSEL1, and a column selection line / YSEL1 are connected to the memory cell MC2.

  Hereinafter, the data write operation and data read operation of the SRAM will be described with reference to FIG. FIG. 16 is a timing chart for explaining the data write operation and read operation of the SRAM.

  First, the data write operation of the SRAM will be described. An example will be described in which the memory cell MC1 is selected and data is written to the selected memory cell MC1.

  The write word line WWL for the selected row is set to the high level. One of the pair of bit lines BL0 and BL1 in the selected column is set to a high level and the other is set to a low level according to data to be written. The unselected row write word line WWL is set to a low level, and the bit lines of the unselected column (that is, bit lines other than BL0 and BL1) are set to a high level.

  Further, the column selection signal YSEL0 of the selected column is set to a high level, and the column selection signals of non-selected columns including YSEL1 are set to a low level. Since the inverted signal of the column selection signal is opposite to the high level and the low level with respect to the column selection signal, the inverted signal / YSEL0 of the column selection signal YSEL0 is set to the low level, and the non-selected column including / YSEL1 The inverted signal of the column selection signal is set to a high level. All read word lines RWL are set to a low level.

  By such a data write operation, it is possible to prevent the unselected memory cell from undergoing a write disturb, as in the second embodiment. In all the memory cells, the read transfer gate RT1 is turned off. For this reason, a cell current does not flow through the read transistor composed of RD1 and RT1 during data writing. As a result, power consumption during data writing can be reduced.

  Next, the data read operation of the SRAM will be described. Note that, similarly to the data write operation, a case where the memory cell MC1 is selected and data of the selected memory cell MC1 is read will be described as an example.

  The read word line RWL of the selected row is set to the high level, and the bit line BL0 of the selected column is set to the high level. The read word line RWL of the non-selected row is set to the low level, and the bit lines of the non-selected column including the bit line BL1 are set to the high level.

  Further, the column selection signal YSEL0 for the selected column is set to a high level, and the column selection signals for the unselected columns including the column selection signal YSEL1 are set to a low level. The inverted signal / YSEL0 of the column selection signal YSEL0 is set to the low level, and the inverted signal of the column selection signal of the non-selected column including / YSEL1 is set to the high level. All the write word lines WWL are set to a low level.

  By such a data read operation, it is possible to prevent all unselected memory cells from undergoing read disturb as in the second embodiment. At this time, the read transfer gate RT1 of all the memory cells connected to the read word line RWL in the same row as the selected memory cell MC1 is turned on. However, in the memory cells other than the selected memory cell MC1, both the bit line BL and the inverted signal / YSEL of the column selection signal are at the high level. Therefore, even when the read driving transistor RD1 is turned on according to the data of the storage node N0, the read transistor does not flow a cell current. As a result, power consumption during data reading can be reduced.

  Note that, in the configuration of the memory cell array shown in FIG. 15, the gate terminal of the read driving transistor RD1 is not the storage node N0 common to the gate terminal of the driving transistor D1, but the memory common to the gate terminal of the driving transistor D0. You may change so that it may connect with the node N1. Even in such a configuration, the same effect as the memory cell array of FIG. 15 can be obtained by changing the logic at the time of data reading.

(Sixth embodiment)
The sixth embodiment is a modification of the third embodiment, and reduces the power consumption by reducing the cell current flowing through the read transistor (comprising RD1 and RT1). I have to.

  FIG. 17 is a circuit diagram centering on an SRAM memory cell MC according to the sixth embodiment of the present invention. The source terminal of the read drive transistor RD1 is connected to the read column selection line / YSELR. The readout column selection line is supplied with an inversion signal / YSELR of the readout column selection signal YSELR at the time of readout. Other configurations are the same as those of the memory cell MC of FIG.

  Next, the configuration of the memory cell array included in the SRAM will be described. FIG. 18 is a circuit diagram mainly showing two memory cells MC1 and MC2 included in the memory cell array. FIG. 18 shows two adjacent memory cells MC1 and MC2 in the same row.

  The configurations of the memory cells MC1 and MC2 are the same as those in FIG. Memory cells MC1 and MC2 are connected to the same word line WL. A write bit line WBL0, a read bit line RBL0, a read column selection line / YSELR0, and a write column selection line YSELW0 are connected to the memory cell MC1. A write bit line WBL1, a read bit line RBL1, a read column selection line / YSELR1, and a write column selection line YSELW1 are connected to the memory cell MC2.

  Hereinafter, the data write operation and data read operation of the SRAM will be described with reference to FIG. FIG. 19 is a timing chart for explaining the data write operation and read operation of the SRAM.

  First, the data write operation of the SRAM will be described. An example will be described in which the memory cell MC1 is selected and data is written to the selected memory cell MC1.

  The word line WL of the selected row is set to the high level. One of the pair of write bit lines WBL0 and WBL1 in the selected column is set to the high level and the other is set to the low level according to the data to be written. The word line WL of the non-selected row is set to the low level, and the write bit line (that is, the write bit line other than WBL0 and WBL1) of the non-selected column is set to the high level.

  Further, the write column selection signal YSELW0 for the selected column is set to a high level, and the write column selection signal for non-selected columns including YSELW1 is set to a low level. All read bit lines RBL are set to a high level. The inversion signal / YSELR of all read column selection signals YSELR is set to a high level.

  By such a data write operation, it is possible to prevent the unselected memory cell from undergoing a write disturb, as in the third embodiment. Further, the read bit lines RBL and the read column selection line / YSELR that are connected in a one-to-one relationship via the read transistors composed of RD1 and RT1 are all at the same level. Therefore, the cell current does not flow through the read transistor when data is written. As a result, power consumption during data writing can be reduced.

  Next, the data read operation of the SRAM will be described. Note that, similarly to the data write operation, a case where the memory cell MC1 is selected and data of the selected memory cell MC1 is read will be described as an example.

  The word line WL of the selected row is set to the high level, and the read bit line RBL0 of the selected column is set to the high level. The unselected row word line WL is set to the low level, and the read bit lines of the unselected column including the read bit line RBL1 are set to the high level.

  Further, the inversion signal / YSELR0 of the read column selection signal for the selected column is set to a low level, and the inversion signal of the read column selection signal for the non-selected columns including / YSELR1 is set to a high level. All the write column selection signals YSELW are set to a low level. All the write bit lines WBL are set to a high level.

  By such a data read operation, it is possible to prevent all memory cells from undergoing read disturb as in the third embodiment. At this time, the read transfer gate RT1 of all the memory cells connected to the word line WL in the same row as the selected memory cell MC1 is turned on. However, in the memory cells other than the selected memory cell MC1, both the read bit line RBL and the inverted signal / YSELR of the read column selection signal are at the high level. Therefore, even when the read driving transistor RD1 is turned on according to the data of the storage node N0, the read transistor does not flow a cell current. As a result, power consumption during data reading can be reduced.

  Note that in the configuration of the memory cell array shown in FIG. 18, the gate terminal of the read drive transistor RD1 is not the same storage node N0 as the gate terminal of the drive transistor D1, but the same memory as the gate terminal of the drive transistor D0. You may change so that it may connect with the node N1. Even in such a configuration, the same effect as the memory cell array of FIG. 18 can be obtained by changing the logic at the time of data reading.

  The present invention is not limited to the above-described embodiment, and can be embodied by modifying the constituent elements without departing from the scope of the invention. In addition, various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the embodiments, or constituent elements of different embodiments may be appropriately combined.

FIG. 3 is a circuit diagram mainly showing memory cells MC of the SRAM according to the first embodiment of the present invention. FIG. 3 is a circuit diagram mainly showing two memory cells MC1 and MC2 included in the memory cell array according to the first embodiment. 4 is a timing chart for explaining a data write operation and a read operation of the SRAM according to the first embodiment. The figure explaining a static noise margin. FIG. 6 is a circuit diagram mainly showing a memory cell MC of an SRAM according to a second embodiment of the present invention. FIG. 6 is a circuit diagram mainly showing two memory cells MC1 and MC2 included in a memory cell array according to a second embodiment. 9 is a timing chart for explaining a data write operation and a read operation of the SRAM according to the second embodiment. FIG. 7 is a circuit diagram mainly showing an SRAM memory cell MC according to a third embodiment of the present invention; FIG. 10 is a circuit diagram mainly showing two memory cells MC1 and MC2 included in a memory cell array according to a third embodiment. 10 is a timing chart for explaining a data write operation and a read operation of the SRAM according to the third embodiment. The circuit diagram centering on the memory cell MC of SRAM which concerns on the 4th Embodiment of this invention. FIG. 10 is a circuit diagram mainly showing two memory cells MC1 and MC2 included in a memory cell array according to a fourth embodiment. 10 is a timing chart for explaining a data write operation and a read operation of the SRAM according to the fourth embodiment. The circuit diagram centering on the memory cell MC of SRAM which concerns on the 5th Embodiment of this invention. FIG. 10 is a circuit diagram mainly showing two memory cells MC1 and MC2 included in a memory cell array according to a fifth embodiment. 10 is a timing chart for explaining a data write operation and a read operation of the SRAM according to the fifth embodiment. The circuit diagram centering on the memory cell MC of SRAM which concerns on the 6th Embodiment of this invention. FIG. 10 is a circuit diagram mainly showing two memory cells MC1 and MC2 included in a memory cell array according to a sixth embodiment. 14 is a timing chart for explaining a data write operation and a read operation of the SRAM according to the sixth embodiment.

Explanation of symbols

  MC ... memory cell, IV1, IV2 ... inverter circuit, L0, L1 ... load transistor, D0, D1 ... drive transistor, N0, N1 ... storage node, T1 ... write transfer gate, TC0, TC1 ... column select transistor, RT1 ... Read transfer gate, RD1 ... Read drive transistor, SBL, /SBL...Connection node, BL ... Bit line, WL ... Word line, RBL ... Read bit line, WBL ... Write bit line, RWL ... Read word line, WWL ... Write word line, YSEL, / YSEL ... column select line, YSELW ... write column select line, / YSELR ... read column select line.

Claims (6)

First and second inverter circuits composed of MOS transistors;
A first storage node connected to an output terminal of the first inverter circuit and an input terminal of the second inverter circuit;
A second storage node connected to an input terminal of the first inverter circuit and an output terminal of the second inverter circuit;
A first write path that connects the first storage node and the first bit line and is controlled by a column selection signal during data writing;
A second write path that connects the second storage node and the second bit line and is controlled by the column selection signal when writing data;
A semiconductor memory device comprising: a memory cell comprising: a read path for transferring data stored in the first storage node or the second storage node to the first bit line when reading data . The read path includes a drive transistor, and a read transfer gate connected between the drain terminal of the drive transistor and the first bit line and made of a transistor,
A gate terminal of the driving transistor is connected to the first storage node or the second storage node;
A ground potential is applied to the source terminal of the driving transistor,
2. The semiconductor memory device according to claim 1, wherein a gate terminal of the read transfer gate is connected to a word line activated at the time of data reading. The read path includes a drive transistor, and a read transfer gate connected between the drain terminal of the drive transistor and the first bit line and made of a transistor,
A gate terminal of the driving transistor is connected to the first storage node or the second storage node;
The source terminal of the driving transistor is connected to a second column selection line to which an inverted signal of a column selection signal is supplied at the time of data reading,
2. The semiconductor memory device according to claim 1, wherein a gate terminal of the read transfer gate is connected to a word line activated at the time of data reading. The first write path includes a first column selection transistor connected between the first storage node and a first connection node, and the first connection node and the first bit line. A first write transfer gate connected between and comprising a transistor,
The second write path includes a second column selection transistor connected between the second storage node and a second connection node, and the second connection node and the second bit line. A second write transfer gate connected between and comprising a transistor,
Gate terminals of the first and second column selection transistors are respectively connected to a first column selection line;
The gate terminals of the first and second write transfer gates are connected to the word line,
4. The semiconductor memory device according to claim 2, wherein the word line is activated when data is read and when data is written. The word line includes a read word line activated at the time of data reading and a write word line activated at the time of data writing,
A gate terminal of the read transfer gate is connected to the read word line;
5. The semiconductor memory device according to claim 4, wherein gate terminals of the first and second write transfer gates are connected to the write word line, respectively. The first bit line includes a first read bit line to which read data is transferred, and a first write bit line to which write data is transferred,
The second bit line includes a second read bit line to which read data is transferred, and a second write bit line to which write data is transferred,
The read transfer gate is connected to the first read bit line,
The first write transfer gate is connected to the first write bit line;
5. The semiconductor memory device according to claim 4, wherein the second write transfer gate is connected to the second write bit line.

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