JP2009026376A - Storage circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage circuit capable of reducing the number of transistors per memory cell by sharing a reading circuit in an SRAM, and reducing a maximum current and preventing electromigration by using slow charging based on adiabatic charging. <P>SOLUTION: An SRAM circuit includes two inverters, flip-flops FF for receiving each other's output, and transfer transistors N<SB>3</SB>and N<SB>4</SB>for transmitting signals to bit lines BL and BLi_N. In this case, A signal read from a memory cell during reading is entered to a gate of an nMOSFET(N<SB>6</SB>) having a source grounded, and a circuit having a drain of the nMOSFET(N<SB>6</SB>) and the bit line BL_N grounded by an nMOSFET(N<SB>7</SB>) is shared by a plurality of memory cell lines Line<SB>1</SB>to Line<SB>N</SB>. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a memory circuit that reduces the number of transistors per memory at the time of reading from an SRAM and suppresses an increase in current density when further miniaturization is performed by a method of adiabatic charging.

  A conventional SRAM circuit configuration will be described with reference to FIG. A conventional SRAM uses, as a memory element, a flip-flop that connects two outputs to the other input using two CMOS inverters.

This circuit has transfer transistors N ₃₀₀ and N _{400. In} the data read operation, after the potentials of both bit lines BL and BL_N are set to VDD and the transfer transistors N ₃₀₀ and N ₄₀₀ are turned ON, for example, The potential of the bit line BL_N drops, but this is sensed by a sense amplifier (not shown).

In the technique shown in FIG. 8, when the potential of a bit line BL_N becomes sufficiently lowered to GND, the potential across the transfer transistor N ₄₀₀ is the VDD and GND, in this case, was miniaturized In this case, the current density becomes large, and problems such as wiring disconnection due to electromigration occur.

  In order to solve this problem, it is considered effective to use a read circuit of an SRAM (2-port SRAM, dual port SRAM) having two ports. A circuit of 2-port SRAM is shown in FIG. 9 (see Non-Patent Document 1).

In the 2-port SRAM of FIG. 9, the read bit line RBL does not need to be precharged to VDD, and may be VDD / 8. At this time, both ends of the series connection of the transfer transistors N ₂₂₀ and N ₂₁₀ become VDD / 8 and the GND potential, the current density when miniaturization is advanced can be reduced, and the problem of wiring disconnection due to electromigration is solved. Yes.
L. Chang et al., “Stable SRAM Cell Design for the 32 nm Node and beyond,” IEEE Symposium on VLSI Technology Digest of Technical Papers, pp.128-129 (2005)

  However, in the conventional technique shown in FIG. 9, in the case of such a 2-port SRAM circuit, one memory cell has eight transistors (8T), and LSI compared with 6T of a normal SRAM (see FIG. 8) having no two ports. There was a problem that the area would increase.

  An object of the present invention has been made in view of the above, and by sharing a read circuit in an SRAM, the number of transistors per memory cell can be reduced, and further, gentle charging by adiabatic charging is used. An object of the present invention is to provide a memory circuit that can reduce the maximum current and prevent electromigration.

  In order to solve the above problem, the present invention according to claim 1 is directed to two inverters, a pair of flip-flops having outputs of each other as inputs, and signals between the flip-flops and the bit lines. A storage transistor for transmitting and receiving data, and at the time of reading the data, a read signal from the memory cell is input to the gate portion of the nMOSFET whose source is grounded, The nMOSFET has a drain circuit and a bit line connected by another nMOSFET, and a read circuit shared by a plurality of memory cell rows is provided.

  According to a second aspect of the present invention, in the first aspect, the two read circuits are arranged, and one of the signals of the two bit lines is high impedance when the data is read, and the other is By using a flip-flop composed of two CMOS inverters to be in the GND state and reading these signals, and using the adiabatic signal that gently changes the power supply voltage of the flip-flop using the flip-flop as a sense amplifier The high impedance bit line is set to a high voltage state while the GND state bit line is set to the GND state, thereby reading data.

  According to a third aspect of the present invention, in the first aspect, the word line of the nMOSFET that transmits the read signal is gradually boosted from GND to a high voltage, and the read is performed while checking the state of the bit line.

Further, according to a fourth aspect of the present invention, in any one of the first to third aspects, the memory cell includes:
A first voltage input for inputting a voltage changing from a high voltage to a low voltage in a time longer than the time constant of the flip-flop circuit to the source electrode of each pMOS transistor in the flip-flop through the memory cell power line. Means,
One of the flip-flop circuits is set to GND, and a voltage for changing from a low voltage to a high voltage is input to one input terminal of the flip-flop circuit for a time longer than the time constant of the flip-flop circuit. Voltage input means;
The present invention according to claim 5 further includes a switch between the memory cell power supply line and the power supply line according to claim 4, and the memory is written when the data is written. After the potential of the cell power supply line is reduced, the switch is turned OFF, the memory cell power supply line is set to high impedance, and while the one bit line is in the GND state, the other bit line is gently boosted to perform the writing. Do.

  According to the present invention, the number of transistors per memory cell can be reduced by sharing the readout circuit in the SRAM, and further, the maximum current can be reduced and the electromigration can be generated by using gentle charging by adiabatic charging. It is possible to provide a memory circuit that can prevent the above.

<First Embodiment>
FIG. 1 shows a first embodiment of the present invention.

As shown in FIG. 1, in an SRAM circuit having two inverters and having transfer transistors N ₃ and N ₄ for transmitting a signal to bit lines BL and BLi_N, and a flip-flop FF having outputs of each other as inputs. A read signal from the memory cell at the time of reading is input to the gate portion of the nMOSFET (N ₆ ) whose source is grounded, and the drain of the nMOSFET (N ₆ ) and the bit line BL_N are connected by the nMOSFET (N ₇ ). Is shared by a plurality of memory cell rows Line _{1 to} Line _N.

The operation method is as follows. That is, when the write word line RWL is Low, the word line WL ₁ and WL ₂ and WWL is set to High. As a result, the bit lines BL and BL_N are connected to the flip-flop FF in the memory cell. Writing can be performed by inputting a signal smaller than VDD / 2 to one of the bit lines and VDD to the other.

At the time of reading, WWL is set to Low, RWL is set to High, WL _{1 is set} to Low, and WL _{2 is set} to High. Thus, when the signal transmitted through N ₄ is High, the input of the nMOSFET (N ₆ ) is High, so that N ₆ is turned ON. N ₇ is ON because RWL is High, and therefore BL_N is grounded to GND. If the bit line is precharged to a certain voltage in advance and a potential drop is confirmed, it can be seen that the output signal for transmitting N ₄ is High. Conversely, when the potential drop cannot be confirmed, it can be seen that the output signal for transmitting N ₄ is Low.

  The precharge voltage does not need to be VDD, and may be VDD / 2, VDD / 4, or VDD / 8 as long as the voltage drop can be confirmed. In the case of VDD / 8, the voltage becomes 1/8 times and the electromigration problem can be solved.

By this method, the number of transistors in one memory cell can be reduced. Consider a case where eight memory cell rows are connected to the divided bit line BLi_N. At this time, Line ₁ to Line ₈ are connected. In this case, the average number of transistors in one memory cell is [6 × 8 + 3] /8=6.375. Since there are eight conventional circuits, 6.375 / 8 = 80% of the conventional circuit. In addition, when 16 memory cell rows are connected, the average number of transistors in one memory cell is [6 × 16 + 3] /16=6.188. In this case, 6.188 / 8 = 77% of the conventional circuit.

  When compared with a 6T SRAM, which is not a 2-port SRAM, the area increase may be 6.188 / 6 = 3%.

  In the first embodiment, the transfer transistor connected to the external bit line from the flip-flop FF is one port, and is a normal single-port SRAM.

<Second Embodiment>
FIG. 2 shows a second embodiment of the present invention.

  In FIG. 2, in order to read the bit line differentially at the time of reading, the shared circuit portion of FIG. 1 is arranged not only on the right side of the bit line but also on both sides, and signals on the two bit lines are sent to the sense amplifier 1. It is characterized by reading by the above. The circuit configuration of the sense amplifier is shown in FIG.

2, the bit line at the time of reading, for example, the input of the _{N 10} is High, the input of the _{N 6} is the Low, BL is GND state, BL_N is high impedance state. In such a situation, the GND state remains the GND state, and the high impedance state is set to VDD. This can be realized as follows. That is, in a memory circuit that represents a distinction between logic “1” and “0” by the high impedance and low impedance of a bit line, a memory cell of “1” and a memory cell of “0” are paired, and the memory cell of the pair Each bit line is connected to a differential sense circuit, and a power clock having a waveform that gradually rises to the power supply voltage of the differential sense circuit is used. After the power clock rises, the high potential appearing on each bit line Take out voltage and low potential voltage. This method is also used in a circuit having an SRAM read sharing circuit.

  As for the operation, when the bit line is sensed in the sense amplifier 1 shown in FIG. 3, the adiabatic signal AS for gradually adiabatically increasing from GND to VDD is input to the power supply voltage of the flip-flop FF of the sense amplifier 1. .

  Here, the word “insulation” will be explained. Insulation is used in the case of changing the system very slowly in physics. Thus, “adiabatically boosting” means a method of charging more slowly than the time constant of the memory cell circuit.

<Third Embodiment>
FIG. 4 shows a third embodiment of the present invention. FIG. 4 shows a circuit configuration characterized in that the voltage of the word line is gradually changed during reading. In the configuration of the third embodiment, the voltage of the bit line (bit line) is read out by the control circuit C ₁ for controlling the voltage of the word line WL and the desired voltage of the word line WL by the sense amplifier 2, and the output thereof results comprises a circuit for setting the potential of the bit line by the control circuit C ₂ based on. By changing the gate voltage of the transfer transistor adiabatically, the current flowing through the transfer transistor can be reduced.

Precharge BL_N is performed via the P _31. The precharge voltage need not be VDD as before, and may be, for example, VDD / 8.

Next, after setting RWL to High, WL ₂ is changed stepwise from GND to VDD.

FIG. 4 shows an example in which WL ₂ is changed stepwise, but RWL may be changed stepwise. That is, WL ₂ may be changed stepwise from GND to VDD, and then RWL may be changed stepwise from GND to VDD.

  Further, the method of changing in a stepwise manner is conceivable in addition to this, and is not limited to the above.

<Fourth Embodiment>
FIG. 5 shows a fourth embodiment of the present invention.

FIG. 5 is a circuit in which the circuit of FIG. 1 is developed and has a switch between a memory cell power line (MCPL) and VDD, and between MCPL and GND. This circuit is characterized in that MCPL is turned off at the time of writing, switch S ₁ is turned off, switch S ₂ is turned on to change from VDD to GND, then switch S ₂ is turned off, and the memory cell power supply line is set to high impedance. To do. In the fourth embodiment, a time longer than the time constant of the voltage flip-flop circuits of the source electrode of each pMOS transistor of the flip-flop circuit in a state where switching element S ₂ provided in the memory cell power supply line is turned on in the high voltage is stepped down to a low voltage, after the voltage of the source electrode becomes a low voltage, the switching element S ₂ is turned off and switching element S ₂ is then turned off, the one input terminal of the flip-flop circuit The voltage is boosted from a low voltage to a high voltage in a time longer than the time constant of the flip-flop circuit.

In FIG. 5, writing can be performed by inputting the adiabatic signal A ₂ to BL with BLi_N set to GND.

<Fifth Embodiment>
FIG. 6 shows a fifth embodiment of the present invention.

FIG. 6 shows a further development of the configuration shown in the first embodiment, which is a circuit having two ports having a read port (N ₅₄ ) and a write port (N ₅₃ , N ₅₈ ). is there.

At the time of writing, writing is performed using the bit lines BLW and BLW_N using N ₅₃ and N ₅₈ transfer transistors. At the time of reading, reading is performed using the bit line BLR using a circuit composed of N ₅₄ , N ₆ and N ₇ . In this embodiment, while the writing in the memory cell of Line ₁ in Block _1, that performs reading the memory cells of different Line _N within Block _1, it is possible to realize the characteristics of the dual-port SRAM . Also, while writing to the memory cells of Line ₁ in Block _1, it is also possible to perform the reading in the memory cell with the Block _N.

<Sixth Embodiment>
FIG. 7 shows a sixth embodiment of the present invention.

FIG. 7 is a configuration obtained by further developing the configuration shown in the second embodiment, and is a circuit having two ports having a read port (N ₆₃ , N ₆₄ ) and a write port (N ₆₅ , N ₆₆ ). This is a dual port SRAM. At the time of writing, WL ₁ is set high and WL ₂ is set low, and writing is performed using the bit lines BLW and BLW_N. At the time of reading, WL _{1 is set} to Low, WL _{2 is set} to High, and RWL is set to High. Then, reading is performed using the bit lines BLR and BLR_N. In this embodiment, while the writing in the memory cell of Line ₁ in Block _1, that performs reading the memory cells of different Line _N within Block _1, it is possible to realize the characteristics of the dual-port SRAM . Also, while writing to the memory cells of Line ₁ in Block _1, it is also possible to perform the reading in the memory cell with the Block _N.

  According to the first to sixth embodiments described above, it is possible to reduce the number of transistors per memory cell by sharing the readout circuit in the SRAM, and furthermore, by using gentle charging by adiabatic charging. In addition, a memory circuit that can reduce the maximum current and prevent electromigration can be provided.

1 is a circuit diagram of a memory circuit according to a first embodiment of the present invention. FIG. 3 shows a circuit diagram of a memory circuit according to a second embodiment of the present invention. FIG. 3 shows a circuit diagram of a sense amplifier according to a second embodiment of the present invention. FIG. 5 shows a circuit diagram of a memory circuit according to a third embodiment of the present invention. FIG. 6 shows a circuit diagram of a memory circuit according to a fourth embodiment of the present invention. FIG. 6 shows a circuit diagram of a memory circuit according to a fifth embodiment of the present invention. FIG. 9 shows a circuit diagram of a memory circuit according to a sixth embodiment of the present invention. It is a figure which shows the circuit of the conventional SRAM. It is a figure which shows the conventional 2-Port SRAM circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 ... Sense amplifier AS ... Adiabatic signal C1, C2 ... Control circuit Cell ... Cell BL, BL_N ... Bit line FF ... Flip-flop WL ... Word line SW ... Switch P1, P2, P31, P41, P42 ... pMOS transistor N1- N10, N31, N41, N42, N53, N54, N58, N63 to N66 ... nMOS transistors IN, A, B ... input signals OUT ... output signals

Claims (5)

It has two inverters, a pair of flip-flops whose outputs are mutual inputs, and a transfer transistor that transmits a signal between the flip-flops and the bit line, and performs data writing and reading In a memory circuit for
At the time of reading data, a read signal from the memory cell is input to the gate portion of the nMOSFET whose source is grounded, and the drain and bit line of the nMOSFET are connected by another nMOSFET and shared by a plurality of memory cell rows. A memory circuit comprising a reading circuit. Two readout circuits are arranged, and when reading the data, one of the signals of the two bit lines is in a high impedance state and the other is in a GND state, and two CMOS inverters are used to read out the signals. And the adiabatic signal that gently changes the power supply voltage of the flip-flop, and using the flip-flop as a sense amplifier, the bit line in the GND state remains in the GND state, 2. The memory circuit according to claim 1, wherein the impedance bit line is set to a high voltage state, thereby reading data. 2. The memory circuit according to claim 1, wherein the nMOSFET word line for transmitting a read signal is gradually boosted from GND to a high voltage, and reading is performed while checking the state of the bit line. The memory cell is
A first voltage input for inputting a voltage changing from a high voltage to a low voltage in a time longer than the time constant of the flip-flop circuit to the source electrode of each pMOS transistor in the flip-flop through the memory cell power line. Means,
One of the flip-flop circuits is set to GND, and a voltage for changing from a low voltage to a high voltage is input to one input terminal of the flip-flop circuit for a time longer than the time constant of the flip-flop circuit. Voltage input means;
The memory circuit according to claim 1, further comprising: A switch is provided between the memory cell power supply line and the power supply line, and when the data is written, the switch is turned off after the potential of the memory cell power supply line is reduced, and the memory cell power supply line is set to high impedance. 5. The memory circuit according to claim 4, wherein the writing is performed by gently boosting the other bit line while keeping one bit line in the GND state.

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