JP4045023B2 - Synchronous memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory device, and more particularly to a memory device that reads and writes data in synchronization.
[0002]
[Prior art]
FIG. 13 shows a conventional example. In the conventional example, an X address input buffer for inputting X address data, a Y address input buffer for inputting Y address data, and the address data held in the input buffer are transferred to a first clock signal (CLK1 ), The X address input latch and the Y address input latch for fetching and outputting, the X decoder for decoding the address data from the input latch, the Y decoder, and the address data from the decoder for the second clock signal (CLK2) Based on the output of the X decoder latch, the Y decoder latch, and the X, Y decoder latch that captures and outputs, the data held in a predetermined plurality of memory cells is output via the bit line, and Write data is written to a predetermined number of memory cells via bit lines A memory cell array having a plurality of memory cells, a sense amplifier for amplifying a data signal output from a plurality of predetermined bit lines, and an output of the Y decoder latch from the plurality of data of the sense amplifier Based on the above, a selector that selects one data, an output latch that captures and outputs the data from the selector by a third clock signal (CLK3), and an output that holds and outputs the data from the output latch A buffer, an input buffer for inputting write data, the write data held in the input buffer by CLK1, and a write data input latch for outputting and outputting, and a write data from the write data input latch by CLK2 Write data latch to capture, output, and the above The write data from the write data latch is held in the input buffer based on the output of the Y decoder latch, the input buffer for inputting the control signal, and the input buffer. The control signal input latch that captures and outputs the control signal by CLK1, the control signal latch that captures and outputs the control signal from the control signal input latch by CLK2, and the control signal from the control signal latch. The read / write control circuit that inputs and outputs control signals for the write circuit and the sense amplifier, and a CLK generation circuit that generates clock signals (CLK1, CLK2, and CLK3) from the external clock signal to each latch. The
[0003]
FIG. 14 shows a simplified flow of addresses, data, and clocks in the conventional example of FIG. First, the address is held in the address latch through the input buffer. Thereafter, when CLK1 is input to the address latch, the address is output from the latch, and the address is decoded by the predecoder and the decoder and held in the decoder latch. Thereafter, when CLK2 is input to the decoder latch, the decoded address is output, and the memory cell based on the decoding is selected. Thereafter, data is output from the selected memory cell and amplified by a sense amplifier. As for the amplified data, one data is selected by the selector and held in the output data latch. Thereafter, when CLK3 is input to the output data latch, data is output to the outside of the chip through the output buffer.
[0004]
FIG. 15 shows operation waveforms at the time of reading in the conventional example. First, an address is input from the outside of the chip and is held in an address latch through an input buffer. Thereafter, CLK1 is input to the address latch after t1 from the first external clock input (1st), and the address data is output. The output is held in the decoder latch after ta. Then, after t2 from the second external clock input (2nd), CLK2 is input to the decoder latch and an address decode signal is output. A word line is selected based on the output, data is read from the memory cell, and amplified by a sense amplifier. Thereafter, one data is selected by the selector, and the selected data is held in the output latch. The required time during this time is tb. Finally, CLK3 is input to the output latch after t3 from the third external clock input (3rd), and output data is output. The output data is output to the outside of the chip through the output buffer after tc. At this time, t3 + tc = tack (clock access time). In order to guarantee the above operation, t1 + ta <tcycle (cycle time) + t2, t2 + tb <tcycle + t3 must be satisfied.
[0005]
FIG. 16 shows operation waveforms at the time of writing in the conventional example. First, write data is input from the outside of the chip and is held in a write data input latch through an input buffer. Next, CLK1 is input to the write data input latch t1w after the first external clock input (1St), and the write data is output. The output is held in the write data latch after taw. Then, after t2w from the second external clock input (2nd), CLK2 is input to the write data latch and the write data is output. The output is input to a writing circuit, and is written in the memory cell based on the X address and the Y address. The required time during this period is tbw. As a result, the write time tw becomes tw = tcycle + t2w + tbw. In order to guarantee the above operation, t1w + taw <tcycle + t2w must be satisfied.
[0006]
A circuit having such a configuration is disclosed in, for example, Japanese Patent Application Laid-Open No. 64-21786.
[0007]
Further, as a circuit using a plurality of latches, JP-A-01-204292, JP-A-03-122895, JP-A-4-85779, JP-A-4-358392, JP-A-09-223393 are disclosed. JP-A 09-251774.
[0008]
[Problems to be solved by the invention]
In general, the cycle time of a synchronous memory device is limited by the maximum delay time between an input latch that holds data of an address signal and a chip selection signal and an output latch for outputting data. Cannot be shorter than this time interval.
[0009]
Therefore, a method has been proposed in which an intermediate latch is provided separately from the input latch and the output latch to reduce the delay time between the latches and shorten the cycle time. This is shown in the prior art.
[0010]
However, in the conventional example, since a latch is provided in a portion where the number of signal lines such as word lines is large, there is a problem that the number of latch circuits inevitably increases and the chip area increases. For example, in a 2M bit CMOS cache SRAM (× 36), since there are 8 X addresses and 8 Y addresses, 512 decoder latches are required.
[0011]
In the conventional example, two cycles are always required for writing to the memory cell. Therefore, the writing time cannot be shortened to 1 cycle time or less.
[0012]
An object of the present invention is to provide a synchronous memory device that suppresses an increase in chip area caused by insertion of a latch circuit for shortening the cycle time.
[0013]
Another object of the present invention is to provide a synchronous memory device that shortens the writing time.
[0014]
[Means for Solving the Problems]
To achieve the above object, the synchronous memory device according to the present invention eliminates the address decoder latch in the conventional example, provides a selector output latch between the selector and the output latch, and writes the data latch and control signal in the conventional example. It is characterized by eliminating the latch.
[0015]
In order to achieve the above object, the address decoder latch in the conventional example is abolished, a latch is provided between the selector address decoder and the selector and between the sense amplifier and the selector, and the write data latch and the control signal latch in the conventional example are abolished. It is characterized by doing.
[0016]
Further, in order to achieve the above object, the address decoder latch in the conventional example is abolished, a latch is provided between the Y address predecoder and the selector address decoder and between the sense amplifier and the selector, and the write data latch and the control signal in the conventional example are provided. It is characterized by eliminating the latch.
[0017]
In the embodiment of the present invention described above, a more preferable embodiment uses at least two latches (or flip-flops). The latch configuration is an edge trigger type latch. It is assumed that at least two latches are in the subsequent stage of the sense amplifier, more preferably in the subsequent stage of the selector.
[0018]
The present invention makes it possible to realize a read latency 4 associated with an increase in SRAM speed (for example, a clock frequency of 200 MHz or more) by using a plurality of latches. That is, in the present invention, three cycles of the clock are consumed from the input of an address to the output of output data. In the conventional technique, when the read latency is 3, for example, two cycles of the clock are consumed from the input of the address to the output of the output data. Therefore, when the delay time from the address input to the output of the output data is the same, the latency 4 circuit can speed up the clock cycle compared to the latency 3 circuit.
[0019]
Further, it is preferable to use an edge trigger type latch for speeding up the clock cycle. As a concept corresponding to the edge trigger type latch, there is a level trigger type latch. However, as the clock cycle speeds up, the data latch becomes difficult in the level trigger type latch. The edge trigger type latch usually has a circuit configuration in which two level trigger type latches are connected in series.
[0020]
Specifically, the edge trigger type latch circuit includes a first latch and a second latch connected in series. For example, the edge trigger type latch circuit includes a first inverter and a second inverter connected in series. A first switch in the previous stage and a second switch between the first inverter and the second inverter are provided, and the first switch and the second switch operate in a complementary manner.
[0021]
The location where the latch is inserted is also important. In the present invention, an increase in circuit scale can be avoided by using a plurality of latches and disposing the latches at locations where the number of signal lines is small. For example, if a latch is provided for the bit line before the sense amplifier, a latch circuit is required for the bit line, and the circuit scale increases significantly. However, as in the present invention, the latter stage of the sense amplifier, more preferably the rear stage of the selector. The number of latch circuits can be reduced. In particular, since the edge trigger type latch requires twice the circuit scale as compared with the level trigger type latch, such circuit scale compression is important. In addition, the latch circuit is preferably after the sense amplifier in view of the delay time distribution.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of a synchronous memory device according to the invention will be described with reference to the accompanying drawings.
[0023]
FIG. 1 shows a first embodiment of a synchronous memory device according to the present invention. FIG. 1 shows an X address input buffer for inputting X address data, a Y address input buffer for inputting Y address data, and the address data held in the input buffer as a first clock signal (CLK1). ), An X address input latch and a Y address input latch for fetching and outputting, a decoder for decoding the X and Y address data from the input latch, and a plurality of predetermined memories based on the decoding of the X and Y decoder The data stored in the cell is output via a bit line, and a memory cell array including a plurality of memory cells in which write data is written via a bit line to a predetermined plurality of memory cells is output. A sense amplifier for amplifying data signals from a plurality of predetermined bit lines; Based on the decoding of the Y address decoder based on the Y address decoder, a selector output latch for fetching and outputting the data from the selector by the second clock signal (CLK2), and the selector output An output latch that captures and outputs data from the latch by a third clock signal (CLK3), an output buffer that holds and outputs data from the output latch, and a write data input buffer for inputting write data And the write data input latch that captures and outputs the write data held in the write data input buffer by CLK1, and the write data from the write data input latch is decoded based on the decoding of the Y address decoder. Cell array A write circuit for writing to the memory cell, a control signal input buffer for inputting a control signal, a control signal input latch for capturing and outputting the control signal held in the control signal input buffer by CLK1, and the control signal A control signal from the input latch is input, and a read / write E control circuit that outputs the control signal of the write circuit and the sense amplifier, and a clock signal (CLK1, CLK2, CLK3) from the external clock signal to each latch are generated. And a CLK generation circuit.
[0024]
When the above configuration is used, in the 2M bit CMOS cache SRAM (× 36), the decoder latch circuit which is 512 in the conventional example can be replaced with 36 selector output latch circuits. That is, the number of latch circuits is reduced to about 1/13. As a result, an increase in chip area caused by insertion of a latch circuit for shortening the cycle time can be suppressed. In the above configuration, the write data latch and the control signal latch required in the conventional example can be deleted, so that the increase in the number of latch circuits can be suppressed. In the 2M bit CMOS cache SRAM (× 36), a total of 37 write data latch circuits and control signal latch circuits can be deleted from the conventional example.
[0025]
FIG. 2 shows a simplified flow of addresses, data, and clocks in the first embodiment shown in FIG. First, the address is held in the address latch through the input buffer. Thereafter, when CLK1 is input to the address latch, the address is output from the latch, and the address is decoded by the predecoder and the decoder. A memory cell is selected based on this decoding. Thereafter, data is output from the selected memory cell and amplified by a sense amplifier. As for the amplified data, one data is selected by the selector and held in the selector output latch. Thereafter, when CLK2 is input to the selector output latch, data is output and held in the output data latch. Thereafter, when CLK3 is input to the output data latch, data is output to the outside of the chip through the output buffer.
[0026]
FIG. 3 shows operation waveforms at the time of reading in the first embodiment shown in FIG. First, an address is input from the outside of the chip and is held in an address latch through an input buffer. Thereafter, CLK1 is input to the address latch after t13 from the first external clock input (1St), and the address data is output. The output is decoded through a predecoder and a decoder, a word line is selected based on the decoding, data is read from the memory cell, and amplified by a sense amplifier. Thereafter, one data is selected by the selector, and the selected data is held in the selector output latch. The required time during this period is ta3. Thereafter, after t23 from the second external clock input (2nd), CLK2 is input to the selector output latch and data is output. The output is held in the output latch after tb3. Finally, CLK3 is input to the output latch after t33 from the third external clock input (3rd), and output data is output. The output data is output to the outside of the chip through the output buffer after tc3. At this time, t33 + tc3 = tack (clock access time). In order to guarantee the above operation, t13 + ta3 <tcycle + t23 and t23 + tb3 <tcycle + t33 must be satisfied. As described above, in the configuration of the first embodiment shown in FIG. 1, data can be output to the outside of the chip in the third cycle as in the conventional example.
[0027]
FIG. 4 shows operation waveforms at the time of writing in the first embodiment shown in FIG. First, write data is input from the outside of the chip and is held in a write data input latch through an input buffer. Next, after t14 from the first external clock input (1St), CLK1 is input to the write data input latch, and the write data is output. The output is input to a writing circuit, and is written in the memory cell based on the X address and the Y address. The required time during this period is ta4. As a result, the write time tw4 is tw4 = t14 + ta4. As described above, in the first embodiment, the decoder latch is abolished so that the word line can be selected in the first cycle, and the write data latch and the control signal latch are deleted and the first cycle is written. Since the data can reach the memory cell, the data can be written in the first cycle. Therefore, the writing time can be shortened as compared with the conventional example in which data is written in the second cycle. In FIG. 16, when t1w + taw <tcycle, it can be shortened by about ((tcycle− (t1w + taw)) + t2w), and when t1w + tow> tcycle, it can be shortened by about (t2w − ((t1w + taw) −tcycle)).
[0028]
FIG. 5 shows a second embodiment of the synchronous memory device of the present invention. FIG. 5 shows an X address input buffer for inputting X address data, a Y address input buffer for inputting Y address data, and the address data held in the input buffer as a first clock signal (CLK1). ) To capture and output X address input latch and Y address input latch, X and Y predecoders for predecoding X and Y address data from the input latch, and X and Y from the X and Y predecoders. Based on the X and Y decoders for decoding the predecoded data, and the decoding of the X and Y decoders, the data held in a predetermined plurality of memory cells are output via the bit lines, A memory cell array having a plurality of memory cells into which write data is written via a bit line. A sense amplifier that amplifies signals of data output from a plurality of predetermined bit lines, a sense amplifier output latch that captures and outputs the output of the sense amplifier by a second external clock (CLK2), and the Y A selector address latch that captures and outputs the output of the predecoder by a second external clock (CLK2), a first selector address decoder that decodes predecoded data from the selector address latch, and a sense amplifier output latch A selector that selects one data from a plurality of data based on the decoding of the first selector address decoder; an output latch that captures and outputs the data from the selector by a third clock signal (CLK3); Holds data from the output latch and outputs Output buffer, a write data input buffer for inputting write data, a write data input latch for capturing and outputting the write data held in the write data input buffer by CLK1, and an output of the Y predecoder A second selector address decoder for decoding the write data, a write circuit for writing the write data from the write data input latch into the memory cells of the memory cell array based on the decode of the second selector address decoder, and a control signal A control signal input buffer for inputting, a control signal input latch for capturing and outputting the control signal held in the control signal input buffer by CLK1, and a control signal from the control signal input latch are input. Writing circuit and A Database of / WRITE control circuit for outputting a control signal of the serial sense amplifier composed of a CLK generating circuit for generating a clock signal (CLK1, CLK2, CLK3) to each latch from the external clock signal. At this time, when the Y address fetched by the first external clock and the Y address fetched by the second external clock are equal to one or more bits and the address is a selector address, as shown by a dotted line in FIG. The address may be input directly to the first selector address decoder without being input to the address latch. The selector address latch may be disposed between the first selector address decoder and the selector. At this time, the first and second selector address decoders may be shared.
[0029]
When the above configuration is used, in the 2M-bit CMOS cache SRAM (× 36), the decoder latch circuit, which is 512 in the conventional example, only needs 72 sense amplifier output latch circuits and two selector address latch circuits. That is, the number of latch circuits is reduced to about 1/6. As a result, an increase in chip area caused by insertion of a latch circuit for shortening the cycle time can be suppressed. In the above configuration, the write data latch and the control signal latch required in the conventional example can be deleted, so that the increase in the number of latch circuits can be suppressed. In the 2M bit CMOS cache SRAM (× 36), a total of 37 write data latch circuits and control signal latch circuits can be deleted from the conventional example.
[0030]
FIG. 6 shows a simplified flow of addresses, data, and clocks in the second embodiment shown in FIG. First, the address is held in the address latch through the input buffer. Thereafter, when CLK1 is input to the address latch, the address is output from the latch, and the address is decoded by the predecoder and the decoder. A memory cell is selected based on this decoding. Thereafter, data is output from the selected memory cell and amplified by a sense amplifier. The amplified data is held in the sense amplifier output latch. Part of the address predecoded by the predecoder is held in the selector address latch. Thereafter, when CLK2 is input to the selector address latch, the output is decoded by the selector address decoder and input to the selector. When CLK2 is input to the sense amplifier output latch, the data is input to the selector, and one data is selected based on the decoding of the selector address decoder and held in the output data latch. Thereafter, when CLK3 is input to the output data latch, data is output to the outside of the chip through the output buffer.
[0031]
FIG. 7 shows operation waveforms at the time of reading in the second embodiment shown in FIG. First, an address is input from the outside of the chip and is held in an address latch through an input buffer. Thereafter, CLK1 is input to the address latch after t17 from the first external clock input (1St), and the address data is output. The output is decoded through a predecoder and a decoder, and a word line is selected based on the decoding. Thereafter, a plurality of data is read from the memory cell, the plurality of data is amplified by the sense amplifier, and held in the sense amplifier output latch. The required time during this period is ta71. A part of the output of the predecoder is held in the selector address latch as a selector address. At this time, the required time from the address latch input of CLK1 is ta70. In FIG. 7, ta70 <ta71 is assumed, but ta70> ta71 may be satisfied. Thereafter, CLK2 is input to the selector latch after t270 from the second external clock input (2nd), and the predecode signal of the selector address is output. The output is decoded by the selector address decoder and input to the selector. CLK2 is input to the sense amplifier output latch after t271 from the second external clock input (2nd) (t270 <t271 in FIG. 7 but may be t270> t271), and the plurality of data is output. The The plurality of outputs are input to the selector. Thereafter, the selector selects one data from the plurality of data based on the decode signal, and the selected data is held in the output latch. The required time during this period is tb70 from the selector address input of CLK2 and tb71 from the sense amplifier output latch input of CLK2. Finally, CLK3 is input to the output latch after t37 from the third external clock input (3rd), and output data is output. The output data is output to the outside of the chip through the output buffer after tc7. At this time, t37 + tc7 = tack (clock access time). In order to guarantee the above operation, t17 + ta70 <tcycle + t270, t17 + ta71 <tcycle + t271, t270 + tb70 <tcycle + t37, and t271 + tb71 <tcycle + t37 must be satisfied. Thus, in the configuration of the second embodiment shown in FIG. 5, data can be output to the outside of the chip in the third cycle as in the conventional example.
[0032]
The operation waveform at the time of writing in the second embodiment shown in FIG. 5 is the same as the operation waveform at the time of writing in the first embodiment (FIG. 4). Therefore, in the second embodiment, like the first embodiment, the decoder latch is abolished so that the word line can be selected in the first cycle, and the write data latch and the control signal latch are deleted as in the first embodiment. Since the write data can reach the memory cell in the first cycle, the data can be written in the first cycle. Therefore, the writing time can be shortened as compared with the conventional example in which data is written in the second cycle.
[0033]
FIG. 8 shows a third embodiment of the synchronous memory device of the present invention. FIG. 8 shows an X address input buffer for inputting X address data, a Y address input buffer for inputting Y address data, and the address data held in the input buffer as a first clock signal (CLK1). ) To capture and output X address input latch and Y address input latch, X and Y predecoders for predecoding X and Y address data from the input latch, and X and Y from the X and Y predecoders. Based on the X and Y decoders for decoding the predecoded data, and the decoding of the X and Y decoders, the data held in a predetermined plurality of memory cells are output via the bit lines, A memory cell array having a plurality of memory cells into which write data is written via a bit line. , A sense amplifier for amplifying data signals output from a plurality of predetermined bit lines, a sense amplifier output latch for latching the output of the sense amplifier, and an output of the Y predecoder for a second external clock (CLK2 ) To generate and output a selector address latch, a first selector address decoder for decoding predecoded data from the selector address latch, an output of the selector address decoder and a clock signal (CLK0) generated by a pulse generation circuit An AND circuit that takes the AND logic of the generated one-shot pulse (PULSE) and pulses the selector address, and selects one data from the plurality of data of the sense amplifier output latch based on the pulsed decode address Selector and the above selector An output latch that captures and outputs the data by a third clock signal (CLK3), an output buffer that retains and outputs data from the output latch, and a write data input buffer for inputting write data From the write data input latch that captures and outputs the write data held in the write data input buffer by CLK1, a second selector address decoder that decodes the output of the Y predecoder, and the write data input latch Write data to the memory cells of the memory cell array based on the decoding of the second selector address decoder, a control signal input buffer for inputting a control signal, and held in the control signal input buffer The above control signal A control signal input latch that receives and outputs by LK1, a control signal from the control signal input latch, and a read / write control circuit that outputs a control signal for the write circuit and the sense amplifier, and an external clock signal A CLK generation circuit that generates clock signals (CLK0, CLK1, CLK2, and CLK3) to each latch and a pulse generation circuit that generates PULSE from the clock signal output from the CLK generation circuit. At this time, when the Y address fetched by the first external clock and the Y address fetched by the second external clock are the same for one bit or more and the address is a selector address, as shown by a dotted line in FIG. The address may be input directly to the first selector address decoder without being input to the address latch. The selector address latch may be disposed between the first selector address decoder and the selector. At this time, the first and second selector address decoders may be shared. Further, the selector address may be pulsed between the selector address latch and the selector address decoder. At this time, when the Y address fetched by the first external clock and the Y address fetched by the second external clock are equal to one or more bits, the address directly input to the first selector address decoder The pulsing may be performed between the Y address latch and the selector address decoder.
[0034]
When the above configuration is used, in the 2M-bit CMOS cache SRAM (× 36), the decoder latch circuit, which is 512 in the conventional example, only needs 72 sense amplifier output latch circuits and two selector address latch circuits. That is, the number of latch circuits is reduced to about 1/6. As a result, an increase in chip area caused by insertion of a latch circuit for shortening the cycle time can be suppressed. In the above configuration, the write data latch and the control signal latch required in the conventional example can be deleted, so that the increase in the number of latch circuits can be suppressed. In the 2M bit CMOS cache SRAM (× 36), a total of 37 write data latch circuits and control signal latch circuits can be deleted from the conventional example.
[0035]
FIG. 9 shows a simplified flow of addresses, data, and clocks in the third embodiment shown in FIG. First, the address is held in the address latch through the input buffer. Thereafter, when CLK1 is input to the address latch, the address is output from the latch, and the address is decoded by the predecoder and the decoder. A memory cell is selected based on this decoding. Thereafter, data is output from the selected memory cell and amplified by a sense amplifier. The amplified data is held in the sense amplifier output latch. Part of the address predecoded by the predecoder is held in the selector address latch. Thereafter, when CLK2 is input to the selector address latch, the output is decoded by the selector address decoder, and is pulsed by the one-shot pulse (PULSE) generated from the clock signal by the pulse generation circuit and input to the selector. Thereafter, one data of the sense amplifier output latch is selected by the selector based on the decoding of the selector address decoder and held in the output data latch. Thereafter, when CLK3 is input to the output data latch, data is output to the outside of the chip through the output buffer.
[0036]
FIG. 10 shows operation waveforms at the time of reading in the second embodiment shown in FIG. First, an address is input from the outside of the chip and is held in an address latch through an input buffer. Thereafter, CLK1 is input to the address latch after t110 from the first external clock input (1St), and the address data is output. The output is decoded through a predecoder and a decoder, and a word line is selected based on the decoding. Thereafter, a plurality of data is read from the memory cell, the plurality of data is amplified by the sense amplifier, and held in the sense amplifier output latch. The required time during this period is ta101. A part of the output of the predecoder is held in the selector address latch as a selector address. At this time, the required time from the address latch input of CLK1 is ta100. In FIG. 10, ta100 <ta101 is set, but ta100> ta101 is also possible. After that, t2100 after the second external clock input (2nd), CLK2 is input to the selector address latch, the output is decoded by the selector address decoder, and pulsed by the one-shot pulse generated from the clock signal by the pulse generation circuit And input to the selector. At this time, the required time from the second external clock input (2nd) is t2101. Thereafter, the selector selects one data from the plurality of data based on the decoding of the selector address decoder, and the selected data is held in the output latch. The required time during this period is tb10. Finally, CLK3 is input to the output latch after t310 from the third external clock input (3rd), and output data is output. The output data is output to the outside of the chip through the output buffer after tc10. At this time, t310 + tc10 = tack (clock access time). In order to guarantee the above operation, t110 + ta100 <tcycle + t2100 and t2101 + tb10 <tcycle + t310 must be satisfied. Further, it is desirable that t110 + ta101 <tcycle + t2101 so that the data of the previous cycle is not transmitted to the subsequent stage of the selector. Thus, in the configuration of the third embodiment shown in FIG. 8, data can be output to the outside of the chip in the third cycle as in the conventional example.
[0037]
The operation waveform at the time of writing in the third embodiment shown in FIG. 8 is the same as the operation waveform at the time of writing in the first embodiment (FIG. 4). Therefore, in the third embodiment, like the first embodiment, the decoder latch is abolished and the word line can be selected in the first cycle, and the write data latch and the control signal latch are deleted as in the first embodiment. Since the write data can reach the memory cell in the first cycle, the data can be written in the first cycle. Therefore, the writing time can be shortened as compared with the conventional example in which data is written in the second cycle.
[0038]
FIG. 11 shows an example of the sense amplifier output latch circuit and the selector circuit in the third embodiment. The sense amplifier output latch circuit (LAT) is a flip-flop composed of two NANDs (NA1, NA2) that receive the outputs (SAT, SAB) of the sense amplifier (SA). The selector circuit (SEL) has a gate connected to the inverted signal (/ ASi) of the pulsed selector address decode signal and a source (PMOS) whose source is connected to one output (NT) of the sense amplifier output latch. PM1), the gate is connected to / ASi, the source is connected to the ground potential, the drain is connected to the drain (N0) of PM1 and the gate is connected to N0, and the source is connected to the ground potential. The NMOS (NM2) is connected and the drain is connected to the data line (IO). The data line is connected to the output data latch, the gate is connected to the data line precharge control signal (PR), and the source is connected to the drain of the PMOS (PM2) connected to the power supply voltage (Vdd). Has been.
[0039]
FIG. 12 shows operation waveforms of the circuit shown in FIG. An address is input in synchronization with the first external clock (1st), and the address is decoded through a predecoder and a decoder. Thereafter, a word line is selected based on the decoded address, and data is read from the memory cell. The read data is amplified by the sense amplifier (SAT, SAB) and held by the LAT (NT, NB). At this time, / ASi is at a high level, so PM1 is off. Therefore, NT (high level) data is not transmitted to N0. Thereafter, when a second external clock is input and CLK2 is input to the selector address latch, a predecode signal for the selector address is output. The output is decoded by a selector address decoder, pulsed by a one-shot pulse generated by a pulse generation circuit from a clock signal, and input to the selector. As a result, / ASi goes low, NT data is transmitted to N0, NM2 is driven, and data is transmitted to IO. At this time, since PR is at a high level, PM2 is off. Therefore, no extra current flows from Vdd to the ground potential through PM2 and NM2. Thereafter, the pulsed / ASi goes high, PM1 turns off, NM1 turns on, N0 goes low, and NM2 turns off. At this time, PR becomes low level and IO is precharged to Vdd. As a result, each node (N0, IO) is in an initial state for reading the next data.
[0040]
In each embodiment of the present invention, by using an edge trigger type latch as the latch circuit, it is possible to operate at a higher speed than the prior art. In particular, in the above-described embodiment, it is preferable to use an edge trigger type latch circuit for the sense amplifier output latch circuit and the output data latch circuit.
[0041]
17 and 18 show an example of an edge trigger type latch circuit. FIG. 19 shows the operation.
[0042]
The edge trigger type latch circuit shown in FIG. 17 includes a first latch L1 and a second latch, and a switch C is disposed between them. These switches and circuits can be composed of transistors such as MOSFETs. DATANEW is input to the input terminal of the first latch L1, and DATAOLD is output to the output terminal of the second latch L2.
[0043]
The first latch L1 has a switch A that is connected to the input terminal and inputs DATANEW, and the switch B has a polarity opposite to that of the switch A. The input terminal of switch B is coupled to the output terminal of switch A. The first latch L1 also has an inverter INV1, and the input terminal of the inverter INV1 is coupled to the output of the switch A. The inverter INV3 receives the output of the inverter INV1, and the output of the inverter INV3 is input to the switch B. The output of inverter INV1 and the input of inverter INV3 are coupled to the input of switch C. The polarity of switch C is the same as that of switch B.
[0044]
The second latch L2 has an inverter INV2 that receives the output of the switch C. The output of this INV2 is coupled to the output terminal of the latch L2 from which DATAOLD is output. The output of inverter INV2 is also coupled to the input of inverter INV4. The output terminal of inverter INV4 is coupled to the input terminal of switch D. The polarity of switch D is the same as that of switch A. The output of switch D is input to inverter INV2.
[0045]
The second example of the edge trigger type latch circuit shown in FIG. 18 includes a first latch L1 and a second latch L2. A switch C is arranged between them. DATANEW is input to the input terminal of the first latch L1, and DATAOLD is output to the output terminal of the second latch L2.
[0046]
The first latch L1 has a switch A that is connected to the input terminal and inputs DATANEW. The first latch L1 also has an inverter INV1, and the input terminal of the inverter INV1 is coupled to the output of the switch A. The output of the inverter INV1 is input to the switch C. The output of the inverter INV5 is coupled to the input of the inverter INV1, the output of the inverter INV6 is coupled to the input of the inverter INV5, and the output of the inverter INV5 is coupled to the input of the inverter INV6.
[0047]
The second latch L2 has an inverter INV2 whose input is coupled to the output of the switch C and whose output is coupled to the output terminal which outputs DATAOLD. The output of the inverter INV7 is coupled to the input of the inverter INV2, the output of the inverter INV8 is coupled to the input of the inverter INV7, and the output of the inverter INV7 is coupled to the input of the inverter INV8. Here, it is important that the polarities of the switch A and the switch C are reversed.
[0048]
The operation of the circuit of FIG. 17 will be described. When the clock is low, the switch A is turned on, and new data (DATANEW) is transmitted from the input terminal of the switch A to the input terminal of the inverter INV1. The inverter INV1 inverts DATANEW and outputs it to the input terminal of the inverter INV3 and the switch C. When switch B is off, output of DATANEW from the output terminal of inverter INV3 is prevented, and when switch C is off, output of DATANEW from the output terminal of inverter INV1 to the second latch is prevented. When switch D is on, data is allowed to be output from the output of inverter INV4 to inverter INV2, and the previous data (DATAOLD) latched in latch 2 is output from the output terminal of latch 2. Is done.
[0049]
When the clock CLK is high, the switch A is turned off, preventing the next DATANEW from being transmitted to the input terminal of the inverter INV1. When the switch B is on, DATANEW is transmitted from the output terminal of the inverter INV3 to the input terminal of the inverter INV1. Further, when the switch C is on, DATANEW is transmitted from the output terminal of the inverter INV1 to the input terminal of the inverter INV2, and becomes DATAOLD. When switch D is off, transmission of DATAOLD from the output terminal of inverter INV4 to the input terminal of inverter INV2 is hindered. That is, DATANEW supplied from the switch C to the input terminal of the inverter INV2 becomes DATAOLD latched in the second latch L2 at the next clock low, which is the output of the second latch at the next timing (clock high). Output to the terminal.
[0050]
The operation of the other edge trigger type latch described in FIG. 18 is substantially the same as described above. That is, when the clock CLK is low, the switch A is on, DATANEW is latched in the latch 1, and the switch C is off, so that DATANEW is retained in the first latch. On the other hand, the second latch L2 outputs DATAOLD to the output terminal. When the clock CLK goes high, the switch A is off and DATANEW is not input to the latch 1. Then, the switch C is turned on, and data is sent from the first latch L1 to the second latch L2. That is, DATANEW is latched by the second latch L2.
[0051]
The important points in the edge-triggered latches shown in FIGS. 18 and 19 are that data is latched at the rising or falling edge of the clock (edge trigger) and latched at the timing when the clock reaches a predetermined level ( It is not a level trigger. Such an operation method of the edge trigger type latch makes it possible to operate stably even in an apparatus having a short clock cycle.
[0052]
The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various design changes can be made without departing from the spirit of the present invention. is there.
[0053]
【The invention's effect】
As is apparent from the above-described embodiments, according to the present invention, the decoder latch circuit is eliminated, and the selector output latch or the selector address latch and the sense amplifier output latch are provided to shorten the cycle time. An increase in chip area caused by the insertion of the latch circuit can be suppressed. Further, by deleting the write data latch and the control signal latch, data can be written in the first cycle, so that the write time can be shortened.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a first embodiment of a synchronous memory device according to the present invention;
FIG. 2 is a block diagram showing a simplified flow of addresses, data, and clocks in the first embodiment.
FIG. 3 is an operation waveform at the time of reading in the first embodiment.
FIG. 4 is an operation waveform at the time of writing in the first embodiment.
FIG. 5 is a block diagram showing a second embodiment of a synchronous memory device according to the present invention;
FIG. 6 is a configuration diagram in which the flow of addresses, data, and clocks in the second embodiment is simplified.
FIG. 7 is an operation waveform at the time of reading in the second embodiment.
FIG. 8 is a configuration diagram showing a third embodiment of a synchronous memory device according to the present invention;
FIG. 9 is a configuration diagram that simplifies the flow of addresses, data, and clocks in a third embodiment;
FIG. 10 is an operation waveform at the time of reading in the third embodiment.
FIG. 11 is an example of a sense amplifier output latch circuit and a selector circuit in the third embodiment.
12 shows operation waveforms of the sense amplifier output latch circuit and the selector circuit shown in FIG.
FIG. 13 is a configuration diagram showing a form of a conventional example.
FIG. 14 is a configuration diagram in which the flow of addresses, data, and clocks in a conventional example is simplified.
FIG. 15 is an operation waveform at the time of reading in the conventional example.
FIG. 16 is an operation waveform at the time of writing in the conventional example.
FIG. 17 is a circuit diagram of an edge trigger type latch.
FIG. 18 is another circuit diagram of the edge trigger type latch.
[Explanation of symbols]
CLK0 to CLK3 ... internal clock signal, PULSE ... one shot pulse, NA0 to NA2 ... NAND circuit, SA ... sense amplifier, LAT ... sense amplifier output latch, SEL ... selector, / ASi ... inverted signal of selector address decode signal, PM1 PM2 ... PMOS transistor, NM1 to NM2 ... NMOS transistor, IO ... Data line, PR ... Data line equalize control signal, Vdd ... Power supply voltage, SAT, SAB, NT, NB, N0 ... Node name.

Claims (7)

A plurality of input buffers for receiving address data;
In accordance with a clock signal, a plurality of input latches that hold the address data held in the plurality of input buffers and output the address data;
A plurality of predecoders for predecoding address data from the plurality of input latches;
A plurality of decoders for decoding address data predecoded by the plurality of predecoders;
A memory cell array having a plurality of memory cells for holding a data signal and outputting a predetermined one of the data signals via a plurality of bit lines based on the address data decoded by the plurality of decoders;
A sense amplifier that amplifies an output data signal output to the plurality of bit lines;
A selector address latch for holding selector address data for selecting one of the amplified output data signals from the sense amplifier according to a clock signal, and outputting the selector address data;
A plurality of selector address decoders for decoding selector address data from the selector address latch;
A sense amplifier output latch that holds the amplified output data signal from the sense amplifier in accordance with a clock signal and outputs the amplified output data signal;
A selector that selects one of the amplified output data signals held in the sense amplifier output latch according to selector address data decoded by the plurality of selector address decoders;
An output latch for holding an amplified output data signal from the selector according to a clock signal;
An output buffer that receives the amplified output data signal from the output latch and outputs the amplified output data signal;
A synchronous memory device. A plurality of input buffers for receiving address data;
In accordance with a clock signal, a plurality of input latches that hold the address data held in the plurality of input buffers and output the address data;
A plurality of predecoders for predecoding address data from the plurality of input latches;
A plurality of decoders for decoding the address data predecoded by the predecoder;
A memory cell array having a plurality of memory cells that hold a data signal and output a predetermined one of the data signals through a plurality of bit lines based on the address data decoded by the decoder;
A sense amplifier that amplifies an output data signal output to the plurality of bit lines;
A sense amplifier output latch for holding an output data signal from the sense amplifier;
A selector address latch for holding selector address data for selecting one of the amplified output data signals from the sense amplifier according to a clock signal, and outputting the selector address data;
A plurality of selector address decoders for decoding selector address data from the selector address latch;
A pulsing circuit for converting selector address data decoded by the selector address decoder into a pulse signal;
A selector for selecting one of the amplified output data signals from the sense amplifier output latch based on the output pulse signal from the pulsing circuit;
An output latch for holding the amplified output data signal from the selector and outputting the amplified output data signal according to a clock signal;
An output buffer that receives the amplified output data signal from the output latch and outputs the amplified output data signal;
A synchronous memory device. The synchronous memory device according to claim 2 , wherein
The synchronous memory device, wherein the pulsing circuit is disposed between the selector address latch and the plurality of selector address decoders. The synchronous memory device according to claim 2 or 3 ,
A synchronous memory device in which part of the address data predecoded by the predecoder is directly input to the plurality of selector address decoders. The synchronous memory device according to claim 4 , wherein
The synchronous memory device, wherein the pulsing circuit is arranged between the predecoder and the selector address decoder for converting a part of the address data predecoded by the predecoder into a pulse signal. The synchronous memory device according to any one of claims 1 to 5 ,
The address data includes an X address and a Y address of the memory cell array,
The predecoder includes an X address predecoder and a Y address predecoder that predecode the X address and the Y address, respectively.
The synchronous memory device, wherein the address decoder includes an X decoder and a Y decoder for decoding the X address and the Y address, respectively. The synchronous memory device according to claim 6 , wherein
A plurality of second input buffers for receiving write data;
A plurality of second input latches for capturing and outputting write data held in the plurality of second input buffers according to a clock;
A second selector address decoder for decoding signals from the plurality of predecoders;
A write circuit for writing write data from the input latch to a plurality of memory cells of the memory cell array corresponding to the second selector address decoder;
A third input buffer to which a control signal is input;
A third input latch for capturing and outputting a control signal held in the third input buffer according to a clock signal;
A read / write control circuit that receives a control signal from the third input latch and outputs a signal for controlling the write circuit and the sense amplifier;
A synchronous memory device further comprising:

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