JPS59114640A - Signal processing processor lsi - Google Patents

Abstract

PURPOSE:To shorten remarkably a data transfer time and a processing time by inputting a data from plural serial data transfer lines, executing its operation by bringing it to a serial-parallel conversion, and outputting it to plural serial data transfer lines. CONSTITUTION:Input data IN1-IN6 are inputted simultaneously by a serial transfer to six serial-parallel converting circuits 11-1-11-6, respectively, from plural serial data transfer lines 101-106. The serial-parallel converting circuits 11-1-11-6 convert said sata to parallel data, respectively, and input them to an arithmetic circuit 13. The parallel data inputted to the arithmetic circuit 13 executes a prescribed operation, receiving a control by an arithmetic control signal from a controlling circuit 16. The parallel data of a result of operation outputted from the arithmetic circuit 13 is converted to a serial data and outputted through output lines 141-144.

Description

Detailed Description of the Invention The present invention relates to a signal processing processor LSI, particularly a signal processing processor LSI that inputs serial data, performs predetermined calculations under the control of a built-in program, and outputs the results as serial data. Regarding.

The conventional signal processing processor LSI of this type is LSI
In order to minimize the number of pins, the input/output and arithmetic processing capacity for serial input data input via parallel data transfer lines, that is, multiple pieces of serial data, are generally extremely low, and the number of take input/output lines is extremely low. They are often common, and it is not uncommon for the number of input lines and output lines to be limited to one each. For this reason, processing of so-called baseband signals obtained through radar, sonar, etc. and related FFT (F-ast Fo...
When inputting a large number of serial data including various parameters such as amplitude, phase, time, and frequency, such as during processing (transform), and performing arithmetic processing on the data, the input and arithmetic processing edge data must be divided into multiple times. Therefore, there is a drawback that the input/output data transfer time and the time required for arithmetic processing become extremely long.

An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a processing processor LSI having a built-in control block in advance, which inputs serial input data, performs predetermined arithmetic processing on the data, and outputs it as serial output data. Serial input data is input through multiple serial data transfer lines equal to the number of serial input data, this serial-to-parallel conversion is performed, and the results of arithmetic processing under the control of the built-in program are converted from parallel to serial. The present invention is configured to generate multiple pieces of serial output data and output them to a plurality of serial data transfer lines equal to the number of serial output data, thereby greatly reducing the input/output data transfer time and the time required for arithmetic processing. An object of the present invention is to provide a signal processing processor LSI capable of processing signals.

The LSI of the present invention is a signal processing processor LSI that inputs a plurality of serial data having a code sequence of a predetermined number of bits, performs predetermined arithmetic processing under the control of a pre-built-in program, and outputs the data. It receives multiple serial input data that are input simultaneously through multiple serial data transfer lines one after another, converts them into parallel data, performs predetermined calculations under the control of the built-in program, and then reproduces the results obtained. It is configured to convert into serial output data of a predetermined number of bits and pieces corresponding to the content of the predetermined operation, and to output these through a plurality of serial data transfer lines equal to the number of pieces of output data. It is configured with a circuit.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The signal processing processor LSII shown in FIG.
1-4.11-5 and 11-6, input double buffer memory 12-1.12-2.12-3.12-4.1
2-5 and 12-6. Arithmetic circuit 13. Output double buffer memory 14-1.14-2.14-3 and 14-
4. Noku parallel serial conversion circuit 15-1.15-2.
15-3 and 15-4. It is configured to include a control circuit 16 and a program memory 17.

A plurality of serial data transfer lines, in this example, six serial data transfer lines 101゜102.10
3, 104, 105 and 106 through six serial input data IN1 of n-bit configuration.

IN2. IN3. IN 4. IN s and I
When Na performs serial transfer, six serial/parallel converter circuits 11-11...11-6 are connected at the same time.
is input. Serial-parallel conversion circuit 11-1.・
...11-6 convert the input serial input data IN, , ...IN6 into parallel data, and these parallel data are output to output lines 111, 112, 113, 114, 115 and 115, respectively. 116
6 input double buffer memories 12-1.
...Sent to 12-6.

Input double buffer memory 12-1. ...12
-6 has two buffer memories to store input parallel data, respectively, and the latest data, -1/, which are successively input to these two buffer memories one after another.

Parallel data is constantly updated and stored, and out of consecutive parallel data, the one stored earlier in time is simultaneously sent to the arithmetic circuit 13 via output lines 121, 122, 123, 124, 125 and 126, respectively. controlled to do so. This type of control is a serial-to-parallel conversion operation received via output lines 161 and 162 under the control of a built-in program of a control circuit 16, which will be described later, which controls the overall operation of each circuit built into the signal processing processor LSII. The control signal is implemented under the control of the input double buffer memory store control signal.

Now, input double buffer memory 12-1.・・・・・・
- The parallel data input from 12-6 to the arithmetic circuit 13 executes a predetermined arithmetic operation while being controlled by an arithmetic control signal received from the control circuit 16 via the output line 163.

The control circuit 16 has a built-in system control program in advance for controlling the operation timing and contents of each circuit and the output double buffer memory built in the signal processing processor LSII, and outputs data under the control of this built-in program. Lines 161°162.164 and 165
It sends out signals for controlling the operation of each circuit, person, and output buffer memory through the control line 171, and reads out specific arithmetic instructions stored in advance in the program memory 17 via the control line 171 and outputs them to the arithmetic circuit 13. It is sent out as an arithmetic control signal via line 163.

In this embodiment, the arithmetic circuit 13 includes an FFT arithmetic circuit, which is stored in the program memory 17 in advance, and the control circuit 1
The FFT operation using the butterfly method is performed according to the FFT operation program command received through the input double buffer memory 12-1.6. . . . This is carried out for the parallel data input from 12-6.

This calculation result is output as parallel data to the output line 141.
, 142, 143, 144, and an output double buffer memory 14-1 having two buffer memories respectively.
．． 14-2. The result of the previous calculation is stored in one of the buffer memories of 14-3 and 14-4, and the result of the calculation is stored in the other buffer memory, and the result of the calculation is input. The calculation results are stored and read in such a way that the result of the previous calculation is output, and the results of two consecutive calculations are always input to one buffer memory and output from the other buffer memory. . Buffer memory like Jin 14-1.・・・・・・
・The operation of 14-4 is from the control circuit 16 to the output line 164.
The execution is executed under the control of a calculation result write/read control signal received via the control signal.

In this embodiment, the parallel data of the calculation result output from the calculation circuit 13 is transmitted through four output lines 141 and 14.
2, 143 and 144, but this is because the calculation content in the calculation circuit 13 is aimed at FFT calculation processing using the butterfly calculation method.
In general, the number of output lines can be arbitrarily set depending on the content of the operation of the arithmetic circuit 13 and the number of bits forming the resulting data.

Parallel serial conversion circuit 15-1.15-2.15-
3 and 15-4 sequentially read the operation results stored in the two buffer memories of output double buffer memories 14-1.14-2.14-3 and 14-4, starting from the earliest in time. The parallel-to-serial conversion is performed under the control of a parallel-to-serial conversion control signal received from the control circuit 16 via the output line 165. Preset number of bits, in this example, n-bit serial data 0U
T1°OUT 2 , OUT a and 0UT4, and output data transfer lines 1501 . ．． 1502
．． Output via 1503 and 1504.

FIG. 2 is a data input/output/arithmetic processing timing chart showing the timing of data input/output and arithmetic processing in the embodiment of FIG.

Six pieces of serial input data INI, INK, INK, IN4 . IN5 and INs
are the serial data transfer line 1 shown in FIG.
It is assumed that the time axis is inputted as serial data via 11°, 112, . . . , 116 at time T1 above. These input data are the first input data group of a serial input data series that is input continuously, and as time t passes, the i+1th, f+2th, and
The i-th input data group is input one after another until reaching the i+M-th (not shown), and the i-th input data group is inputted before the i-th input data group.
Input data group from -1st to 5th -M' (
(not shown) shall input the same information. Here, M and Ml are positive integers determined depending on the content of data to be processed.

In FIG. 2, for example, serial input data group 1 is
As shown by the dotted arrow, the above-described FFT calculation process is executed in the calculation circuit 13 at time T2. This time T
2, while the serial input data group i is undergoing FPT calculation processing, the serial input data group i+l is processed by the serial-to-parallel conversion circuits 11-1, 11-2, .
・・・・・・After being converted into parallel data in 11-6, input double puffer memory 12-1.12
-2. . . . Out of the two buffer memories of 12-6, the input data group i is stored in the other buffer memory that does not store the input data group i.

Also, at time T2, the output double puffer memory 1
4-1.14-2.14-3 and 14-4 have serial input data group i-1 immediately before the serial input data group 1 already stored in one of the two buffer memories. The corresponding serial output data group (i-1) is read out, and this output data group (i-1)
The four pieces of parallel data forming the . '4, then the serial data transfer line 1501,
1502 , 1503 and 1504 output input data groups i+1 , i+2 , . . . i+
For M and 1ci-1, i-2, ...L-M', input/output and FFT are performed at exactly the same input/output/processing timing.
For example, when input data group iK is input at time T1, it undergoes arithmetic processing at time T2 when serial input data group i+1, which is delayed by one time, is input, and then this output data It is controlled to output as the serial output data group (i) at time T3 when another delayed input data group i+2 is input, and at time TxlC, the serial input data 2 before the serial input data group i is output. data i −
A serial output data group (i-2) for 2 is output.

In this way, all the serial input data groups are processed by the signal processing processor LSI 1, which performs serial-to-parallel conversion of the data, then executes a predetermined operation, and then performs parallel conversion on the result again and outputs the data. It is possible to convert multiple pieces of data input via multiple serial data transfer lines into multiple pieces of serial output data under the control of a built-in program, and output the data via multiple serial data transfer lines. It becomes possible.

The present invention provides a conventional signal processing processor that performs predetermined operations on input serial input data under the control of a built-in program. This is often done via a serial data transfer line, whereas multiple pieces of serial input data are received at the same time, each of these is converted into parallel data, a predetermined calculation is performed, and the calculation result is transferred to multiple pieces of serial data again. The basic feature is that it consists of a serial data signal processing processor LSI with a built-in circuit that converts it into a signal and outputs it, thereby reducing the time required for serial data input/output transfer and calculation. Various modifications of the embodiment shown in FIG. 1 are also conceivable.

For example, in the embodiment shown in FIG. 1, the number of serial input data received at the same time is six, and therefore there are six serial-to-parallel conversion circuits and six input double buffer memories, but this is based on the content of the data to be input. It is clear that it would be possible to implement the same method even if the number is 6 or less or more than 6 specified in advance corresponding to 01.
It is obvious that it would be possible to implement the same method using a plurality of buffer memories corresponding to the types of processing, the contents of calculations to be performed, etc.

In addition, in this embodiment, the arithmetic circuit 13 is designed to handle FFT arithmetic processing using the butterfly FFT arithmetic method, and correspondingly, the arithmetic circuit 13 is configured with four output double buffer memories and four parallel-to-serial converter circuits. However, it is clear that the number of output double buffer memories and parallel-to-serial conversion circuits may be set arbitrarily depending on the content of the calculation.

Furthermore, it is obvious that the control circuit 16 and the program memory 17 could easily be constructed into a functionally and structurally integrated configuration, and all of the above defeats the purpose of the present invention. This can be easily carried out without having to do anything.

As explained above, according to the present invention, in a signal processing processor LSI that inputs serial input data, performs predetermined calculations on the data under the control of a built-in program, and outputs the data, a plurality of pieces of serial input data are While simultaneously receiving data through multiple serial data transfer lines equal to the number of input data, these input data are converted from serial to parallel, stored in a buffer memory, and the built-in program is operated using this parallel data. Parallel data obtained by executing a predetermined operation under control is stored in a buffer memory, and then converted from parallel to serial to create multiple pieces of serial output data, and multiple pieces of serial data equal to the number of output data pieces are By providing a means for simultaneous output via a transfer line, it is possible to realize a signal processing processor LSI that can significantly reduce the time required for data input/output transfer and arithmetic processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a data input/output/arithmetic processing timing chart in the embodiment of FIG. 1... Signal processing processor LSI, 11-1
゜...11-6...Parallel-serial conversion circuit, 12-1...12-6...
Input card double sofa memo 1c13... Arithmetic circuit, 14-1.・・・・・・14-4・・・・・・Output Double Bad 7 Amemo IJ%15-1. ...15
-4...Parallel-serial conversion circuit, 16...
...Control circuit, 17...Program memory. one

Claims (1)

[Claims] Transfer of multiple pieces of serial data in a signal processing processor LSI that inputs multiple pieces of serial data having a code sequence with a prespecified number of bits, performs predetermined arithmetic processing under the control of a pre-installed program, and outputs the data. It receives multiple serial input data that are input simultaneously through each line one after another, converts them into parallel data, performs a predetermined operation under the control of a built-in program, and then returns the obtained result to the above-mentioned predetermined operation. A signal characterized in that it is configured to convert into serial output data with a predetermined number of bits corresponding to the content and to output these data via a plurality of serial data transfer lines equal to the number of said output data. Processor LSI for processing.