JPS6145370A - Buffer memory device of data processor - Google Patents

Abstract

PURPOSE:To omit a transfer of data between buffer memories and to shorten a data processing time by reading a pair of the 1st processed data out of the corresponding buffer memory in the subsequent frame periods and then performing the 2nd processing. CONSTITUTION:A buffer memory device contains three buffer memories 1-3 between a processing circuit 4 for the 1st processing A and a processing circuit 5 for the 2nd processing B. The processing time of the circuit 4 is synchronous with that of the circuit 5. The picture data of each frame undergoes repetitively the processing A, storage to memories 1-3, read-out of memories 1-3 and the processing B. The picture data of a certain frame stored in either one of memories 1-3 after the processing A is through by the circuit 4 is read directly out of the memories 1-3 in the next period and its following period and given to the circuit 5 to receive the processing B.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention provides a method for temporarily storing processed data between each process when multiple processes with different contents are sequentially performed on input data. The present invention relates to a buffer memory device used for storing data.

[Conventional technology]

Conventionally, the following methods have been used to mechanically recognize patterns of images, sounds, etc. First, input data such as images or audio is divided into predetermined unit times (referred to as frames), and a predetermined analysis process (referred to as process A) is performed on the data for each frame. Then, predetermined comparative analysis processing (referred to as processing B) is performed between adjacent frames on the data that has undergone processing A. By the way, in order to perform data processing using this method within a limited time, it is necessary to perform processing A for a frame and processing B for another frame that has already been processed A in parallel. Conventionally, buffer memories B1 to B3 have been provided between the circuit 4 for performing processing A and the circuit 50 for performing processing B, as shown in FIG. 3, for example.

, Memories B1 to B3 are each for storing data for one frame. The memo IJB 1 exclusively plays the role of taking in and storing the processed data outputted from the circuit 4.

Further, the memo IJ B 2 and B3 exclusively play the role of providing stored data to the circuit 5 in response to a read request from the circuit 5.

From the circuit 4, data (for example, image data) for each frame that has been processed A is sequentially provided to the memory B1. Suppose that the circuit 4 is performing process A on the image data of frame (t) at the time when the image data of the frame (t-1), which is one frame before the frame (1), is stored in the memory B2. The memory B3 stores image data of a frame (t-2) two frames before the frame (1). The circuit 5 reads the image data of the frames (t-1) and (t-2) from the memories IJ B 2 and B3, respectively, and executes the process B in parallel with the process A in the circuit 4. The image data of frame (1) will be saved in the memo U when processing A is completed.
B 1 and stored in the memo IJ B 1. When both processing A and processing B are completed, the image data of frame (t-1) stored in memory B2 is transferred to memo IJB3, and the image data of frame (1) stored in memory B1 is transferred to memo IJB3. Transferred to IJ B 2. Thereafter, the image data of the next frame (t+1) is given to the circuit 4, and the image data of the next frame (t+H) is processed A and the frames in the memories B2 and B3 (
1) and (t-1) processing B on the image data are executed in parallel in the same manner as above.

Thereafter, the same process is repeated one after another.

[Problem that the invention seeks to solve]

However, in the above case, the processor circuit 4 and the processor 8
In addition to the original processing time by circuit 5, buffer memory IJ
Time is required to transfer data between B1 and B3. Therefore, there is a problem in that the overall data processing time becomes long, resulting in a decrease in processing efficiency.

This invention was made in view of the above points.

The present invention aims to provide a buffer memory device that can process data in a short time by eliminating data transfer time.

[Means for solving problems]

A buffer memory device according to the present invention includes at least three sets of buffer memories for storing a first processed set of data (data for one frame) for each set (for each frame); Write control means for specifying a buffer memory into which one set of processed data is to be written, and sequentially switching the buffer memory to be written next to another memory each time writing of this one set of data is completed. It is equipped with. Furthermore, read memory selection means is provided, and the read memory selection means selects the remaining buffer memories excluding one buffer memory which is in a writing state under the control of the write memory control means from among all the buffer memories. and supplies the read data for second processing. The selection operation of the read memory selection means is performed in synchronization with the switching control of the write memory control means.

[Effect]

The buffer memory into which the first processed set of data (for one frame) is to be written is sequentially switched under the control of the write memory control means.

On the other hand, the buffer memory used for the second process is
The read memory selection means selects a memory other than the buffer memory in the write state in synchronization with the switching control of the write memory control means.

Therefore, when the buffer memory in the write state is switched, the remaining buffer memories used for the second process are also switched in synchronization with this.

A first processed set of data (for one frame) written to a buffer memory in a frame period of Ru. Therefore, data is not transferred between buffer memories at all, eliminating the need for time for data transfer and shortening the overall processing time.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

As shown in FIG. 1, this buffer memory device has a first
Three buffer memories 1 to 3 are provided between the processing circuit 4 that performs the second processing A and the processing circuit 50 that performs the second processing B. The processing circuits 4 and 5 are designated by the same reference numerals in FIG. 3 based on input data (image or audio data, etc., hereinafter referred to as image data).
The processing time of the processing circuit 4 and the processing time of the processing circuit 5 are synchronized.

From the processing circuit 4, the image data that has been processed A for each frame is sequentially given to each of the data input units of the memories 1 to 3. Note that from the processing circuit 4, an AND circuit 8
Writable input W of each of memories 1-3 via ~10
A write command signal is given to E. This write command signal is sent to the processing circuit 4 for the input image data.
is in PA1'' while processing A, and the processing circuit 4
This command instructs that the processed A data sequentially output from the memory 1 to 3 should be written to one of the memories 1 to 3.

The other input of the AND circuits 8 to 10 is connected to a decoder 7.
The signal of each output line of is given separately. Decoder 7
inputs the output signal of the ternary counter 6, decodes the count value, and calculates the count values rOJ', rlJ, r2J
In other words, when the count value is "2", the count value is "1#" on the output line connected to the AND circuit 8.
0”, the output line connected to the AND circuit 9,
When the count value is "1", a signal "1"' is generated on the output line connected to the AND circuit 10, respectively.

Therefore, when the count value is "2", the write command signal is applied only to the memory 1 via the AND circuit 8, so that only the memory 1 is in a writable state. Similarly, when the count value is "0", only memory 2
When the count value is "1", only the memory 3 is in a writable state. The ternary counter 6 uses a clock pulse φ as a count signal, and the cycle of the pulse φ is synchronized with the data frame time, and the time required for processing A by the processing circuit 4 and the time required for processing B by the processing circuit 5 falls within this one frame time.

The processed data stored in each of the memories 1 to 3 is provided to the processing circuit 5 via gate circuits 14 to 16, respectively. Note that the circuit 5 sends two systems of read request signals in order to read out the processed data of two adjacent frames to be compared one by one in a time-division manner within one frame time. A and b are output in a time-division manner at a predetermined time-division timing. Both read request signals a and b are applied to selected signal inputs of selectors 11-13. That is, the signal a is given to the "1" input of the selector 11, the "2" input of the selector 12, and the "0" input of the selector 13, respectively; input and the “2” input of the selector 13, respectively.

Each of the selectors 11 to 13 uses the output signal of the counter 6 as a selection signal.

That is, in each selector 11 to 13, the current count value of the counter 6 (any one of rOJ, rlJ, r2J)
Selects and outputs the signal applied to the input corresponding to (any one of the "0" input, "1" input, and "2" input). The signal selected by the selector 11 is transmitted to the gate circuit 1.
4 control input. Further, the signal selected by the selector 12 is given to the control input of the gate circuit 15,
The signal selected by the selector 13 is applied to the control input of the gate circuit 16.

Therefore, when the count value of the counter 6 is "2", the read request code a for the processed A-completed data of the temporally earlier frame of both read request signals is selected only by the selector 12 and output. The other read request signal is selected and output only by the selector 13. At this time, first, the gate circuit 1 is
5 is opened, and the processed data in the memory 2 is given to the processing circuit 5 in response to the signal a. After the predetermined time has elapsed, the gate circuit 16 is opened by a signal S.
The processed data in the memory 3 is given to the circuit 5 in response to the signal.

Similarly, when the count value of the counter 6 is "0", the signal a is selected only by the selector 13, and the signal S is selected only by the selector 11. At this time,
First, the processed data in the memory 3 is given to the circuit 5 in response to the signal a, and then after the predetermined time has elapsed, the processed data in the memory 1 is given to the circuit 5 in response to the signal a.

Similarly, when the count value of the counter 6 is "1", the signal a is selected only by the selector 11 and the signal S is selected only by the selector 12. At this time, first, the processed A data in the memory 1 is given to the circuit 5 in response to the signal a, and then, after the predetermined time has elapsed, the processed A data in the memory 2 is given to the circuit 5 in response to the signal a. It will be done.

In the processing circuit 5, processing B is performed on the two processed data obtained as described above. The data obtained as a result of processing B is output as image pattern recognition processed data.

Next, an example of the operation of this buffer memory device will be explained with reference to FIG.

When processing A in the processing circuit 4 is being performed on the image data of frame (1) consisting of (during period T),
Assume that the count value of the ternary power counter 6 is "2" as shown in FIG. 2(b). At this time, as described above, the write command signal becomes "1" (command content to write), and this signal is applied only to the memory 1 via the AND circuit 8, and as shown in FIG. 1 is writable. Therefore, the image data of frame (1) is processed by A
As soon as the process is completed, the data is sequentially stored in the memory 1.

Also, in this period T, the count value is "2", so
A read request signal a is applied to the gate circuit 15 through the "2" input of the selector 12, and the stored contents of the memory 2 are made readable based on the signal a, as shown in FIG. 2(d). Here, when the count value of the counter 6 was "0" due to the two previous pulses φ (period T-
2) The frame (t-
2) data has been written.

Similarly, in the period T, since the count value is "2", the read request signal S is given to the gate circuit 16 via the "2" input of the selector 13, and the memory 3 is output as shown in FIG. 2(e). The stored contents of can be read out based on the signal. Here, when the count value of the counter 6 is "1" due to the previous pulse φ (period T
-1), the frame (t
-1) data is written.

Note that, as described above, the read request signals a and b are provided in a time-division manner in accordance with a predetermined time-division timing during one frame period. The processing circuit 5 processes frames (
Latch the processed A data of t-2) and (t-1),
Process B is performed based on this.

When the count value of the ternary counter 6 changes to "0" based on the next pulse φ, the processing circuit 4 performs the process A on the newly given image data of the next frame (t+1). This time, for the same reason as mentioned above, memory 2 is in a writable state, so the image data of the frame (t-4-1) that has been processed A is as shown in period T+1 in FIG. Stored in memory 2.

Also, at this time, as shown in period T+1 in FIG. 2, the stored contents of the memories 3 and 1 are read by the processing circuit 5, respectively, based on the signals a and bK, and subjected to processing B.

Here, the image data of the frame (t-1) is stored in the memory 3, and the image data of the frame (1) written in the period T is stored in the memory 1.

Furthermore, when the count value of the ternary counter 6 changes by "1" K based on the next pulse φ, the image data of the next frame (t-4-2) which has been processed A is processed in the same way as above. The image data of the frames (1) and (t+1) stored in the memory 3 are read out and subjected to processing B (see period T+2 in FIG. 2).

Similarly, processing A, storage in memories 1 to 3, reading from memories 1 to 3, and processing B are repeated for each frame of image data.

In this way, the image data of the frame stored in any one of the memories 1 to 3 after completing the process A by the processing circuit 4 is directly stored in the memory 1 in the next period and the next period.
. . . 3, is provided to the processing circuit 5, and subjected to processing B. Therefore, since image data is not transferred between the memories 1 to 3, no time is required for image data transfer, and the overall image data processing time is shortened.

〔Effect of the invention〕

As described above, according to the buffer memory device according to the present invention, the first set of processed data stored in the buffer memory during the period of is directly read out from the buffer memory and supplied for second processing. Therefore, since no time is required for data transfer, the overall data processing time is shortened, making it possible to perform data processing quickly.

[Brief explanation of drawings]

FIG. 1 is an electrical block diagram showing one embodiment of a buffer memory device according to the present invention, FIG. 2 is a timing chart showing an example of the timing of write and read operations of each buffer memory in FIG. 1, and FIG. 1 is an electrical block diagram showing an example of a conventional buffer memory device. 1-3... Buffer memory, 4... Processing circuit that performs processing A, 5... Processing circuit that performs processing B, 6...
Ternary counter, 7...decoder, 8-10...AND circuit, 11-13...selector, 14-16...
gate circuit.

Claims (1)

[Claims] 1. Data that performs a predetermined first process based on one set of input data, and performs a predetermined second process using at least two sets of data that have undergone the first process. A buffer memory device interposed between the first process and the second process in a processing device, the buffer memory device having at least three sets of data for storing each set of data processed by the first process. a buffer memory; a write memory control means for sequentially switching the buffer memory into which the first set of processed data is to be written; and a write memory control means for sequentially switching the buffer memory in which the first set of processed data is to be written; A buffer memory device in a data processing device, comprising: read memory selection means for selecting a buffer memory other than the buffer memory and supplying the read data for the second processing. 2. The write memory control means includes an N-ary counter corresponding to the number N of buffer memories, and specifies a memory to be written into according to the output of the N-ary counter, and the read memory selection means . The buffer memory device in a data processing apparatus according to claim 1, wherein a buffer memory other than the buffer memory in the writing state is selected in accordance with the output of the N-ary counter. 3. The input data is image data for one frame, the first process is an analysis process for the image data for one frame, and the second process is for mutual analysis of the image analysis data for two adjacent frames. A buffer memory device in a data processing device according to claim 1, which is a comparative analysis process.