JPS6237737A - Microprocessor circuit - Google Patents

Abstract

PURPOSE:To reduce the delay time of the longest delay bus and to increase the working speed of a microprocessor circuit, by providing a register between elements having large delay times. CONSTITUTION:The data are transmitted via a data bus consisting of tristate gates 60, 70 and 100, selectors 20, 30, 80, 90, etc. An arithmetic circuit 10 of a microprocessor calculates the data given from a RAM 110 and this arithmetic result is stored in the RAM 110 to undergo the microprocessing. Here registers 40 and 50 are set between the circuit 10 and the RAM 110 and no bus passes continuously through the circuit 10 and the RAM 110 of the element having a large delay time. Thus the delay time of the longest delay bus is reduced and a clock of a high frequency can be used. Then the working speed is increased for a microprocessor circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application Many microprocessors perform operations and transfer data between their component random access memory (RAM) and registers. part(
It can be divided into a part (hereinafter referred to as the human LU) and a part (hereinafter referred to as the CCU) that determines the execution address of the program and generates signals to control each element of the ALU according to the command being executed. can.

The present invention relates to the structure of an ALU of a microprocessor circuit.

Conventional technology In recent years, when configuring an entire system, by using microprocessors as all components, it is possible to reduce the scale of the hardware, simplify the hardware configuration,
Many attempts have been made to increase the flexibility of the system.

An example of a conventional microprocessor circuit will be described below with reference to all the drawings.

FIG. 2 is a complete block diagram of the LU of a conventional microprocessor circuit, and FIG. 3 is a timing chart fc of the microprocessor.

In FIG. 2, 1 is an arithmetic unit having one output signal terminal, one control input signal terminal, and two input signal terminals, and the type of operation is determined by the control input signal. 2 has one output signal terminal, one clock input signal terminal and 1
This register has two input signal terminals, and the input signal is held on the rising edge of the clock input signal and outputted to the output signal terminal. 3 is a selector that has one output signal terminal, one control input signal terminal, and two input signal terminals, and which of the two input signals is selected and output is determined by the control input signal. .

4 has one output signal terminal, one control input signal terminal and 3
The selector has three input signal terminals, and which of the three input signals to select and output is determined by a control input signal. 5 and 6 have one output signal terminal, one control input signal terminal, and one input signal terminal, and the control input determines whether to output the input signal onto the output signal terminal or to set the output signal terminal to high impedance. It is a tri-state gate determined by a signal. 7 has one data output signal terminal, one write input signal terminal, one address input signal terminal, and one data input signal terminal, and the location of the address indicated by the address input signal during the high level period of the write input signal. This RAM stores the data of the data input signal at the input signal terminal, and outputs the data at the address indicated by the address input signal to the data output signal terminal during the period when the input signal is at a low level. As shown in FIG. 2, the first input signal terminal of the arithmetic unit 1 is connected to the output signal terminal of the register 2, and the second input signal terminal of the arithmetic unit 1 is connected to the output signal terminal of the selector 3. The input signal terminal of register 2 is connected to the output signal terminal of selector 4,
The first input signal terminal of the selector 3 is connected to the output signal terminal of the tristate gate 5, and the second input signal terminal of the selector 3 is connected to the output of the element of the CCU outputting the part of the program code being executed. The first input signal terminal of the selector 4 is connected to the output signal terminal of the register 2, the second input signal terminal of the selector 4 is connected to the output signal terminal of the arithmetic unit 1, and the first input signal terminal of the selector 4 is connected to the output signal terminal of the arithmetic unit 1. The third input signal terminal is connected to the output signal terminal of the tri-state gate 6, the input signal terminal of the tri-state gate 5 is connected to the output signal terminal of the register 2, and the data input signal terminal of the RAM 7 is connected to the output signal terminal of the tri-state gate 5. is connected to the output signal terminal, and the input signal terminal of the tristate gate 6 is R.
It is connected to the data output signal terminal of AM7, the output signal terminal of tristate gate 6 is connected to the output signal terminal of tristate gate 6, and the address input signal terminal of RAM7 outputs part and all of the code of the command being executed. The control input signal terminal of each of the above-mentioned elements is connected to the output signal terminal of the CCU element which is outputting all the decoded values of the code of the command being executed. The clock input signal terminal is shown in Figure 3 (a).
The MCK signal is input, and the write input signal terminal of the RAM 7 is connected to the CCU generating a signal obtained by ANDing WE and the decoded value of the code of the command being executed (FIG. 3(c)). Connected to the output signal terminal of the element. FIG. 3(b) shows the valid period of the signal on the output signal terminal of the CCU element which outputs the entire code of the command being executed and the decoded value of the command code.

Regarding the microprocessor configured as above,
Commands that can be realized by this configuration will be explained below.

First, when the ALU of a microprocessor circuit has a dual configuration, four types of main commands can be considered as the microprocessor's main commands related to the ALU. The first command is a command that stores the data obtained by performing all operations on the data in register 2 and the data in RAM 7 in register 2, and the second command is a command that stores the data in register 2 and the code of the command being executed. The third command is a command to store all the data in register 2 in RAM 7, and the fourth command is to store the data in RAM 7 in register 2. This is a command to be stored in 2. The first command is that the selector 4 selects and outputs all the output signals of the arithmetic unit 1, the selector 3 selects and outputs the output signals of the tri-state gate 6, and the tri-state gate 5 selects all the output signals and outputs the high-impedance signal. This is realized when the tristate gate 6 outputs all input signals to the output signal terminal and the write input signal of the RAM 7 is at a low level. In this state, the data in register 2 is input to the first input signal terminal of arithmetic unit 1, and
7 is input to the second input signal terminal of the arithmetic unit 1 via the tristate gate 6 and the selector 3, and the result of the operation on both data is stored in the register 2 via the selector 4. be done. For the second command, the selector 4 selects and outputs the output signal of the arithmetic unit 1, the selector 3 selects and outputs part of the code of the command being executed, and the write input signal of the RAM 7 is at a high level. realized in a certain state. In this state, the data in the register 2 is input to the input signal terminal of the arithmetic unit 1, and part of the command code is input to the second input signal terminal of the arithmetic unit 1 via the selector 3. The result of calculating both data is stored in the register 2 via the selector 4. For the third command, the selector 4 selects and outputs the output signal of the register 2, the tri-state gate 5 outputs all input signals to the output signal terminal, the tri-state gate 6 sets all the output signal terminals to high impedance, and the RAM 7 The signal on the write input signal terminal of
This is achieved when the level becomes high at the timing of we shown in d). In this state, the data in the register 2 is input to the data input signal terminal of the RAM 7 via the tristate gate 6, and the data in the register 2 is stored in the RAM 7 while the write input signal terminal of the RAM 7 is at a high level. be done. The fourth command is selector 4
selects and outputs the output signal of the tri-state gate 6, the tri-state gate 5 makes the output signal terminal high impedance, the tri-state gate 6 outputs the input signal on the output signal terminal, and the write input signal terminal of the RAM 7 is realized when is at low level. In this state, data in the RAM 7 is stored in the register 2 via the tristate gate 6 and selector 4.

The configuration of the above-mentioned microprocessor circuit is explained, for example, in Ohmsha Microcomputer Basic Course "Microcomputer Architecture" (written by Osamu Ishii), pages 33 to 37.

Problems to be Solved by the Invention However, in the above configuration, in the case of the first command, there is a path that passes through two elements with large delay times such as the RAM and the arithmetic unit, so the longest delay bus is The problem was that the delay time became too long, the frequency of the basic clock of the microprocessor could not be increased, and a high-speed microprocessor circuit could not be realized.

In view of the above-mentioned problems, the present invention provides an entire microprocessor circuit in which the delay time of the longest delay bus is small.

Is there no way to solve all the problems above? In order to solve this problem, the microphone [+ grosser circuit] of the present invention has a configuration in which a register is interposed between two elements having a large delay time.

According to the present invention, with the above-described configuration, there is no bus that passes through two or more elements with large delay times in succession, so the delay time of the bus with the longest delay is reduced, thereby reducing the basic clock of the microprocessor circuit. It is possible to increase the frequency and realize a high-speed microprocessor circuit.

Embodiment Hereinafter, a microprocessor circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of an ALU of a microprocessor circuit in an embodiment of the present invention. It shows.

In FIG. 1, 10 has one output signal terminal, one control input signal terminal, and two input signal terminals, and the type of operation is determined by the control input signal, and the operation results of the two input signals are output as the output signal. It is an arithmetic unit that outputs on the terminal, and 2
0 has one output signal terminal, one control input signal terminal and two
30 is a selector that has two input signal terminals and selects all of one input signal determined by a control input signal and outputs it on an output signal terminal; 30 is one output signal terminal, one control input signal terminal; 40.60 is a selector that has two input signal terminals and selects one input signal determined by a control input signal and outputs it on the output signal terminal, and 40.60 has one output signal terminal and one clock input signal terminal. and,
This is a register that has one input signal terminal, holds all input signals according to the rising edge of the clock input signal, and outputs it to the output signal terminal. 60, 70, and 100 have one output signal terminal and one control input signal. It is a tri-state gate having a terminal and one input signal terminal, and a control input signal determines whether to make the output signal terminal high impedance or output the input signal to all output signal terminals, and 8
0.90 is a selector that has one output signal terminal, one control input signal terminal, and all three input signal terminals, and selects all one input signal determined by the control input signal and outputs it on the output signal terminal. 110 has a data output signal terminal, a write input signal terminal, an address input signal terminal, and a data input signal terminal, and when the write input signal is at a low level, all data output signal terminals at the address indicated by the address input signal are output. This is a random access memory (RAM) that outputs a data input signal and writes a data input signal to the address indicated by the address input signal when the write input signal is at the high level.

The first input signal terminal of the computing unit 10 is connected to the output signal terminal of the selector 20, the second input signal terminal of the computing unit 1o is connected to the output signal terminal of the selector 3o, and the selector 2
The first input signal terminal of selector 2o is connected to the output signal terminal of register 40, the second input signal terminal of selector 2o is connected to the output signal terminal of register 60, and the first input signal terminal of selector 3o is connected to the output signal terminal of register 60. 4o, and the second input signal terminal of the selector 30 is connected to the output signal terminal of the register 5o.
The third input signal terminal of the selector 30 is connected to the output signal terminal of an element that is a component of the CCU which is outputting a part of the command code being executed. The input signal terminal is connected to the output signal terminal of the selector 80, the input signal terminal of the register 60 is connected to the output signal terminal of the selector 90, the input signal terminal of the tristate gate 60 is connected to the output signal terminal of the register 40, The tri-state gate 700A output signal terminal is connected to the output signal terminal of the register 6o, the first input signal terminal of the selector 80 is connected to the output signal terminal of the register 40, and the second input signal terminal of the selector 8o is connected to the output signal terminal of the register 6o. The third input signal terminal of selector 8o is connected to the output signal terminal of tristate gate 100, and the first input signal terminal of selector 90 is connected to the output signal terminal of tristate gate 100. The second input signal terminal of the selector 90 is connected to the arithmetic unit 1.
o, the third input signal terminal of the selector 90 is connected to the output signal terminal of the register 60,
The input signal terminal of the tristate gate 10o is RAM1
The data input signal terminal of the RAM 110 is connected to the output signal terminal of the tristate gate 60 and the tristate gate 70, and the data input signal terminal of the RAM 110 is connected to the output signal terminal of the tristate gate 60 and the tristate gate 70. The output signal terminals are connected to each other, and the address input signal terminal of the RAM 110 is connected to the output signal terminal of a component of the CCU that outputs a part of the command code being executed.
The control input signal terminal of each element mentioned above and the input signal terminal of the RAM 110 are connected to the output signal terminal of the element which is a component of the CCU which is outputting the entire command code value (CCU control signal) being executed. It is connected.

Regarding the microprocessor circuit configured as described above, commands that can be realized by the configuration will be described below.

First, when the ALU of a microprocessor circuit has the above-described configuration, six types of main commands of the microprocessor related to the ALU will be considered. The first command is a command for calculating the data in the register 40 and the data in the register 50, storing the calculation result in the register 40, and storing the data in the register 50 in the iRAM 110. The second command is a command to perform an operation on all the data in the register 40 and the data in the register 60, and store the operation result in the all-data register 40, as well as in the all-data register 5Q of the RAM 110. The third command is register 4
This is a command to store the data 'o in the iRAM 110, perform a calculation on all the data in the register 40 and the data in the register 6o, and store the calculation results in all the registers 40. The fourth command is a command for calculating the data in the register 5o and the data in the register 40, and storing the result in the register 6o, as well as storing the data in the register 4o in the iRAM 110. The sixth command is the data in register 5o and register 4.
This is a command to calculate 0 data and store it in the register 60, as well as to store it in the entire data register 40 of the RAM 110. The sixth command is the data 'i' in register 5o.
This is a command to store the data in the RAM 110, perform a calculation on all the data in the register 5o and the data in the register 40, and store the result in the register 50.

The control of the selector, tri-state gate, RAM, etc. for realizing the above-mentioned commands can be explained in the same manner as in the explanation of the conventional example, and will therefore be omitted.

According to this embodiment as described above, the frequency of the basic clock of the microprocessor can be increased by eliminating the path that successively passes through two elements with a large delay time, such as an arithmetic unit or RAM. I can do it. Further, as is clear from the configuration, the microprocessor circuit of this embodiment calculates the data of the register 4o and the data of the register 5o, and the result of the calculation is all the registers 4o or the register 60.
The operation of storing data in the memory (arithmetic operation) and the operation of transferring all data between the register 40, register 60, and RAM 11o (transfer operation) can be executed simultaneously. The number of steps (program execution time) can be reduced. Furthermore, by controlling the selector 20 and the selector 30i, all the data in the register 40 is input to the first input signal terminal of the arithmetic unit 10, and the data in the register 50 is input to the first input signal terminal of the arithmetic unit 10. 1
0 to the second input signal terminal, or input the data of register 5o to the first input signal terminal of arithmetic unit 10 and input the data of register 4o to the second input signal terminal of all arithmetic unit 10. Therefore, when executing all operations for which the commutative law does not hold, the data entered in register 40 and register 5
Is it possible to program efficiently because there is no need to distinguish between data to be put in 0? Can be assembled.

Effects of the Invention As described above, according to the present invention, it is possible to realize a microprocessor circuit that can be efficiently programmed and perform high-speed processing using an extremely simple circuit, and is extremely useful in practice. be.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an ALU in a microprocessor circuit of the present invention, and FIG. 2 is a diagram of an ALU in a conventional microprocessor circuit.
FIG. 3 is a timing chart of the microprocessor. 1.10... Arithmetic unit, 20, 30.80, 9
0. 3.4...Selector, 40,50.2...
...Register, 60, 70, 100, 5, 6...
・Tristate gate, 110.7...Random access memory (RAM), MCK...Basic clock signal of microprocessor, CNTL...
. . . Decode signal of a command being executed by the microprocessor, WC . . . RAM write enable signal, WE . . . Intermediate signal not generated by wc1. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (1)

[Claims] an arithmetic unit A that has a control input signal terminal, an output signal terminal, and an input signal terminal, and that calculates an input signal and outputs it on the output signal terminal by a calculation determined by the control input signal; Two selectors S_2 and S_3 that have an output signal terminal and an input signal terminal and select one input signal according to a control input signal and output it on the output signal terminal.
and two selectors S_0 and S_, which have a control input signal terminal, an output signal terminal, and an input signal terminal, and select one input signal according to the control input signal and output it on the output signal terminal.
1, two registers A_0 and A_1 which have a clock input signal terminal, an output signal terminal, and an input signal terminal, and which hold the input signal and output it to the output signal terminal according to a change or state of the clock input signal, and a control input. two tristate gates G_0 having a signal terminal, an output signal terminal, and an input signal terminal, and in which a control input signal determines whether the output signal terminal is in high impedance or the input signal is output on the output signal terminal; G_1, the output signal terminal of the selector S_0 is connected to the first input signal terminal of the arithmetic unit A, the output signal terminal of the selector S_1 is connected to the second input signal terminal of the arithmetic unit A, The output signal terminal of register A_0 is connected to the first input signal terminal of selector S_0, the output signal terminal of register A_1 is connected to the second input signal terminal of selector S_0, and the output signal terminal of register A_1 is connected to the first input signal terminal of selector S_1. The output signal terminal of register A_0 is connected, the output signal terminal of register A_1 is connected to the second input signal terminal of selector S_1, the output signal terminal of selector S_2 is connected to the input signal terminal of register A_0, and the output signal terminal of register A_1 is connected to the second input signal terminal of register A_1. The output signal terminal of selector S_3 is connected to the input signal terminal, the output signal terminal of register A_0 is connected to the input signal terminal of tristate gate G_0, and the output signal terminal of register A_1 is connected to the input signal terminal of tristate gate G_1. is,
Register A_0 is connected to the first input signal terminal of selector S_2.
The output signal terminal of the arithmetic unit A is connected to the second input signal terminal of the selector S_2, and the output signal terminal of the tristate gate G_0 and the output signal terminal of the tristate gate G_0 are connected to the third input signal terminal of the selector S_2. Gate G_1
The output signal terminal of the tri-state gate G_0 and the output signal terminal of the tri-state gate G_1 are connected to the first input signal terminal of the selector S_3, and the output signal terminal of the tri-state gate G_1 is connected to the second input signal terminal of the selector S_3. Vessel A
A microprocessor circuit characterized in that an output signal terminal of a register A_1 is connected to a third input signal terminal of a selector S_3, and an output signal terminal of a register A_1 is connected to a third input signal terminal of a selector S_3.