JPH05158691A - Microprocessor - Google Patents

Abstract

PURPOSE:To shorten the cycle time required for one cycle and increase the operation frequency by providing two arithmetic units and using them alternately through a switching means. CONSTITUTION:The arithmetic units 65-1, 65-2 consists of arithmetic and logic units(ALU), etc., which perform mathematical arithmetic and logical arithmetic for data. One arithmetic unit 65-1 is connected to data buses 63a and 63b through input gates 73, 74 and also connected to a data bus 63C through an output gate 75. The other arithmetic unit 65-2 is connected to the data buses 63a, 63b through input gates 76 and 77 and also connected to the data bus 63C through an output gate 78. Those gates 73-78 are placed in opening/closing operation through a switching control means to alternately control the input and output of the 1st and 2nd arithmetic units 65-1, 65-2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor which decodes an instruction to perform an arithmetic operation, and more particularly to an arithmetic system thereof.

[0002]

2. Description of the Related Art FIG. 2 is a schematic block diagram of a conventional microprocessor system. In this microprocessor system, from the instruction group stored in the instruction memory 10,
The instruction indicated by the address on the address bus 11 is fetched into the microprocessor 20 through the instruction bus 12, and the processing is executed according to the instruction. The microprocessor 20 is connected to a data memory, an input / output port and the like (not shown) via a data bus 31, a control bus 32 and the like.

FIG. 3 shows the microprocessor 20 shown in FIG.
2 is a schematic functional block diagram of FIG. The microprocessor 20 fetches an instruction from the instruction memory 10 in synchronism with one cycle of the clock signal (this is called a state), decodes the instruction, and controls the operation of the entire microprocessor 21. Have The control unit 21 holds an instruction register 22 holding an instruction fetched from the instruction memory 10 and various control signals S23-1 to S23-4 for decoding the instruction and controlling the operation of the entire processor. It has a decoder 23 for generating An address generator 24 is connected to the decoder 23 via a control line. A register circuit 26 for holding data and an arithmetic unit 27 are connected to the internal data buses 25a to 25c, and the register circuit 26 and the arithmetic unit 27 are connected to the control signals S23-1 to S23-1.
It is controlled by S23-3.

In this type of microprocessor 20, the instruction from the instruction memory 10 fetched into the instruction register 22 via the instruction bus 12 is decoded by the decoder 23, and the various control signals S from the decoder 23 are decoded.
23-1 to S23-4 are output. Address generator 2
In 4, the next address is generated by the control signal S23-4, and the address of the next instruction is supplied to the instruction memory 10 via the address bus 11.

The decoder 23 sends to the register circuit 26 the control signal S23-, the address at which the data to be output to the data bus 25a is stored and the address at which the data to be output to the data bus 25b is stored. It is transmitted to the register circuit 26 in the form of 1. Then, the register circuit 26 causes the data bus 25a according to the control signal S23-1.
And output the necessary data to 25b. The data on these data buses 25a and 25b are processed by the arithmetic unit 27.
According to the instruction of the control signal S23-3, an arithmetic operation, a logical operation, or the like is performed, and the operation result is output to the data bus 25c. The data on the data bus 25c is
It is written to any address in the register circuit 26 designated by the control signal S23-2.

FIG. 4 shows a series of these operations. FIG. 4 is a diagram for explaining the operation of FIG.
It is composed of three parts, D and E, respectively. Each stage F, D, E corresponds to one cycle of the clock signal.

Stage F is a fetch cycle,
The address is determined by the address generator 24 from the instruction register 22 through the decoder 23, and the address bus 1
It is from outputting an address from 1 to writing an instruction to the instruction register 22 from the instruction memory 10 of FIG. 2 via the instruction bus 12. The stage D is a decode cycle, which is a period until the decoder 23 decodes the instruction of the instruction register 22 and outputs the control signals S23-1 to S23-3. The stage E is an execution cycle, and two data in the register circuit 26 are operated by the operation device 27 according to the control signals S23-1 to S23-3 output from the decoder 23, and the data is written in the register circuit 26 again. Say.

Each of the instructions 1 to 4 requires three stages (3 cycles) F, D, and E, but since each stage F, D, and E for each instruction is performed in parallel, each instruction is apparent. It means that it is executed in the upper 1 cycle.

[0009]

However, in the microprocessor having the above configuration, the stage F of each instruction,
Although D and E are performed in parallel and the operation speed is apparently increased by executing them in one cycle, the stages F and D must be aligned with the stage E having the longest time. Therefore, stages F and D are stage E
However, there is a problem that the cycle time becomes long and the operating frequency becomes low as a result, which is difficult to solve.

The present invention provides a microprocessor which solves the problem of the decrease in operating frequency as a problem of the prior art.

[0011]

In order to solve the above-mentioned problems, the first invention takes out an instruction in synchronization with a cycle which is one cycle of a clock signal, decodes the instruction, and operates the entire microprocessor. A control unit for generating various control signals for controlling the data, an address generator for generating an address of the instruction to be read next based on the control signal, and a data bus connected to a data bus to generate data based on the control signal. A microprocessor having a register circuit for storing data, performing arithmetic processing of data in the previous register circuit, and storing the arithmetic processing result in the register circuit includes the following means.

That is, according to the first aspect of the present invention, the first and second aspects are connected to the data bus through the gate and perform arithmetic processing of data in the register circuit based on the control signal.
And the switching control means for alternately controlling the input and output of the first and second arithmetic devices by opening and closing the gate for each cycle.

In a second invention, the first and second aspects of the first invention are provided.
The arithmetic unit of 1 is constituted by an arithmetic unit having the same function.

[0014]

According to the first aspect of the invention, since the microprocessor is constructed as described above, the switching control means opens and closes the gate every cycle. Then, the first or second
The input and output of the arithmetic unit are alternately performed.
It becomes possible to shorten the cycle time of the stages of the fetch cycle and the decode cycle to an optimum time separately from the execution cycle using the second arithmetic unit.

In the second aspect of the invention, the first and second arithmetic devices are constituted by devices having the same function, so that the control for alternately using them can be simplified. Therefore, the above problem can be solved.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic functional block diagram of a microprocessor showing an embodiment of the present invention. The microprocessor 40 includes an address bus 11 and an instruction bus 12
2 is connected to the instruction memory 10 of FIG. 2 via a control unit 50, and the address bus 11 is connected to an address generator 62. The control unit 50 has a function of fetching an instruction from the instruction memory 10 in synchronization with one cycle of a clock signal, decoding the instruction, and generating various control signals, and an instruction register for temporarily holding the instruction. 51, and a decoder 52 which decodes the instruction and outputs control signals S52-1 to S52-4 for controlling the operation of the entire processor. A flip-flop (hereinafter referred to as FF) 61 that adjusts the timing of the control signal and outputs the control signal S61 is connected to the control signal S52-1. An address generator 62 composed of a program counter or the like is connected to the control signal S52-4, and its output side is connected to the instruction memory 10 of FIG.

The microprocessor 40 has a data bus 6
3a to 63c are provided, a register circuit 64 for holding data is connected to them, and 2 having the same function
Two arithmetic units 65-1 and 65-2 are connected. Each of the arithmetic units 65-1 and 65-2 is composed of an arithmetic logic unit (ALU) or the like that performs an arithmetic operation or a logical operation of data, and one arithmetic unit 65-1 has one input gate 7
The data bus 63a is connected to the data buses 63a and 63b via 3, 74, and the data bus 63c is connected via the output gate 75.
It is connected to the. The other arithmetic unit 65-2 is connected to the data buses 63a and 63b via the input gates 76 and 77, and is connected to the data bus 63c via the output gate 78. These gates 73-78
The switching control means performs opening and closing operations to alternately control the input and output of the first and second arithmetic units 65-1 and 65-2.

The switching control means includes, for example, a 1-bit counter 71 which counts up every cycle and outputs an output permission signal S71, and an inverter 72 which inverts the output permission signal S71 and outputs an inverted output permission signal S72. And an output permission signal S71 from the gate 7
4, 73 and 78 are opened, and the gates 75, 76 and 77 are opened by the inverted output permission signal S72.

Next, the operation will be described. The instruction fetched from the instruction memory 10 of FIG. 2 to the instruction register 51 via the instruction bus 12 is decoded by the decoder 52, and various control signals S52-1 to S52-4 are output. The address generator 62 generates the next address based on the control signal S52-4, and supplies the address of the next instruction to the instruction memory 10 of FIG.

In the register circuit 64, the data bus 63a
And the address of the data to be output to 63b is the control signal S5.
2-2, and outputs the instructed data to the data buses 63a and 63b. If the initial value of the counter 71 is "1", the output enable signal S71 output from the counter 71 opens the input gates 73 and 74 on the side of the arithmetic unit 65-1 and the data buses 63a and 63b.
The above data is input to the arithmetic unit 65-1.

In the next cycle, the address of the register circuit 64 is designated by the control signal S52-2 output from the decoder 52, and the data at the designated address is output to the data buses 63a and 63b. In this cycle, the counter 71 counts up to "0", so that the output enable signal S71 of the counter 71 is inverted by the inverter 72, and
The input gates 76 and 77 on the arithmetic unit 65-2 side are opened,
The data on the data buses 63a and 63b is the arithmetic unit 65.
-2, and the control signal S52-from the decoder 52-
Calculation processing is performed based on 3. At this time, in the previous cycle, the arithmetic operation is completed by the arithmetic unit 65-1, the output gate 75 on the arithmetic unit 65-1 side is opened by the inverted output permission signal S72, and the data after the arithmetic operation is performed from the arithmetic unit 65-1. Is output to the data bus 63c. The write address of the register circuit 64 output from the decoder 52 in the form of the control signal S52-1 is timing-adjusted by the FF 61 to become the control signal (write address) S61, which is stored in the register circuit 64 designated by the control signal 61. , Data bus 6
The data on 3c is written.

Further, in the next cycle, the counter 71
Is counted up to "1", and the arithmetic unit 65-1 is operated by the control signal S71 output from the counter 71.
The input gates 73 and 74 on the side and the output gate 78 on the side of the arithmetic unit 65-2 are opened. Control signal S from decoder 52
According to the address output in the form of 52-2, the data in the register circuit 64 is output to the data buses 63a and 63b and input to the arithmetic unit 65-1 via the gates 73 and 74. At this time, the arithmetic unit 65-2 of the previous cycle
The operation that was being performed at the
8 is output to the data bus 63c and the data on the data bus 63c is transferred to the register circuit 64 based on the control signal (write address) S61 output from the FF 61.
Written in.

A series of these operations is shown in FIG. FIG. 5 is a diagram for explaining the operation of FIG.
And stage D and stage E65-1 or E65-
2 and 2.

The stage F is a fetch cycle, in which the address is determined by the address generator 62 from the instruction register 51, the decoder 52, and the address bus 11.
From the instruction memory 10 of FIG. 2 through the instruction bus 12 to writing an instruction in the instruction register 51. Stage D is a decode cycle, which is a period from the decoding of the instruction of the instruction register 51 by the decoder 52 to the output of the control signals S52-1 to S52-3. Stage E65-1 is an execution cycle using the arithmetic unit 65-1, and stage E65-2 is an execution cycle using the arithmetic unit 65-2. The stage E65-1 or E65-2 calculates two data in the register circuit 64 by the arithmetic unit 65-1 or 65-2 based on the control signals S52-1 to S52-3 output from the decoder 52. Then, the operation result is written into the register circuit 64 again.

Each of the instructions 1 to 4 requires 4 stages (4 cycles) to complete, but the arithmetic units 65-1 and 6
By alternately using 5-2 and 5-2, the cycle time of the stages F and D is shortened to the optimum time, and as a result, the time required for one cycle is shortened.

As described above, in this embodiment, the two arithmetic units 65-1 and 65-2 are provided, and the two arithmetic units 65-1 and 65 are provided by the 1-bit counter 71, the inverter 72, and the gates 73 to 78. Since -2 is used alternately, the time required for one cycle can be shortened, and thereby the operating frequency can be improved. In addition, the calculation device 65-
Since 1 and 65-2 are configured by the device having the same function, the control for alternately using them becomes simple.

The present invention is not limited to the above embodiment,
For example, the arithmetic devices 65-1 and 65-2 may be configured with devices having different functions, or three or more arithmetic devices may be provided.
The bit counter 71 may have a different circuit configuration for the switching control means using a flag or the like, or the microprocessor 4
Various modifications are possible, such as adding other functional blocks within 0.

[0028]

As described in detail above, according to the first aspect of the invention, the first and second arithmetic units are provided and they are alternately used by the switching control means.
The cycle time required for the cycle can be shortened, which can be expected to improve the operating frequency.

According to the second aspect of the present invention, the first and second arithmetic units are constituted by the units having the same function, so that the control for alternately using them becomes simple.

[Brief description of drawings]

FIG. 1 is a schematic functional block diagram of a microprocessor according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a conventional microprocessor system.

3 is a schematic functional block diagram of a microprocessor in FIG. 2. FIG.

FIG. 4 is an operation explanatory diagram of FIG. 3;

5 is an operation explanatory diagram of FIG. 1. FIG.

[Explanation of symbols]

 40 microprocessor 50 control unit 51 instruction register 52 decoder 62 address generator 63a, 63b, 63c data bus 64 register circuit 65-1, 65-2 first and second arithmetic unit

Claims (2)

[Claims] 1. A control unit for fetching an instruction in synchronization with one cycle of a clock signal, decoding the instruction, and generating various control signals for controlling the operation of the entire microprocessor; An address generator which generates an address of the instruction to be read next based on a signal, and a register circuit which is connected to a data bus and stores data based on the control signal are provided, and arithmetic processing of data in the register circuit is performed. In a microprocessor having an arithmetic function of performing the arithmetic processing result and storing the arithmetic processing result in the register circuit, the first and second arithmetic circuits are connected to the data bus through a gate and perform arithmetic processing of data in the register circuit based on the control signal. A second arithmetic device, and input / output of the first and second arithmetic devices by opening and closing the gate for each cycle. And switching control means for controlling alternately the microprocessor, characterized in that provided. 2. The microprocessor according to claim 1, wherein the first and second arithmetic units have the same function.