JPS61185789A - Reduction and expansion control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a reduction/enlargement control method used in electronic equipment that handles dot/main pattern data such as characters and graphics.

[Prior art and its problems]

When reducing or enlarging characters, figures, etc. in an IJ box configuration using an arbitrary specified magnification, conventionally, the dot matrix pattern of NXN dots to be converted is divided into two-dimensional small area units of nXn dots. Then, according to a certain algorithm for each divided small area unit, logical operations or 2-bit conversion ROM prepared in advance are performed.
A method was adopted in which dot conversion was performed based on access.

Therefore, conventionally, two-dimensional i! This requires a turn conversion mechanism, which makes the configuration extremely complicated and expensive.

In particular, when trying to provide the image processing mechanism with the function of reducing and enlarging characters and figures in a simple internal computer computer, etc., the conventional reducing and enlarging means described above cannot be used. This method could not be put into practical use due to various inconveniences such as cost and processing speed.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a reduction and enlargement control method that can reduce and enlarge dot pattern data with a simple configuration and at high speed.

[Key points of the invention]

The reduction and enlargement control method according to the present invention uses control information storage means of N bits and M bits in the X direction and Y direction, respectively, for example, an N bit X direction shift register, and M bits, without performing coordinate calculation. The designation information of the dots to be reduced or enlarged is set in each shift register, and based on this information, the compression processing of the target adjacent dots or the dot The configuration is such that an increase process is performed.

That is, to give a specific example, during reduction, the X-direction shift register is used to perform a logical OR operation on adjacent dots to be converted and determine whether or not to use this as an output dot, 1 dot of 9 turns. Instructing information is provided, and this information is circulated within the shift register to repeat selective dot compression processing, thereby performing one-dimensional reduction processing in the X direction. Furthermore, when this reduced X-direction data is expanded onto the memory as an output dot pattern, information is provided to instruct whether or not to update the line address (Y-direction address) of the memory, and the above data is updated according to this information. The output image is expanded into memory and compressed in the Y direction.

Also, when enlarging, the X-direction shift register is provided with information instructing whether or not to increase the number of dots to be converted, and this information is circulated within the shift register to selectively increase the number of dots. The process is repeated to perform one-dimensional enlargement processing in the X direction. Furthermore, when expanding this enlarged X-direction data as an output dot pattern on the memory, it is provided with information instructing whether or not to update the line address (Y-direction address) of the memory, and the above data is updated according to this information. Execute the process of expanding the output image to memory and press Y
Performs direction enlargement processing.

With this, dot pattern data can be reduced and enlarged at an arbitrary magnification with a simple configuration and at high speed.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, reference numeral 11 denotes an image memory in which dot and pattern data such as characters and figures to be subjected to reduction and enlargement conversion processing is stored.

12\'i is an address register that specifies the X-direction address of the image memory 11, and 13 is an address register that specifies the same Y-direction address.

Reference numeral 14 denotes a serial-to-serial conversion circuit that sequentially converts the serial data read out from the image memory 11 in predetermined bit units (for example, 16-bit units) into serial data according to a clock signal (CK) of a constant cycle and outputs the serial data. This is hereinafter referred to as the P-8 conversion circuit.

Reference numeral 15 denotes an X for controlling the decrease or increase of the dot data to be converted that is output from the P-8 conversion circuit 14.
This is an X-direction shift register that stores direction conversion control data (hereinafter referred to as X-direction reduction/enlargement data), and here the X-direction reduction/enlargement data is transferred in bit serial mode according to the clock (CK) and shift signal (SCX). Circular shift control is performed during reading and conversion processing. 16 is the X that is shifted out from the X direction shift register 15.
A conversion circuit that performs processing to decrease or increase the dot data output from the p-s conversion circuit I4 based on directional reduction/enlargement data and various control signals output from a control signal generation circuit to be described later; The specific circuit will be described later with reference to FIG.

Reference numeral 17 denotes a serial to parallel conversion circuit which sequentially inputs the bit serial mode dot data converted by the conversion circuit 16 and outputs it in predetermined bit units (for example, 16 pit units); It is called. 18 is s
This is an image memory that stores data output from the -p conversion circuit 17 after reduction and enlargement conversion. 19 is the above sp
When writing data after reduction and enlargement conversion (X-direction-dimensional data) output from the conversion circuit 17 to the image memory 18, an OR operation is performed to OR-add the existing data at the write position and the above-mentioned converted write data. It is a circuit. 20 is atto 0 that specifies the X-direction address of the image memory 18.
Address register 21 is an address register that specifies the same Y-direction address. 22 is a Y-direction shift register that stores Y-direction conversion control data (hereinafter referred to as X-direction reduction/enlargement data), and the data is set in the bit serial mode similarly to the X-direction shift register 15;
The Y-direction address register 21 is selectively updated according to the contents of the shift-out bit.

23 is a control signal generation circuit that generates various control signals, and a 1 word shift completion signal (16 bit full
), the X direction reduction output from the address register 22 /
Input enlarged data, etc., and store image memories 11 and 18.
Each read/write designation signal (R/W) to, conversion circuit 1
Shift signal to 6 (SCX), enlargement designation signal (EN
L), reduction designation signal (RED), and each count-up signal (CT
A, CTB.

CTY), a shift signal to the Y-direction shift register 22 (
SCY) etc. 24 enables the shift out bit of the Y direction shift register 22 during reduction;
A count amplifier signal (C
The AND route 25 receives the output of the AND dart 24 and the count up (CTY) during expansion output from the control signal generation circuit 23, and sends it to the Y direction address register 21 in the Y direction. ORr supplied as a count-up signal for address update
- It is.

FIG. 2 is a logic circuit block diagram showing a specific example of the circuit configuration of the conversion circuit 16. In the figure, when the X direction reduction/enlargement data shifted out from the X direction shift register 15 is 1", A1 superimposes the corresponding dot data output from the p-s conversion circuit 14 on the immediately preceding dot data. A loop is formed to compress adjacent dots by writing, i.e., performing logical summation, and when the reduced/expanded data is "0", the dot data resulting from the logical summation, that is, the compressed dot data, is sent to the S-P conversion circuit. This is an and dart that controls transmission at 17.

A! A3 is an AND/DART circuit that receives the reduction designation signal (RED) and shift signal (SCX) output from the control signal generation circuit 23, and A3 is an UNP date circuit that receives the expansion designation signal (ENL) and shift signal (SCX). , A4 is an AND gate that receives the output of AND gate A and the inverted output of reduced/enlarged data, and A is an AND date that receives the inverted output of reduced/enlarged data and the output of AND date A. A 1-bit delay circuit 201 latches and delays the dot data shifted out by the P-8 conversion circuit 14, and delays the data in units of one clock period of the clock (CK). 0□ is p-s conversion circuit 1
4 dot data (S-In) shifted out,
and the delay circuit 20 output from the AND date A1.
ORDATE, which receives delayed output data (S-out) of 1 as input data of the delay circuit 201, 0! (and goo) Each output of A2 + A4 is connected to delay circuit 2.
01 load signal and the shift signal (SCi) of the P to S conversion circuit 14. is and dirt A,.

A1. The respective outputs of the shift signal SC of the S-P conversion circuit 17
It is an or gate that is received as o. Reference numeral 202 is a hexadecimal counter for counting shift clocks SCo that are outputted more than ORDATE 03 and for detecting completion of shifting for one word (here, 16 bits).

Here, the operation in one embodiment will be explained. During reduction or enlargement conversion, under the control of the host device and the control signal generation circuit 23, the data to be converted, such as a character pattern, is stored in the image memory 11.
The reduced/enlarged data is stored in the X-direction shift register 15 and the Y-direction shift register 22, respectively.

Furthermore, the read start address of the image memory 11 is set in the address register 12.13, and the write start address of the image memory 18 that stores the converted pattern data is set in the address register 20.21. Thereafter, the image memory 11 is read-out controlled, and the first word of data read from the memory 11 (data of 16 dots in the X direction) is set in the P-8 conversion circuit 14, and the shift signal scl and The reduction or expansion designation signal (RED/ ENL) The conversion process according to K is started. That is, the conversion circuit 16 receives the reduction designation signal (RED) and the shift signal (S) from the control signal generation circuit 23.
When receiving the dot data (S-1n) shifted out from the p-s conversion circuit 14 and the reduced data shifted out from the X-direction shift register 15, the The corresponding input dot data (S-in) is selectively compressed (or-added) and output. A specific example will be explained with reference to FIG. 2. In the reduction mode, "1", which specifies the reduction mode,
In response to the "level reduction designation signal (RED="1°C") and the shift signal (SCX=-), the output of ANDr-)A becomes "1". The output "1" of this AND DART A2 is AND DATE A,,A.

A1. A is brought into the dart open control state, and is supplied as a load signal to the delay circuit 201 via the OR f-)0, and further supplied to the P-8 conversion circuit 14 as a shift signal (SCi).

As a result, the P-8 conversion circuit 14 is shift-controlled, and the shifted out 1-bit dot data (S-
in) is or f-)0. The signal is read into the delay circuit 201 via the clock signal, and its output is awaited until the next clock timing.

At this time, when the reduced data shifted out from the X direction shift register 15 is "0", the AND/DART A1
is closed and no feedback loop is formed in the delay circuit 201, and AND gate A is opened and a shift signal of "1" level (SCo = "1") is opened from the OR dirt o3.
) is output and supplied to the S-P conversion circuit 17. Therefore, when the reduced f-value is "0", the P-8 conversion circuit 14
1 shifted out and stored in the delay circuit 201
Bit dot data is read into the SP conversion circuit 17 as it is after a delay of one clock. That is, when the reduced data is "0", the corresponding dot data is not compressed and is output as is. Further, when the reduced data shifted out from the X direction shift register 15 is °1'', the AND date A1 is opened and the delay circuit 201
The output of is fed back to the delay circuit 201 again.
The dot data is inputted into the P-8 conversion circuit 14 and is overwritten (or-added) with the dot data at the next dot position shifted out from the P-8 conversion circuit 14. At this time, the AND gate A is closed, and the shift signal (SCo) at the r level is not supplied from the ORDART 03 to the S-P conversion circuit 17, so that the delay circuit 2
The dot data output from 01 is sent to the S-P conversion circuit 17.
On the other hand, the delay circuit 201 has two adjacent
The dot data is combined and latched for the next step.

In this manner, when the reduced data is "1", the corresponding dot data is overwritten (logical summation) in the delay circuit 201, thereby compressing the adjacent dot data.

Therefore, the X-direction shift register 15, for example, "XX0
Assuming that the reduced data IIIOIIIOX"J is shifted out, the adjacent dot data for 3 dots in the X direction corresponding to the reduced data "1" are logically summed, and each compressed dot in the X direction of 1 dot is obtained. Output as data.

Selective dot compression processing according to such reduced data is sequentially executed, and one word worth of dot data (here, 16 bits worth) in the X direction is output from the conversion circuit 16, and the dot data is output from the conversion circuit 16.
- When input to the P conversion circuit 17, the conversion circuit 16016
The advance counter 202 outputs a shift completion signal (16bitF
ull) is output, and this signal is sent to the control signal generation circuit 23.
is input. When the control signal generation circuit 23 receives this shift completion signal (16bit Full = -1''), it prohibits the output of the shift signal (SCX), temporarily stops the conversion process in the X direction, and sends the signal to the sp conversion circuit 17. Writing of one word of stored dot data that has been subjected to reduction processing in the X direction and dimension to the image memory 18 is performed. The circuit 19 performs an OR addition with the dot data output from the S-P conversion circuit 17, and then writes it into the image memory 18 according to the address specification of the address registers 20 and 21. Furthermore, upon completion of this writing, the address A count up signal (CTB) is supplied to the register 20, and the X-direction address of the image memory 18 is updated.

Furthermore, each time one word (16 bits) of dot data is shifted out from the p-s conversion circuit 14, a count up signal (CTA) is output from the control signal generation circuit 23 and the X-direction address of the image memory 11 is output. counter 12
When the contents of the image memory 11 and the dot data for 4 frames are read out from the image memory 11, a 1 line end signal is output from the address counter 12, and this signal is supplied to the control signal generating circuit 23. At the same time, it is supplied to the Y-direction address register 13 as a count-up signal. When the control signal generation circuit 23fi receives the Scheline end signal from the address register 12, it sends a shift signal (5CY-"1") to the Y-direction shift register 22. The X direction shift register 22 receives this shift signal (SC
When Y="1") is received, the reduced data in the Y direction is shifted out by 1 bit. The reduced data shifted out from this Y-direction shift register 22 is sent to the Y-direction address register 21 of the image memory 18 via an ANDFF port 24 and an address register 25 as a count up signal (CTC).
given as. At this time, the Y direction shift register 22
When the reduced data shifted out is "0", the AND/DART 24 does not output a valid count-up signal (CTC) of "1" level, and therefore the Y-direction address of the image memory 18 is not updated. Therefore, the compressed dot data for the next line is overwritten (or-added) to the data one line before it on the image memory 18, and compressed in the Y direction.

Furthermore, when the reduced data shifted out from the Y-direction shift register 22 is "1", the AND gate 24
A valid count-up signal of “1” level (CTC
) is output and the Y-direction address of the image memory 18 is updated, and the compressed dot data for the next line is not ORed with the same dont data one line before it, and is transferred to the next line. Write control is performed sequentially to new line positions.

The one-dimensional compression process in the X direction according to the shift-out bit of the X-direction shift register 15 and the same compression process in the Y-direction according to the shift-out bit of the Y-direction shift register 22 are sequentially executed, so that the image memory 11 is Dotno of stored characters, shapes, etc.! The turn data is compressed in the X direction and Y direction with a compression rate according to the bit array contents of each reduced data set in the X direction shift register 15 and Y direction shift register 22, and is stored as a reduced dot image in the image memory. 18
expanded above.

At this time, the reduced data in the X-direction shift register 15 and the Y-direction shift register 22 are each subjected to cyclic shift control.

Next, the enlargement processing effect will be explained. During this enlargement process, the conversion circuit 16 uses the control signal generation circuit 23 to generate an enlargement designation signal (EN) instead of the reduction designation signal (RED) described above.
L), the dots are selectively increased according to each enlarged data shifted out from the X-direction shift register 15 and the Y-direction shift register 22, respectively.

That is, during the enlargement process, the control signal generation circuit 2
3, an enlargement designation signal (ENL) is output in place of the reduction designation signal (RED). As a result, the conversion circuit 16
Then, AND gate A is opened in place of ANDr-)A in synchronization with the shift signal (SCX), and its output is "1".
is supplied as a shift signal (SCo) to the S-P conversion circuit 17 via the OAT 03, and also to the AND/DART A4. Here, X direction shift register 1
When the enlarged data shifted out from 5 is "0", the dot data output from the delay circuit 201 is transferred to the S-P conversion circuit 1 by the shift signal (SCo).
7 is loaded, and Dart A4 opens,
The P-8 conversion circuit 14 is shift-controlled, and the shifted out dot data is input to the delay circuit 201 via the oak port 01. Therefore, when the enlarged data is "0" continuously, no dot increase processing, that is, enlargement processing is performed, and the dot data shifted out by the p-s conversion circuit 14 is delayed by one clock cycle and is then directly converted into the S- It will be read into the P conversion circuit 17. Further, when the enlarged data shifted out from the X direction shift register 15 is "1", AND gate A is closed and P
−8 Shift signal effective for the conversion circuit 14 (SCt = “1
”) is not supplied, and the load signal is not supplied to the KAD1 noise circuit 20, so the contents of the delay circuit 201 are not converted. On the other hand, the shift signal (5Co -"1") are sequentially output.Therefore, the 1-bit dot data shifted out from the P-8 conversion circuit 14 and latched by the delay circuit 201 is read into the S-P conversion circuit 17 again.

In this way, when the enlarged data shifted out from the X direction shift register 15 is "1", the shift control of the P-8 conversion circuit 14 and the reading of the delay circuit 201 are prohibited, and the S-P conversion circuit 17 is shift controlled,
One dot of data stored in the delay circuit 201 is sequentially read into the sp conversion circuit 17 in duplicate, so each time the enlarged data becomes "1", the corresponding dot is increased to two dots. Otherwise, dot enlargement processing in the X direction is performed according to the contents of the enlarged data. Further, dot enlargement processing in the Y direction is selectively performed depending on the contents of the enlarged data shifted out from the Y direction shift register 22.

That is, one word of dot data is stored in the S-P conversion circuit 19, and the conversion circuit 16 outputs a shift completion signal (16b).
When it Full) is output, the control signal generation circuit 23 prohibits the output of the shift signal (SCX), and also outputs the shift signal (SCY) to the Y-direction shift register 22.
) is output. As a result, the Y direction shift register 22
is shifted by 1 bit, and the shifted out 1-bit enlarged data is input to the control signal generation circuit 23.

At this time, if the input enlarged data is ``0'', the dot data enlarged in the After being written to address register 20.18, the address register 20. or address register 2
0°21 is counted up and the next data write address is designated.

Further, when the enlarged data shifted out from the Y-direction shift register 22 is "BI", the address is updated in the same manner as described above, and then under the control of the control signal generation circuit 23,
One line of dot data written in the command, that is, the dot data stored in the S-P conversion circuit 17, is written again on the updated address of the image memory 18, and then the address is updated in the same manner as above. 5 is performed and the next data write address is specified. At this time, when the enlarged data of 41) 1 degree level is outputted by shift control of the Y direction shift register 22 upon completion of the above writing,
The write control for the same data above is executed repeatedly.
Incidentally, when writing data to the image memory 18 at this time, the OR circuit 19 performs the s
The write data stored in the -p conversion circuit 17VC and the data stored in the write position of the memory are OR-added.

The image stored in the image memory 11 is sequentially executed by enlarging the image in the X direction according to the shift-out bit of the X-direction shift register 15 and enlarging the image in the Y-direction according to the shift-out bit of the Y-direction shift register 22. The dot/yarn data of characters, figures, etc. is enlarged dot by dot in the X direction and Y direction with an enlargement magnification according to the bit array contents of each enlarged data set in the X direction shift register 15 and the Y direction shift register 22. The data is increased and expanded on the image memory 18 as enlarged dot/mother turn data.

By using the above-mentioned psychological force reduction/enlargement means, a personal computer or the like can be inexpensively and easily provided with functions for reducing and enlarging characters and figures, and the processing can be executed at high speed. Furthermore, since arbitrary dot image data can be easily reduced or enlarged to a desired aspect ratio, image processing functions can be greatly expanded.

Furthermore, by using the above embodiment for layout display in a document processing mechanism, for example, the layout of the entire page can be output in a form close to the original image.

In the above embodiment, the X direction shift register 15
, and the Y-direction shift register 22 are configured by independent shift registers, but for example, the same RA
M, and the reduced/enlarged data may be read out by addressing.

Further, in the above embodiment, there are an image memory 11 for storing the dolatono-kata turn data to be reduced/enlarged, and an image memory 18 for storing the reduced/enlarged data.
For example, they may be configured with the same bitmap memory, and the data read from the same memory may be
A configuration may also be adopted in which the signal is latched in the -8 conversion circuit 14, converted in the conversion circuit 16, latched in the S-P conversion circuit 17, and written into the memory.

Further, the definition of the reduced/enlarged data (1"/"0") is not limited to the above embodiment, and may have a meaning opposite to that of the embodiment.

In addition, in the above embodiment, when writing the reduced/enlarged dot data to the image memory 18, the data at the write position is OR-added, but other logic such as exclusive OR, AND, etc. Calculations may also be performed.

Further, in the above embodiment, the conversion circuit 16 is provided with a 1-pin latch circuit (delay circuit), but the present invention is not limited to this.
A launch circuit for multiple pins (m bits) is provided, and after latching data for m dots output from the p-s conversion circuit 14 into each pin (m bits), reduction/enlargement processing is performed. Good too.

〔Effect of the invention〕

As described in detail above, according to the reduction and enlargement control method according to the present invention, each control information storage means is provided in the X direction and the Y direction with N bits and M bits, respectively, without performing coordinate calculation. By setting the designation information of the dot to be reduced or enlarged in the control information storage means, and performing the compression process of the target adjacent dots or the process of increasing the number of dots based on this information, dots/dots can be 4' turn data can be reduced and enlarged at high speed with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the structure of an embodiment of the present invention, and FIG. 2 is a circuit block diagram showing the structure of a conversion circuit in the above embodiment. 11, Ill... Image memory, 12, 13゜20
．． 21... Address register, 14...No 4 parallel serial conversion circuit (P-8 conversion circuit), 15"・X direction shift register, 16... Conversion circuit, 17°゛・serial roots 4 parallel conversion Circuit (S-P conversion circuit), 19
... OR circuit, 22 ... Y direction shift register, 2
3...Control signal generation circuit.

Claims (2)

[Claims] (1) A first storage means for storing dot pattern data to be subjected to reduction conversion, and a first storage means for specifying dots to be compressed in the X direction of the dot pattern data to be subjected to reduction conversion.
a reduced dot designating means; a means for reading dot pattern data from the first storage means and extracting it in units of specific dots in a fixed dot arrangement order; an X-direction dot conversion means for compressing dots according to a specification; a second storage means for storing the X-direction dot pattern data reduced by the dot conversion means; a second reduced dot specifying means for specifying dots to be compressed in the Y direction of the dot pattern data; and a Y direction for compressing the dot pattern data targeting lines corresponding to the dots specified by the second reduced dot specifying means. dot conversion means, and expands the dot pattern data compressed by the respective dot conversion means into the second storage means. (2) A first storage means for storing dot pattern data to be subjected to enlargement conversion; and a first storage means for specifying dots to be enlarged in the X direction of the dot pattern data to be enlarged.
an enlarged dot designating means; a means for reading dot pattern data from the first storage means and extracting it in units of specific dots in a fixed dot arrangement order; A dot conversion means in the X direction that increases the number of dots according to a specification, a second storage means for storing the dot pattern data in the X direction increased by the dot conversion means, and a dot expanded in the second storage means. a second enlarged dot specifying means for specifying dots to be enlarged in the Y direction of the pattern data; and a second enlarged dot specifying means for specifying dots to be enlarged in the Y direction of the pattern data;
directional dot conversion means, and expands dot pattern data enlarged by each of the dot conversion means into the second storage means.