JPH03243992A - Window setting circuit - Google Patents

Abstract

PURPOSE:To decrease the number of parts increased with an increase in the number of windows by providing common parts to setting of respective windows. CONSTITUTION:A switching means 2 is switched to the state of writing window setting information and the beginning point and end point information of the window corresponding to an image address is inputted from a CPU and is stored in a memory means 1. The means is then held switched in the state of allowing the reading out of the window setting information and the memory means 1 is accessed by the image address. The window beginning point information is read out by the image address corresponding to the end point of the window. Holding means 51 to 5N provided to each of the windows are inputted with the window beginning point information and hold and output the window setting signals. The means output the window setting release signal when the window end point signal is inputted thereto. The parts to be increased in proportion to the number of the windows are decreased in this way and the compact circuit is obtd.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a window setting circuit for an image processing device.

(Prior Art) In recent years, image processing devices have become popular in various fields including inspection devices.

This image processing is digitally processed. This involves dividing the image into a mesh pattern, assigning a number or address to each divided pixel, and processing it using the address and the image data (binary or multivalued data) indicated by that address. It's something to go on.

By the way, when performing image processing, there are cases where it is desired to extract and process only a specific image area. This specific image area is called a window. To set this window, define the window area, check whether the pixel to be processed is within the window, extract the pixel within the window area, and set it in the window. An example of a conventional window setting method for display will be described with reference to FIG. FIG. 5 shows the window setting circuit.

This circuit includes a latch 20 that holds the start point of the window, a latch 21 that holds the end point of the window, an address comparator 22 that compares the image address with the start point of the window, and an address comparator that compares the image address with the end point of the window. 23, address comparator 2
It is composed of an AND gate 24 that performs the logical product of 2 and 23. To set the window, first, the coordinates of the start point and end point of the window are set in the latches 20 and 21, respectively. When the image address to be processed is input to the address comparators 22 and 23, the comparator 22 compares the start point of the window with the input image address, and outputs a signal if the image address is greater than the start point.
The comparator 23 compares the window end point with the input image address, and outputs a signal if the image address is smaller than the window end point. When the signals from both comparators 22 and 23 are output together, the AND gate 24 outputs a signal indicating that the input image is within the window, and otherwise outputs a signal indicating that the input image is outside the window. Said latch 20.21. A window setting circuit consisting of window comparators 22, 23 and an AND gate 24 is required for each window, and is required for the number of windows set by the image processing apparatus.

(111g to be solved by the invention) In this way, according to the conventional window setting method, as the number of windows increases, the IC (integrated circuit) and comparator IC for setting the start and end points of the window are required in proportion to this number. As a result, the number of parts increases.

The present invention has been made in view of the above problems, and its purpose is to provide a window setting circuit that can reduce the number of components that increase as the number of windows increases by providing common components for each window setting. There is a particular thing.

(Structure of the Invention) (Means for Solving Problems) In order to achieve the above object, the present invention includes a storage means for storing window setting information corresponding to a pixel address, and a storage means for writing the window setting information into the storage means. The apparatus includes a switching means for switching between a state and a state for reading out the written window setting information, and a holding means provided for each window for holding the window setting information read from the storage means.

(Function) In the window setting circuit configured as described above, first, the switching means is switched to a state where window setting information is written, and the starting point and ending point information of the window corresponding to the image address is input from the CPU to the storage means. Switch to a state where you can read the 0th window setting information to be memorized,
The storage means is accessed by the image address. The storage means reads window start point information using an image address corresponding to the address where the window start point is set, and reads window end point information using the image address corresponding to the address where the window end point is set.The holding means inputs the window start point information. It outputs the window setting signal while holding it, and outputs the window setting cancellation signal when the window end point signal is input. This allows the window to remain open while the window setting signal is being output, and the window to be closed by the window setting cancel signal.
The above is a case of setting one window, but next, setting of a plurality of windows will be explained.

The switching means is switched to a state in which window setting information is written, and the start point and end point information of multiple windows corresponding to the image address is input from the CPU and stored in the storage means. The storage means is accessed by the address. Each window start point information is read out from the storage means using the image address corresponding to the address at which the start point of each window is set, and input into the holding means corresponding to each window. Also, each window end point information is read out using the image address corresponding to the address where the end point of each window is set, and similarly inputted into the holding means corresponding to each window.

The holding means corresponding to each window outputs a window setting signal based on window start point information, and outputs a window closing signal based on window end point information.

As is clear from the above, the switching means and storage means may be common to each window setting, and the same number of holding means as the number of windows may be provided.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of the window setting circuit of this embodiment, and FIG. 2 shows an overall block diagram of an image processing system using the circuit of this embodiment.

First, the relationship between the window setting circuit of this embodiment and the image processing system will be explained using FIG. The image processing system includes a CPU board 10 that controls the system, a plurality of image processing boards 111 to lln, a window setting circuit 7, and these 10, 111 to lln,
CPU bus connecting 7 to 12. It is composed of an image bus 13. The CPU bus 12 is connected to the CPU address bus, CPU
It consists of signal lines such as a U data bus and read/write lines. In addition, the image bus 13 is connected to each image processing board 1.
11 to 11n, a pixel address bus, a window bus,
The image processing boards 111-11n, which are composed of an image data bus and the like, perform image processing such as creating pixel addresses.The window setting circuit 7 outputs window setting information according to instructions from the CPU board 10, and uses this window information for image processing. The images are output to the boards 111-11n via the image bus 13.

Next, the window setting circuit 7 will be explained using FIG.

The window setting circuit 7 includes a memory 1 that stores window setting information, a selector 2 that switches the address bus to the memory 1 to either a CPU address or a pixel address bus, and a CPU data bus connected to the data bus of the memory 1. A gated bus buffer 3 connected to the data bus of the memory 1, a gated path buffer 4 connected to the data bus of the memory 1, and flip-flops 51 to 5N connected to the path buffer 4 and provided for each settable window. .

Memory 1 has memory addresses for pixel addresses, and the bit length of the data stored in each address is equal to or greater than the number of windows that can be set, for example 4.
It may be bit or 8 bit. The address bus of the memory (2) is connected to a selector 2 which switches the connection to either the CPU address bus of the CPU bus 12 or the pixel address bus of the image bus 13. The data bus of the memory 1 is connected to a bidirectional gated bus buffer 3 and a gated bus buffer 4, which enable connection with the CPU data bus of the CPU bus 12. When the selector 2 selects the CPU address bus by the select signal, the gate of the pass buffer 3 is opened and the CPU data bus and the data bus of the memory 1 are connected, and the gate of the pass buffer 4 is closed by the action of the inverter 6. The data bus of the memory 1 and the flip-flops 51 to 5N are disconnected. Also,
When a pixel address bus is selected by the select signal, the gate of pass buffer 3 is closed and the gate of pass buffer 4 is opened. Each bit of data stored in the memory 1 is connected to a corresponding flip-flop 51 to 5N.
For example, the l-th bit of data is input to flip-flop 51, and the second bit is input to flip-flop 5.
2, the Nth bit is input to flip-flop 5N. Flip-flops 51 to 5N are D-FFs, and the output ζ is fed back to the input. Therefore, the output Q is inverted at the input rising edge of the clock. Therefore, when the clock is changed from 0 to 1, the output Q becomes 1, and if the clock is set to 0 thereafter, the output Q continues to be 1.

When the clock is set to 1, the output is inverted and becomes 0.

As a result, when the output is 1, the window is open and when the output is 0, the window is closed.The outputs of the flip-flops 51 to 5N become window setting information. In other words, if you set data in memory 1 so that the data of each pixel address that is the start point and end point of the window is 1, when the pixel address of the window start point is accessed to memory 1, the window will be set, and the window end point will be set. The window is closed when the pixel address of is accessed in memory l. The operation of this embodiment configured as described above will be explained using FIGS. 3 and 4.

FIG. 3 is a flowchart showing the procedure for writing window setting information from the CPU into memory 1, and FIG. 4 is a time chart showing the situation in which a window is set and closed based on the window setting information stored in memory 1. be. In FIG. 3, at step 30, selector 2 is first switched so that the address bus and data bus of memory 1 are connected to the CPU side. In step 31, the contents of memory 1 are all cleared to zero using software. In step 32, bit 1 is set in the start and end points of each window. Data representing setting information for each window is written by the CPU at the location indicated by each address in the memory 1. This data consists of a number of bits equal to or greater than the number of windows to be set, with one bit corresponding to each window. Figure 4 shows this situation. In this example, the data consists of 4 pits DO, Di, D2. Bit D3 is input to flip-flop 51, and bit D1
D3 corresponds to flip-flop 54; Further, flip-flop 51 corresponds to window 1, and similarly, flip-flop 54 corresponds to window 4.

For address O, the data is 0000, indicating that no window has a starting point and cannot be opened.

At address 1, the data is 1001, indicating that there are two starting points and that windows 1 and 4 are opened. At address 2, the data is 0100, indicating that window 2 is to be opened, and at address 3, the data is 0001. Since window 4 has already been opened at address l, this data represents the end point and will be closed. In this way, the CPU sets data representing the start and end points of the window for all pixel addresses.

Note that by incorporating the address to which data is written in hardware to be the same as the pixel address, the same address as the pixel address corresponding to the start point and end point will be specified.Next, in step 33, the memory 1 address bus The gates of the selector 2 and the pass buffer 3.4 are switched so that the pixel address bus is set to the pixel address bus and the data bus is connected to the pass buffer 4. This completes the writing of the window setting information to the memory 1 and makes it possible to access the memory 1 using the pixel address. FIG. Data in the memory 1 is read out using the 0 pixel address, which will be explained using FIG. Each bit of this data is input as a clock to the corresponding flip-flop 51 to 5N, and when it first changes from 0 to 1,
That is, when the starting point of the target window is reached, the output Q to the flip-flop 5 corresponding to that window changes to 1. When the input to the flip-flop 5 changes from 0 to 1, that is, when the end point of the window is reached, the output Q to the flip-flop 5 changes to 0. As a result, the output Q to the flip-flop 5 is 1 when the pixel address is within the window, and 0 when it is outside the window. Figure 4 shows this situation.

Window 1, which corresponds to flip Flora 151, has data changed from O to 1 at address 1, so window l
is set and the data changes from 0 to 1 at address 14, so window 1 is closed.

Similarly window 2 is set at address 2 and address 5
If you want to change the data set in the 0th memory 1, which is closed at address 8, set again at address 8, and closed at address 11, clear the data that has already been set to zero, and then set it again at address 11. Reset using the method explained in the figure. In addition, in case the order of the start point and end point of the window is out of order due to a data setting error, etc., input one pulse of clear signal to flip-flops 51 to 5N every time a pixel data line ends to reset the output. I have to.

In this embodiment, one-dimensional image processing has been described for ease of understanding, but two-dimensional image processing can be performed by providing two window setting circuits shown in FIG. Also, set the pixel address and memory address to 1
The correspondence was made on a one-to-one basis, but if very detailed window settings are not required, two-on-one correspondence may be used. The ratio may be set to 4:1, etc.

As is clear from the above explanation, according to this embodiment, the window can be set and closed by changing the data in memory 1 from 0 to 1, so the window area does not become heavy and the setting of l If the data is set so that the window setting and closing signals are not consecutive, it is possible to output the window setting and closing signals to the same flip-flops 51 to 5N any number of times.

〔Effect of the invention〕

As described above, according to the present invention, a compact window setting circuit can be realized because components common to each window setting are provided, and the number of components that increases in proportion to the number of windows is reduced.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a block diagram showing the relationship between the circuit shown in Fig. 1 and the entire image processing system, and Fig. 3 shows the operation of the embodiment. FIG. 4 is a flowchart, FIG. 4 is a timing chart showing the operation of the embodiment, and FIG. 5 is a circuit diagram showing a conventional example. 1-11 memory, 2-m-selector, 3.4-m-bus buffer, 51-5 Nm-flip-flop/6--inverter, 7--window setting circuit. Application agent Patent attorney Suzue Figure 2

Claims (1)

[Claims] a storage means for storing window setting information corresponding to an address of a pixel; a switching means for switching between a state in which window setting information is written in the storage means and a state in which the written window setting information is read; and a window read out from the storage means. A window setting circuit comprising a holding means provided for each window that holds setting information.