JPH01311382A - Graphic processor - Google Patents

Abstract

PURPOSE:To speed up line drawing processing by providing the title processor with a register for holding the ON/OFF of transparency and controlling a write enable signal for an image memory in accordance with the value of the register. CONSTITUTION:A transparency control part 6 outputs a write enable signal, the inverse of WE', in accordance with the ON/OFF of transparency set up in a transparency register 5. When the register 5 is ON, a selector 62 selects and outputs an input A. When drawing data generated from a line pattern shift register 1 are '1', its drawing is executed, and when the drawing data are '0', the write enable signal, the inverse of WE', in the image memory is inhibited. When the register 5 is OFF, the selector 62 always selects a write enable signal, the inverse of WE, obtained from a memory control part 4 and executes drawing operation in accordance with drawing data '0' or '1' generated from a line pattern register 1.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a graphic processing device in the field of graphic processing that has improved line pattern generation during line drawing.

<Conventional Technology> Conventionally, drawing linear figures (lines) such as straight lines, dotted lines, circles, etc. in an image memory has been achieved using software.

In other words, a repeating pattern of lines is stored as a line pattern in a line pattern shift register, and this pattern is sequentially shifted so that when the bit data (drawing data) is "0", "0" is written to the image memory. Draw “
When it is 1”, it is 1′.

Draw.

When performing such a process, the process becomes even more complicated if a transparency operation as described below is added.

When transparency is on, it is necessary to draw straight lines, dotted lines, circles, etc. (especially dotted lines, -dotted chain lines, etc.) so as not to erase the background display of the current display screen, and the drawing data is "1". In this case, this drawing data must be written in the image memory, and the device must be configured so that if the drawing data is "0'°,""0" is not drawn.On the other hand, in the case of transbare range - or off, Drawing data “1′”
°.

“Draw '0°' as is in the image memory.

In this manner, in order to efficiently draw a new figure without erasing the background screen display during a drawing operation, it is necessary to add software that performs transparency processing to the conventional figure processing device.

<Problems to be Solved by the Invention> When transparency processing software is added to drawing processing software, there is a problem in that the entire software configuration becomes complicated and its burden increases.

The problem to be solved by the present invention is to perform transparency processing using hardware instead of software, and aims to provide a graphic processing device that can perform line drawing at high speed and efficiently.

<Means for Solving the Problems> In order to solve the above problems, the present invention provides a register that holds transparency on/off, and controls a write enable signal to the image memory according to the value of this register. The structure is as follows.

That is, a line pattern shift register stores a line pattern to be drawn in an image memory, and a clock pulse corresponding to the number of enlarged images of the line pattern is counted and shifted to the line pattern shift register. A repeat counter that gives tarotsuku and this repeat counter.
In a graphic processing device having a memory control unit that provides the clock pulse to a counter and outputs a write enable signal for the line pattern, a transparency register that holds transparency on/off, and a transparency register that holds transparency on/off; time,
a transparency control unit that outputs the write enable signal when the drawing data of the line pattern is "1", and inhibits the write enable signal when the drawing data of the line pattern is "O"; This is a graphic processing device characterized by the following.

Function> The transparency control section in the graphic processing device of the present invention controls the line and
Drawing data generated from the pattern shift register
0", "1", and when transparency is on, when the drawing data generated from the line pattern shift register is "1", drawing is performed as is, and when the drawing data is "0", At this time, the write enable signal to the image memory is prohibited.

<Embodiment> FIG. 1 shows a block diagram of the configuration of a graphic processing device embodying the present invention.

1 sets the line pattern when drawing lines 1
6 Hint)...A shift register, which stores the shift tally (B
or rrow ), the data is shifted up by one bit, and the shifted out data is added to the least significant bit position. The line pattern is referenced from the topmost bin 1 onwards. 62 is a repeat counter that determines the output period of 1-bit drawing data of line pattern shift register 1, and is composed of a 4-bit down counter. Ru. When the count value reaches "0", a shift tally (Borrow) is sent to the line pattern shift register 1.

3 is a zoom register which is given by the line pattern enlargement coefficient set in line pattern shift register 1 or data bus DB. This expansion factor is sent to repeat counter 2 by load clock LOADCK.

A memory control unit 4 outputs a write enable signal WE to an image memory (not shown) to control data write (read) timing, and outputs a count clock RCCK to a repeat counter 2.

5 is a transbearing range register in which on/off of the transbearing range is set.

6 is a transbearing range control section, gate 61;
It is composed of a selector 62. Gate 61 is line
Drawing data from pattern shift register 1 (“O
", "l") and the write enable signal WE from the memory control unit 4. The selector 62 inputs the output of the gate 61 to the A terminal, the write enable signal WE of the memory control unit 4 to the B@ child, When the transveer range register 5 is on, the A input is selected, and when it is off, the B input is selected.

Now, the operation of the graphic processing apparatus of the present invention configured as described above will be explained using the block diagram of FIG. 1 and the time chart of FIG. 2.

First, the line pattern is stored in line pattern shift register 1, and the enlargement factor (“
2") is set by the data bus DB. At this time, the enlargement coefficient ("2") is also set in the repeat counter 2 by the load clock LOADCK.

The repeat counter 2 receives a signal ((
Clock) RCCK, and when the count value reaches "0," output the shift clock (Borrow) to line pattern shift register 1.6 As a result, line pattern shift register 1 is shifted up by one bit and the shifted out data is added to the least significant bit position of line pattern shift register 1.

At the same time, the shifted out 1-bit drawing data D is given to the image memory side.

In this example, the zoom register 3 is set to the value "2", and the repeat counter 2 is set to the clock RC from the value "2".
While counting down to “1” and “0” by CK,
Between 3 clocks RCCK, drawing data D (Valid
DataH (“1” or “0”) is given to the image memory.

On the other hand, the transbearing range control section 6 outputs a write enable signal W E- by turning on/off the transbearing range set in the transbearing range register 5.
Output.

When the transbearing range register 5 is on, the following operation is performed.

A selector 62 in the transveer range control section 6 selects the A input and outputs it.

When the drawing data from the line pattern shift register 1 is "1", the output of the gate 61 is also active ("L") when the write enable signal WE"L" (Low active) of the memory control unit 4 is set. , ”), and the write enable signal WE-, which is the output of the selector 62, becomes active.

Therefore, the drawing data D (“1°°)” of the line pattern shift register 1 is drawn in the image memory.

If the drawing data from the line pattern shift register 1 is "0", when the write enable signal WE 'L' (low active) of the memory control unit 4 is
The gate 62 becomes inactive and the selector 62 becomes “
H" level is output and the write enable signal WE- is inhibited. Therefore, new drawing data D ("0'°) is not written to the image memory, and the previous data remains in the image memory as it is. .

On the other hand, when the transbearing range register 5 is off, the selector 62 of the transbearing range control part 6 always selects the write enable signal WE from the memory control part 4, so the line pattern shift
The drawing data "0" and "1" in the register are written to the image memory.

In the above example, the drawing data from line pattern shift register 1 was explained in units of 1 bit, but normally this bit data is latched and stored in 1 word (
Processing is performed in units of 16 bits.

In this way, new drawing data can be written to the image memory without erasing data previously written to the image memory when the transber range is on.

<Effects of the Invention> As described above, since the graphic processing device of the present invention solves the transbearing range processing using hardware, the software performs the same steps as in conventional line drawing except for setting the line pattern and enlargement factor. It is good that you can perform the same processing as
The speed of drawing processing can be increased.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of the graphic processing device of the present invention, and FIG.
The figure is a flowchart 1 representing the operation of the apparatus of the present invention. 1...Line pattern shift register, 2...
・Repeat counter, 3...Zoom register, 4
...Memory control unit,

Claims (1)

[Claims] (1) A line pattern shift register that stores a line pattern to be drawn in an image memory, and a clock pulse corresponding to the enlargement factor of the line pattern that is counted and shifted to the line pattern shift register. A repeat counter that provides a clock and a repeat counter that provides a clock.
In a graphic processing device having a memory control unit that applies the clock pulse to a counter and outputs a write enable signal for the line pattern, a transparency register that holds transparency on/off and when transparency is on are provided. ,
and a transparency control unit that outputs the write enable signal when the line pattern drawing data is "1" and inhibits the write enable signal when the line pattern drawing data is "0". A graphic processing device characterized by: