JPS5891491A - Picture information input circuit for picture memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image information input circuit for an image memory used in a graphic display device or the like.

Conventionally, when writing graphical information such as straight lines on a graphic display device, the following methods have been broadly classified.

Specifically, there is a method of generating graphical information corresponding to a desired graphic using software and writing the graphical information in byte units or word units into an image memory, and a method of generating graphical information corresponding to the desired graphic using predetermined graphical information generation. Generated from a vessel,
This method writes the generated graphic information directly into the image memory.

However, in the former method, the graphic information is generated by software, so while it is easy to view the information once written, such as partial erasure, it has the disadvantage that high-speed writing is difficult. On the other hand, in the latter method, the graphic information is generated by hardware, so it can be written at high speed, but on the other hand, it requires complex logical conditions to change the information once written, such as partial erasure, and the information cannot be changed. The disadvantage is that it is extremely difficult.

The present invention has been made in view of the above-mentioned drawbacks, and its purpose is to write image information at high speed and to easily change the image information already written to the image memory. An object of the present invention is to provide an image information input circuit for a memory.

To solve this problem, the present invention provides a gate circuit which inputs image input information and an erase signal and outputs the image input information only when there is no erase signal, and a gate circuit which outputs image information from the gate circuit and image information read from the image memory. is used as a selection input, and a selection circuit is provided which selects the output image information of the gate circuit when inputting the image input information and supplies it to the image information input of the image memory.

Hereinafter, the present invention will be described in detail based on the illustrated embodiments.

The figure is a block diagram showing one embodiment of the present invention. In the figure, a graphical signal generated by a linear generator 1 is supplied to an AND gate 2. AND gate 2 is the other input K
A round erasing signal IR8 for partially or completely erasing the mesa memory is input. This erasure! No. ER8
is used as a K “0#” signal when partially erasing the contents of the image memory, and is used as an expanded “1” signal in other cases. Therefore, in cases other than when erasing the entire image memory, The gate 2 outputs the graphic signal generated from the linear generator 1 as it is, and transmits this graphic signal to an ant game consisting of n pieces 3a to 3a.
Commonly supplied to 3n.

A maximum of 2n types of color instruction information are added to the graphic signal input from the AND gate 2. For example, color instruction signals CO to Cn input to the AND gates 3a to 3n, respectively. If the content is "000...1", the graphic signal input from the AND gate 2 is output as graphic information to be displayed in red.

In this way, the graphic signal to which the color instruction information is added is supplied to the A side selection person cams 1 to 4n of the selector 4.

The selector 4 inputs B selection inputs B1 to lln to the image memory 5.
The graphic information (Ml to Mn) read out from the line generator 1 is inputted, and the linear generator 1
When a graphic signal is input, the A selection input is selected when the graphic signal is being generated, and when the graphic signal is not being generated, the B selection input is selected and the information supplied to each selection input is selected. Output. Figure information (Di to Dn) selected and output by this selector 4 Id image memory 5
is supplied to the image information input of , and written to each address of the memory 5 under the control of the address control circuit 6.

Therefore, the erase signal EJEjl is set as the 11# signal,
When a desired graphic signal is generated from the straight line generator 1, this graphic signal is input to the selector 4 as i-shaped information to which color instruction information is added at the AND gates 31 to 3n. Then, the selector 4 selects and outputs the selected image and supplies it to the image memory 5.

Thereby, the graphic signal generated by the linear generator 1 is directly supplied to the image memo 95, so that high-speed writing of the graphic signal becomes possible.

On the other hand, if the erase signal IR8 is set as a 10# signal and the linear generator 1 generates a graphic signal that is the same as a part of the graphic signal already written in the image memory 5, the outputs of the AND gates 2 and 31 to 3n All the signals are "O" signals, and the two-way selector 4 selects and outputs the output information of the anime games (3a to 3n) only at 9 o'clock when a graphic signal is generated, and when no graphic signal is generated, it selects and outputs the output information from the image memory 5. The read image information is selectively output. As a result, the graphic information already written in the image memory 5 is transferred to the linear generator 1.
Only those corresponding to the graphic signals generated from the above become 'O'. That is, the graphic information already written in the image memory 5 is partially erased.

In this case, if the linear generator 1 constantly generates a graphic signal, all the graphic information stored in the image memory 5 will be erased.

Therefore, partial erasure and full erasure of graphic information can be extremely easily performed by simply appropriately controlling the graphic signal generated from the linear generator 1 while the erase signal ERR is set to the "0# signal."

In addition, since the above embodiment adds color instruction information to the graphic signal and writes it into the image memory,
a to 3n, but in the case of white/black display, these 3a to 3n can be omitted.

As is clear from the above description, according to the present invention, image information can be written at high speed, and changes such as partial deletion of already written image information can be easily performed. Since the circuit in this case is only provided with a gate circuit and a selector, it has a simple configuration and has excellent effects such as being extremely economical.

[Brief explanation of drawings]

FIG. 1 is a pull diagram showing an embodiment of the present invention. 1... Linear generator, 2... And gate, 4...
...Selector, 5'l-...Image memory. Patent applicant: Nippon Musical Instruments Manufacturing Co., Ltd. Agent: Masaki Yamakawa (and one other person)

Claims (1)

[Claims] iii. a gate circuit that receives input information and an erasure signal as input, and outputs image input information only when there is no erasure signal;
A selection circuit which takes the output image information of this gate circuit and the image information read from the image memory as selection inputs, selects the output image information of the gate circuit only when the image input information is input, and supplies it to the image information input of the image memory. An image information input circuit for an image memory, comprising: