JP2661326B2 - Elastic store circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention performs a write / read operation in response to a write / read request generated asynchronously, and immediately executes data when a read request is made. More particularly, the present invention relates to an elastic store circuit suitable for a low power consumption circuit such as a CMOS circuit.

[Prior Art] Conventionally, this kind of elastic store circuit is configured as shown in FIG.

That is, the clock signal CK input via the clock input terminal 1 is input to each of the clock input terminals C and CLK of the D-type flip-flop 4, the read address counter 5, and the write address counter 6. The read control signal RC input from the read control signal input terminal 2 is transmitted to the data terminal D of the D-type flip-flop 4 and the read address counter 5.
The write control signal WC input from the write control signal input terminal 3 is input to the count control terminal CONT of the write address counter 6.

The read address RAD and the write address WAD output from the two address counters 5 and 6 are input to the selection input terminals A and B of the address selector 7, respectively. On the other hand, D
A write enable signal ▼, which is the Q output of the type flip-flop 4, is supplied to the selection control terminal S of the address selector 7. The address selector 7 has a selection control terminal S
When the level of the selection control terminal S is "L", the selection input terminal A, that is, the write address WAD is selected. Then, the selected address is output from the output terminal Y of the address selector 7, and R is set as the RAM address AD.
It is given to an address input terminal ADR of an AM (random access memory) 8.

The clock signal CK is applied to the clock input terminal CLK of this RAM.
A RAM clock signal (memory clock signal) RCK, which is obtained by inverting the clock signal by the inverter 9, is supplied. The read / write control terminal R / of the RAM 8 has a D-type flip-flop 4
Is input.
Further, the data input terminal IN of the RAM 8 is connected to the data input terminal 10
Input data DI from the RAM8 and the data output terminal of RAM8
From OUT, output data DO is output to the data output terminal 11.

FIG. 6 is a timing chart showing the operation of this circuit.

The RAM 8 is normally in a write state, but when the read control signal RC goes high, the D-type flip-flop 4
Latches the "H" level at the next rise of the clock signal CK, so that the write enable signal ▲ rises and the RAM 8 enters the read state. At this time, the read address counter 5 counts up and the read address RAD is updated. When the RAM 8 enters the read state, the address selector 7
Selects the read address RAD, which is given to the RAM 8 as the RAM address AD, so that the output data DO of the corresponding address is read from the RAM 8. This reading is performed according to RAM clock signal RCK.

At the next rising of the clock signal CK, the D-type flip-flop 4 latches the "L" level as the read control signal RC.
Returns to the writing state. When the RAM 8 returns to the write state, the write address WAD is selected by the address selector 7, and this is
As a RAM address AD. As a result, RAM8
The input data DI from the data input terminal 10 is written in the storage area specified by the write address WAD. This writing is also performed according to the RAM clock signal RCK.

When the write control signal WC becomes "H" level, the write address counter 6 counts up at the next rise of the clock signal CK, and the write address WAD is updated.

[Problems to be Solved by the Invention] By the way, in the above-mentioned elastic store circuit,
A read / write request occurs asynchronously, and data must be output immediately in response to the read request. For this reason,
In the conventional circuit, the memory clock signal RCK for operating the memory is set to the same cycle as the clock signal CK,
The RAM 8 is operated in synchronization with a clock signal so that data can be read immediately regardless of a read request. Therefore, the operation frequency of the memory is extremely high,
There is a problem in that excessive writing operation is frequently performed, so that power consumption is wasted.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has an elasticity capable of significantly reducing power consumption while performing an operation that does not hinder any read / write request generated asynchronously. It is intended to provide a store circuit.

[Means for Solving the Problems] An elastic store circuit according to the present invention includes a read address counter that updates and outputs a read address in synchronization with a clock signal based on a read control signal, and the clock based on a write control signal. A write address counter that updates and outputs a write address in synchronization with a signal; and selects a read address output from the read address counter and a write address output from the write address counter in accordance with the read control signal. An address selector that outputs the selected address, a read / write memory that is controlled to a read state or a write state by the read control signal, and inputs an address selected by the address selector, and whose output is specified by the read control signal. Frequency dividing means which is set to the value of Memory clock output means for outputting a memory clock signal for operating the read / write memory when the output of the frequency dividing means is the specific value.

[Operation] According to the present invention, the frequency dividing means performs the frequency dividing operation by the clock signal, and the memory clock output means outputs the memory clock signal when the output value becomes a specific value. That is, since the memory clock signal for putting the read / write memory into the operating state is output at a longer cycle than the clock signal, the operation rate of the read / write memory is limited, and the power consumption of the memory can be largely suppressed. it can.

Further, according to the present invention, when there is a read request, the output of the frequency dividing means is set to the specific value by the read control signal. Data can be immediately read from the read / write memory and output. Therefore, an operation that does not hinder the read / write request can be ensured.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of the elastic store circuit according to the first embodiment of the present invention. The first
In the figure, the same portions as those of the conventional circuit shown in FIG. 5 are denoted by the same reference numerals, and the description of the overlapping portions will be omitted.

The difference between this circuit and the conventional circuit shown in FIG.
The means for generating and outputting the RAM clock signal RCK for driving the RAM 8 is provided. That is, in the circuit of this embodiment, the clock signal
CK is input to the up-counter 21, the output of the up-counter 21 and the clock signal CK are input to the 4-input NOR gate 22, and the output of the NOR gate 22 is used as the RAM clock signal RCK as the clock input terminal of the RAM8. It is supplied to CLK.

Here, assuming that both the write request and the read request are output at intervals of 20 clocks or more, a 3-bit up counter can be used as the up counter 21. That is, the up-counter 21 includes three cascaded D-type flip-flops 27, 28, and 29, an inverter 23 that inverts the read control signal RC, and an inverter 23.
AND gates 24, 25, and 26 for forcibly resetting each of the D-type flip-flops 27 to 29 by the output of the AND gates 31 and EX-O for controlling the upper bit carry timing.
And R (exclusive OR) gates 30 and 32.

The operation of the elastic store circuit according to the present embodiment configured as follows will be described.

 FIG. 2 is a timing chart showing the operation of this circuit.

The RAM 8 is normally in a write state, but when the read control signal RC goes high, the D-type flip-flop 4
Latches the "H" level at the next rise of the clock signal CK, so that the write enable signal ▼ rises and the RAM 8 enters the read state. At this time, the read address counter 5 counts up and the read address RAD is updated.

Further, when the read control signal RC becomes “H” level, the “L” level is supplied to the data terminals D of the D-type flip-flops 27 to 29 via the inverter 23 of the up counter 21 and the AND gates 24 to 26. Are latched by the next clock signal CK, and the output of the up counter 21 is reset to "0". The output of this up counter 21 is the clock signal CK
, And returns to “0” again when it reaches “7”.
The RAM corresponding to the “L” level period of the clock signal CK only during the period when the output of the up counter 21 is “0”
Clock signal RCK is output from NOR gate 22 to RAM 8. Therefore, the RAM clock signal RCK is a pulse signal having a cycle eight times as long as the clock signal CK.

When this RAM clock signal RCK is applied to RAM8, RAM8
Is the read address RAD selected by the address selector 7.
The output data DO is read out from the storage area designated by, and is output to the data output terminal 11.

At the next rising of the clock signal CK, the D-type flip-flop 4 latches the "L" level as the read control signal RC.
Returns to the writing state. When the RAM 8 returns to the write state, the write address WAD is selected by the address selector 7 and is given to the RAM 8 as the RAM address AD. As a result, the data input terminal 10 is stored in the storage area specified by the write address WAD of the RAM 8.
Input data DI is written. This writing also
Each time the output of the up counter 21 becomes “0”, the NOR gate 22
This is performed in accordance with the RAM clock signal RCK output from the CPU.

As described above, according to the circuit of this embodiment, the output period of the RAM clock signal RCK is eight times longer than that of the conventional one, so that the operation rate of the RAM 8 is reduced to 1/8 and the power consumption is also reduced to about 1/8. Will do.

In this embodiment, the write request interval and the read request interval are set to 20 clocks or more, and the cycle of the RAM clock signal RCK is set to 8 clocks. However, the cycle of the RAM clock signal RCK is not limited to this. However, the cycle of the RAM clock signal RCK is preferably set to be equal to or less than 1/2 of the write request interval and the read request interval in order to prevent the occurrence of an address that is not written before and after the read request occurs. .

In the first embodiment, a 3-bit up-counter having a count value of "8" is used as the frequency dividing means. If the count value is a power of 2, the counter is optimized. be able to. Further, in the first embodiment, the up counter is used, but the down counter can be similarly realized.

FIG. 3 is a block diagram of an elastic store circuit according to a second embodiment of the present invention. In FIG. 3, the same portions as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and the description of the overlapping portions will be omitted.

In this embodiment, an 8-bit ring counter 41 is used as the frequency dividing means instead of the 3-bit up counter 21 used in the previous embodiment. Ring counter 41
Are cascaded D-type flip-flops 51 to 58 that perform a latch operation in response to a clock signal CK, and a NOR gate 43 for constructively resetting the D-type flip-flops 51 to 58 in response to a read control signal RC. 49 and an OR gate 50. The output of the ring counter 41 is input to a two-input NOR gate 42 together with the clock signal CK. The output of the NOR gate 42 is the RAM clock signal
It is supplied to RAM8 as RCK.

FIG. 4 is a timing chart showing the operation of this circuit.

As shown in the figure, the output of the last stage of the ring counter 41 goes to the “L” level once every eight clocks.
During the level period and during the “L” level period of the clock signal CK
The RAM clock signal RCK is supplied to the RAM 8.

Also in this embodiment, as in the previous embodiment, the operation rate of the RAM 8 can be suppressed to 1/8, and the power consumption can be reduced.

[Effects of the Invention] As described above, according to the present invention, the memory clock signal for activating the read / write memory is obtained by dividing the frequency of the clock signal. The operation rate is limited, and the power consumption of the memory can be suppressed to a rate corresponding to the frequency division rate.

Further, according to the present invention, the output of the frequency dividing means is set to the specific value by the read control signal. Data can be read and output immediately.

Therefore, according to the present invention, it is possible to greatly reduce the power consumption of the circuit while performing an operation that does not hinder any read / write request generated asynchronously.

[Brief description of the drawings]

FIG. 1 is a block diagram of an elastic store circuit according to a first embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the circuit, and FIG. 3 is an elastic store circuit according to a second embodiment of the present invention. 4 is a timing diagram showing the operation of the circuit of FIG. 3, FIG. 5 is a block diagram of the conventional elastic store circuit, and FIG. 6 shows the operation of the circuit of FIG. It is a timing chart. 1; clock input terminal, 2: read control signal input terminal, 3: write control signal input terminal, 4, 27 to 29, 51 to 58; D flip-flop, 5; read address counter, 6; write address counter , 7; address selector, 8; RAM, 9, 23; inverter, 1
0; data input terminal, 11; data output terminal, 21; up counter, 22, 42 to 49; NOR gate, 24 to 26, 31; AND gate, 3
0,32; EX-OR gate, 41; Ring counter, 50; OR gate

Claims (1)

(57) [Claims] 1. A read address counter for updating and outputting a read address in synchronization with a clock signal based on a read control signal, and a write address for updating and outputting a write address in synchronization with the clock signal based on a write control signal. Address counter, an address selector for selecting and outputting a read address output from the read address counter and a write address output from the write address counter in accordance with the read control signal, and reading by the read control signal. A read / write memory controlled to a state or a write state and inputting an address selected by the address selector; an output of the read / write memory being set to a specific value by the read control signal; and performing a frequency dividing operation by the clock signal. Frequency dividing means, and the read / write memo when the output of the frequency dividing means is the specific value. Elastic store circuit; and a memory clock output means for outputting a memory clock signal to operate the.