JPH01140809A - Cmos type integrated circuit - Google Patents

Abstract

PURPOSE:To remove unnecessary current consumption by supplying a fixed potential to a static circuit and a clock signal which has been frequency-divided into to a dynamic circuit at the time of non-selection. CONSTITUTION:When an integrated circuit where the static circuit 15 and the dynamic circuit 16 are mix-used is in a selection state, a clock control signal 13 is set to '1' level, and the clock signal 11 is selected in an AND circuit and a two inputs/one output selection circuit 18, and supplied to the circuits 15 and 16. Since the signal 13 is set to '0' level when the integrated circuit is in a non-selection state, the fixed potential of '0' level is supplied from the AND circuit to the circuit 15, and the consumption of the circuit 15 comes to the current of DC components or a leak current. At that time, the clock signal which has been 1/n frequency-divided in a 1/n frequency division circuit 12 is supplied to the circuit 18, and data is held in the circuit 16,whereby consumption power comes to 1/n.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a CMO8 type integrated image integrated circuit that performs high-speed clock operation.

(Prior art) Figure 2 shows a conventional general CMO 8-type integrated circuit, roughly illustrated in "Introduction to VLSI System" Baifukan PP 246
~250K It is composed of two types of circuits, a static circuit 1 and a dynamic circuit 2, as shown in FIG. 2, to which the same clock signal is applied from the input 3.

(Problems to be Solved by the Invention) Such a CMO8 type integrated circuit has an electrical characteristic in which the power consumption increases in proportion to the frequency of the clock signal. In addition, in this CMO8 type integrated circuit, if the integrated circuit is not selected in the system,
There are times when the integrated circuit can be in a quiescent state. However, in a configuration in which the clock signal from the input 3 is simply applied to the static circuit 1 and the dynamic circuit 2 as in the conventional example described above, even though the integrated circuit in question can be in a non-selected and quiescent state within the system, Regardless, there is the problem of applying a clock signal and causing unnecessary current consumption.

The object of the present invention is to provide a CMO8 type integrated circuit that can eliminate unnecessary current consumption.

(Means for Solving the Problems) This invention provides a CMO8 type O8 circuit with an lZn frequency divider circuit that divides the input clock signal into '/n, and a clock selection circuit. The circuit is C
MO8 type integrated image integrated circuit, depending on the non-selection, either the input clock signal or the clock signal output from the 1/n frequency dividing circuit is selected and supplied to the dynamic circuit, and the clock signal is supplied to the static circuit. is the input clock signal?
The clock signal is supplied by selecting either the %□l level or the fixed potential of %1 level.

(Function) The CMO8 type integrated circuit configured as described above has the following features:
When the integrated circuit is in the selected state, the input clock signal is supplied as is to the static circuit and the dynamic circuit as before, but when the integrated circuit is in the non-selected state, the clock signal is not supplied to the static circuit. v1ON
The potential is fixed at the novel or first level, so the current consumption in static circuits is only the DC component current or leakage current, and in dynamic circuits
Since the clock signal whose frequency is divided by n is supplied, the dynamic circuit can properly hold data and the current consumption is reduced to '/n.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention, which includes a '/n frequency divider circuit 12 that divides the clock signal from the first input 11 by 1/nK, and a '/n frequency divider circuit 12 that divides the clock signal from the first input 11 by 1/nK. a clock selection circuit 14 connected to the output of the clock selection circuit 14, into which the clock signal from the first input 11 is input, and which is controlled by the clock control signal from the second input 13; It consists of a static circuit 15 and a dynamic circuit 16.

In addition, the clock selection circuit 14 selects whether to supply the clock signal from the first input 11 to the static circuit 15 or to supply a fixed signal at the OI level based on the clock control signal from the second input 13. The AND circuit 17 and the clock control signal select whether to supply the clock signal from the first input 11 to the dynamic circuit 16 or to supply the 1/n frequency-divided clock signal of the output of the '/n frequency divider circuit 12. It is composed of a two-manpower one-output selection circuit 18.

The CMO8 type integrated circuit configured in this way has the following characteristics:
When the integrated circuit is in a selected state in a device that uses all of the integrated circuits, that is, when normal high-speed clock operation is required, the clock control signal of the second input 13 is set to 'k'1' level. By this, the first input 11
The clock signal of the AND circuit 1 of the clock selection circuit 14
7 and 2 are selected by the one-output selection circuit 18 and supplied to the static circuit 15 and the dynamic circuit 16.

Next, when the integrated circuit is in a non-selected state, that is, when a state in which only data is held and no operation is required is required, the second input L3 output control signal is set to the %O level. As a result, the static circuit 15 is not supplied with a clock signal by the AND circuit 17 in the clock selection circuit 14 and has a fixed potential of "0" level, so that the current consumption of the static circuit 15 is a DC component current or a leakage current. Only. In addition, the dynamic circuit 16 includes a two-power one-output selection circuit 18 of the clock selection circuit 14.
As a result, the clock signal whose frequency is divided by l/n of the output of the '/n frequency divider circuit 12 is selected and supplied, so that the dynamic circuit 16 normally retains data and the current consumption is reduced to 1. /n.

Note that the AND circuit 17 of the clock selection circuit 14 is replaced with a NAND circuit, and the static circuit 15 is replaced with a NAND circuit when not selected.
Even with a fixed potential at the I level, the current consumption of the static circuit 15 can be reduced to only a DC component current or a leak current when not selected.

(Effects of the Invention) As detailed above, in the CMO8 type integrated image integrated circuit of the present invention, when not selected, the static circuit is supplied with a fixed potential of the 91〃 level or the 91 level, and Since the dynamic circuit is supplied with a clock signal whose frequency is divided by 1/n, when the integrated circuit is in a non-selected state, the current consumption is reduced to 1 in the dynamic circuit while maintaining data normally. /n, and in the static circuit section, current consumption can be reduced to only a direct current component or leakage current, and unnecessary current consumption can be eliminated.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a CMO8 type O8 circuit according to the present invention, and FIG. 2 is a circuit diagram showing a conventional CMO8 type O8 circuit. 11...first input, 12...'/n frequency divider circuit, 1
3... Second input, 14... Clock selection circuit, 1
5... Static circuit, 16... Dynamic circuit, 17... AND circuit, 18... 2 human power 1 output selection circuit, Figure 1, Figure 2

Claims (1)

[Claims] CM that mixes static circuits and dynamic circuits
In an OS type integrated circuit, (a) a 1/n frequency dividing circuit that divides the input clock signal into 1/n, and (b) a dynamic circuit that divides the input clock signal into 1/n, depending on whether the integrated circuit is selected or not. A clock signal is supplied by selecting one of the clock signals output from the 1/n frequency divider circuit, and the input clock signal or "
1. A CMOS integrated circuit comprising: a clock selection circuit that selects either a 0" level or a 1" level fixed potential to supply a clock signal.