JPH04276386A - Memory circuit - Google Patents

Abstract

PURPOSE:To control the reading and writing of information by plural signals with simple configuration by taking the logic of a first signal to control the reading and writing of the information and a second signal to control the action of a memory circuit and controlling the power supply. CONSTITUTION:When a second signal supplied from a signal line 11 is (1), a (p) channel Transistor(Tr)12 becomes a non-conducting condition. When a first signal supplied from a word line 31 within the time is (1), an (n) channel Tr34 and 37 becomes the conducting condition and a reading action can be performed. When the true value of information to be written in a bit line 32 is impressed from the condition where the information is held, the complementary value is impressed to a bit line 33 and (1) is given to the word line 31 only, a (p) channel Tr40 becomes the non-conducting condition and the writing action can be to suppress the constituent to the minimum limit, a memory circuit to be able to read and write the information with 2 signals can be obtained.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit that controls reading and writing of information using a plurality of signals.

0002

2. Description of the Related Art A typical memory circuit has a structure in which reading and writing of information is controlled only by word line signals. On the other hand, in a configuration in which multiple memory circuits are connected to one word line, it is necessary to control reading and writing of information only to the specified memory circuit, so a second signal is used together with the word line signal. It has become necessary to control reading and writing of information using two signals.

FIG. 3 shows an example of the configuration of a conventional CMOS memory circuit that controls reading and writing of information using two signals. In the figure, reference numeral 31 is a word line that supplies a first signal that controls reading and writing of information;
Reference numeral 3 designates bit lines through which information to be read and written is input and output in a complementary manner. Reference numerals 34 to 37 are n-channel transistors constituting the memory circuit, and reference numerals 38,
39 is a p-channel transistor constituting the memory circuit. Reference numeral 40 is a p-channel transistor that is connected to a power source and constitutes an electrical switch that opens and closes in response to a signal from the word line 31. Note that the n-channel transistor 35 and the p-channel transistor 38, and the n-channel transistor 36 and the p-channel transistor 39 each constitute a CMOS inverter, and mutually input to output.
Outputs are connected to inputs.

The above configuration is a memory circuit in which reading and writing of information is controlled by a signal on the word line 31 (Japanese Patent Laid-Open No. 58
-122693 publication), and further includes two signal lines 51 and 52 that supply a second signal, and two n-channel transistors 53 and 54 that control reading and writing of information by this second signal. are connected between n-channel transistors 34 and 37 and each CMOS inverter.

That is, the first signal supplied from the word line 31 and the second signal supplied from the signal lines 51 and 52 cause the n-channel transistors 34 and 37 and the n-channel transistors 53 and 54 to become conductive. Non-conduction is set, and reading and writing of information is controlled.

[0006]

By the way, in the configuration of a conventional memory circuit that controls reading and writing of information using two signals, in addition to the basic configuration, two signal lines (51, 52 ) and two transistors (53,5
4) was essential. SUMMARY OF THE INVENTION An object of the present invention is to provide a memory circuit that has a simple configuration with a minimum number of components and can control reading and writing of information using two signals.

[0007]

[Means for Solving the Problems] The present invention provides an information read/write terminal to which information to be read and written is input/output, a first control terminal to which a first signal for controlling reading and writing of information is input, and a power supply. A power supply connection terminal, and a first switch means whose conduction/non-conduction is controlled by the first signal and which controls the supply of the power, and the first switch means is configured to hold, read, and hold the information according to the first signal. In a memory circuit that performs writing, a second control terminal to which a second signal for controlling the operation of the memory circuit is input, and a logic between the first signal and the second signal, and the logic is determined. It is characterized by comprising a second switch means that controls conduction/non-conduction of the first switch means based on a signal obtained as a result of the measurement.

[0008]

[Operation] The present invention provides a first
The conduction/non-conduction of the switch means is controlled via the second switch means by a signal which takes the logic of the first signal that controls reading and writing of information and the second signal that controls the operation of the memory circuit. It will be done. Therefore, the first signal and the second
By combining the logic of these signals, it is possible to control power supply and read/write information with a small number of components.

[0009]

Embodiment FIG. 1 is a diagram showing the configuration of a first embodiment of the present invention. In the figure, word line 31, bit lines 32, 3
3. N-channel transistor 34 constituting the memory circuit
, 35, 36, 37 and p-channel transistor 38
, 39, p-channel transistor 4 for controlling power supply
0 is similar to a conventional memory circuit.

The feature of this embodiment is that the number of signal lines 11 for supplying the second signal is one, and the first signal supplied from the word line 31 and the second signal supplied from the signal line 11 are connected to each other. A p-channel transistor 12, which takes logic with the signal , is connected between the word line 31 and the p-channel transistor 40, and its conduction/non-conduction is controlled to control the supply of power to the memory circuit. Note that the connection point between the p-channel transistor 12 and the p-channel transistor 40 is α, and the connection point between the p-channel transistor 40 and the memory circuit (p-channel transistors 38 and 39) is γ.
shall be.

[0011] Hereinafter, with reference to FIG. 1, ■ Information retention, ■
Each operation of reading information, (1) writing information, and (2) prohibiting writing of information will be explained. Note that in this memory circuit, when the p-channel transistor 40 is in a conductive state,
It is assumed that the driving force and other settings of each transistor are set so that the state of the memory circuit cannot be changed externally. This setting can be made, for example, by increasing the driving force of p-channel transistors 38 and 39 and decreasing the driving force of n-channel transistors 34 and 37.

(1) Information retention Information can be retained by applying a low potential (hereinafter referred to as "0") to the word line 31 and the signal line 11. That is,
When the second signal supplied from the signal line 11 is "0", the p-channel transistor 12 becomes conductive, and since the first signal supplied from the word line 31 is "0", the α point is becomes "0", and the p-channel transistor 4
0 also becomes conductive. Therefore, power is supplied to the γ point, and the memory circuit can hold static information.

■ Reading information To read information, first apply a high potential (hereinafter referred to as "1") to the signal line 11 from the state where the information is held, and then apply a high potential (hereinafter referred to as "1") to the word line 3.
This is possible by assigning "1" to 1. That is,
When the second signal supplied from the signal line 11 is "1", the p-channel transistor 12 becomes non-conductive, and the potential at point α becomes "0" within a predetermined time regardless of the potential of the word line 31. ” is maintained, and the state in which power is supplied to the γ point continues. By setting the first signal supplied from the word line 31 to "1" within this time, the n-channel transistors 34 and 37 become conductive, and a read operation similar to that of a normal static memory circuit can be performed. .

[0014] Note that a configuration may also be adopted in which "1" is applied only to the word line 31 in a state where information is held, and power supply to the γ point is cut off when reading the information. At this time, reading is performed while the information is being held dynamically.

[0015] Writing information To write information, from the state where the information is held, apply the true value of the information to be written to the bit line 32, apply its complementary value to the bit line 33, and apply the true value of the information to the word line 31. This is possible by giving "1" to only "1". That is,
The p-channel transistor 40 becomes non-conductive and γ
Since the power supply to the point is cut off, the write operation can be performed at high speed and stably.

■Prohibition of writing of information The operation of prohibiting writing to a designated memory circuit among the plurality of memory circuits connected to one word line 31 is to prohibit writing of information to the memory circuit to be prohibited from writing. This is possible by applying ``1'' to the signal line 11 before applying ``1'' to the word line 31 from a state where information is held during writing. That is, when the second signal supplied from the signal line 11 becomes "1", the p-channel transistor 12 becomes non-conductive, and the potential at point α remains within a predetermined time regardless of the potential of the word line 31. In this case, "0" is maintained, and the state in which power is supplied to the γ point continues. Even if the first signal supplied from the word line 31 becomes "1" in this state, when the p-channel transistor 40 is in a conductive state, the state of the memory circuit cannot be changed externally, so information cannot be written. doesn't happen.

In this embodiment, the signal line 11 is connected to the gate of the p-channel transistor 12, and the word line 31 is connected to the gate of the p-channel transistor 12.
Although the configuration example in which the signal line 11 is connected to the source of the p-channel transistor 12 is shown, the signal line 11 is connected to the source of the p-channel transistor 12.
Even if the word line 31 is connected to the source of the p-channel transistor 12 and the word line 31 is connected to the gate of the p-channel transistor 12, the same operation can be achieved by appropriately controlling each signal.

FIG. 2 is a diagram showing the configuration of a second embodiment of the present invention. The feature of this embodiment is that, in contrast to the configuration of the first embodiment shown in FIG. 1, the p-channel transistor 12 is realized by an n-channel transistor 22. The other configurations are the same as in the first embodiment. In this embodiment, in the first embodiment, by reading the potentials "0" and "1" of the second signal supplied to the signal line 11, similarly, (1) retaining information, (2) reading information, (2) It is possible to explain each operation of writing information and (1) prohibiting writing of information.

Also in this embodiment, the signal line 11 is connected to the source of the n-channel transistor 22, and the word line 31 is connected to the source of the n-channel transistor 22.
Even if the configuration is such that the n-channel transistor 22 is connected to the gate of the n-channel transistor 22, the same operation can be achieved by appropriately controlling each signal. Moreover, in the embodiment shown above, C
Although the description has been given using a MOS circuit format as an example, the present invention can be similarly applied to other circuit formats.

[0020]

Effects of the Invention As explained above, the present invention controls the supply of power by taking the logic between the first signal that controls reading and writing of information and the second signal that controls the operation of the memory circuit. , it is possible to control reading and writing of information using two signals with a small number of components.

[0021] Therefore, when using the same amount of components as in the past, the capacity of the memory device can be increased and the cost per capacity can be significantly reduced. In addition, when a transistor with a large driving force is used as a load element of an inverter that constitutes a memory circuit,
The resistance to soft errors caused by alpha rays, which is a problem when configuring a memory circuit using integrated circuit technology, can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing the configuration of a second embodiment of the present invention.

FIG. 3 is a configuration example of a conventional CMOS memory circuit that controls reading and writing of information using two signals.

[Explanation of symbols]

11 Signal line 12 P channel transistor 22 N channel transistor 31 Word line 32, 33 Bit line 34, 35, 36, 37 N channel transistor 3
8, 39 p-channel transistor 40 p-channel transistor 51, 52 signal line

Claims (1)

[Claims] 1. An information read/write terminal to which information to be read and written is input/output; a first control terminal to which a first signal for controlling reading and writing of information is input; and a power supply connection terminal to supply power; a first switch means whose conduction/non-conduction is controlled by a first signal and which controls supply of the power, and which holds, reads and writes the information according to the first signal; A second control terminal to which a second signal for controlling the operation of the memory circuit is input; a logic is calculated between the first signal and the second signal; 1
and second switch means for controlling conduction/non-conduction of the switch means.