KR100280436B1 - Output buffer for input level having tolerance - Google Patents

Abstract

The present invention relates to an output buffer having an allowable limit for the input level. In the related art, when a pad is connected to an output terminal of an output buffer and writes data larger than this voltage at a 'low' power supply voltage, a substrate of the output buffer is used. When the n-well bias is lower than the potential of the pad, carrier injection from the drain of the P-MOS transistor of the output buffer to the n-well occurs, and a resistance between the pad and the input buffer is prevented. However, there is a problem that latch-up is caused when a large amount of current flows due to a small resistance value.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and the power source of the first P-MOS transistor and the second P-MOS transistor having a gate connected to the pull-up signal input terminal in common A gate of the first N-MOS transistor connected to a voltage, a drain of the first P-MOS transistor connected to a drain and a pad of the first N-MOS transistor through node 1, and a source connected to ground; A drain of a second P-MOS transistor connected to a down signal input terminal and having a gate connected to the node 1 to a substrate bias terminal of the first and second P-MOS transistors in common with the drain of the second N-MOS transistor; And a device formed by connecting the gate and the source of the second N-MOS transistor to the node 1 in common. Air injection reduces the phenomenon, a stable operation by variably changed on the input level, and also has a number of components to be added less low-burden at the time of design effect.

Description

OUTPUT BUFFER FOR INPUT LEVEL HAVING TOLERANCE}

The present invention relates to an output buffer having an allowable limit for the input level, and particularly to an output buffer in which one pad (PAD) is shared with the input buffer, and to a reverse current phenomenon that may occur when the output voltage of the output buffer is low. Problems such as power dissipation, carrier injection, etc. cause an output buffer with an allowable limit on the input level to prevent latch-up in the output buffer. It is about.

FIG. 1 is a circuit diagram illustrating a configuration of an output buffer sharing a pad with a conventional input buffer. As shown in FIG. 1, a gate is connected to a source of a P-MOS transistor PM1 connected to a pull-up signal input terminal DUPb. A gate of the N-MOS transistor NM1 connected to a VCC, a source of which is connected to ground VSS, to a pull-down signal input terminal DDN, and a drain of the P-MOS transistor PM1 is connected to node 1. A power supply voltage Vcc is applied to a drain of the N-MOS transistor NM1, a node 1 connected to a pad 10, and a substrate bias terminal of the P-MOS transistor PM1. The back bias voltage or the ground voltage Vss is applied to the substrate bias terminal of the N-MOS transistor NM1. The operation process of the conventional circuit configured as described above is as follows.

In the read operation, the output buffer 30 has the P-MOS transistor PM1 turned on when the pull-up signal and the pull-down signal are 'low', and the N-MOS transistor NM1 turns off. When the pull-up signal and the pull-down signal are 'high' through the node 1, the power supply voltage VCC is output to the pad 10. In contrast, the P-MOS transistor PM1 is turned off. The N-MOS transistor NM1 is turned on to output the ground voltage VSS to the pad 10 through the node 1, and the input buffer 20 is connected to the write enable bar signal WEb. It does not work by.

In the write operation, when the input buffer 20 is enabled by WEb, write data is input to the input buffer 20 through the pad 10.

As described above, in the related art, as shown in FIG. 1, the pad is connected to the output terminal of the output buffer, and thus, when writing data larger than this voltage at the 'low' power supply voltage, the substrate bias of the output buffer becomes n-well bias. Carrier injection from the drain of the P-MOS transistor of the output buffer to the substrate (n-well) occurs when the potential is smaller than the potential of, and to prevent this, there is a resistance between the pad and the input buffer, but the resistance is small so that the current There was a problem that a lot of flow caused the latch-up.

Accordingly, an object of the present invention is to provide a circuit for changing a substrate bias voltage in accordance with an input level by adding P-MOS and N-MOS transistors. .

1 is a circuit diagram showing a configuration of an output buffer sharing a pad with a conventional input buffer.

2 is a circuit diagram showing the configuration of an embodiment of the present invention.

*** Description of the symbols for the main parts of the drawings ***

10: pad 20: input buffer

30, 40: Output buffers PM1 to PM3: P-MOS transistors

NM1 to NM3: N-MOS transistor

In order to achieve the above object, a configuration of an output buffer having an allowable limit for an input level of the present invention includes a source of a first P-MOS transistor and a second P-MOS transistor having a gate connected to a pull-up signal input terminal. Is connected to a power supply voltage in common, a drain of the first P-MOS transistor is connected to a drain of the first N-MOS transistor through node 1, and a gate of the first N-MOS transistor having a source connected to ground is connected. A substrate of the first and second PMOS transistors in common with a drain of a second N-MOS transistor connected to a pull-down signal input terminal and having a gate connected to the node 1 and a pad; And a gate and a source of the second N-MOS transistor connected to the node 1 in common.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a circuit diagram illustrating an embodiment of the present invention. As shown therein, a source and a second P-MOS of a first P-MOS transistor PM2 having a gate connected to a pull-up signal input terminal DUPb. A source of the transistor PM3 is commonly connected to the power supply voltage VCC, a drain of the first P-MOS transistor PM2 is connected to a drain of the first N-MOS transistor NM2 through node 1, A second P-MOS transistor having a source connected to a ground of the first N-MOS transistor NM2 connected to a pull-down signal input terminal DDN, and a gate connected to the node 1 and the pad 10; The drain of PM3 is connected to the substrate bias terminal of the first and second P-MOS transistors PM2 and PM3 in common with the drain of the second N-MOS transistor NM3. The gate and the source of the transistor NM3 are connected to the node 1 in common. .

Referring to the operation process and the effect of an embodiment according to the present invention configured as described above are as follows.

If this data is larger than the power supply voltage Vcc when writing to the high during the write operation, the second N-MOS transistor NM3 is turned on and the first and second P-MOS transistors PM2 and PM3. ), The substrate bias (n-well bias) becomes V ('high' data)-V _T , and when writing to low, the second P-MOS transistor PM3 is turned on. As a result, the substrate bias becomes the power supply voltage Vcc, thereby reducing carrier injection due to bidirectional bias between the P-MOS transistor PM2 and the substrate.

That is, the carrier injection dependency between the drain of the P-MOS transistor PM2 of the output buffer 40 and the substrate decreases with respect to the input of the input buffer 20, and the tolerance of the input level is set to the output buffer 40. Has had.

When the pull-up signal becomes 'high' during the read operation and the pull-down signal becomes 'high', the first N-MOS transistor NM2 is turned on and the second P-MOS transistor PM3 is turned on. Since the substrate bias of the first and second P-MOS transistors PM2 and PM3 becomes the power supply voltage Vcc, when the pull-up signal and the pull-down signal are input as 'low', the first and second P-MOS transistors PM2 and PM3 are turned on. 1 P-MOS transistor (PM2) is turned is on the substrate bias after I is VCC-V _T is the level.

In this case, carrier injection may occur, but this current value may be negligible since it is insignificant compared to the current value flowing through the first P-MOS transistor PM2.

When the pad 10 reaches the level of the high impedance voltage (hereinafter, referred to as V _OZ ) by the system driver when no read or write operation is performed, the second P-MOS transistor PM3 and the second N-MOS transistor NM3. ) Is turned on so that a small amount of current flows, so that the substrate bias of the first P-MOS transistor PM2 is relatively larger than V _OZ of the pad 10, and the conductance is large. When the drain level of the second P-MOS transistor PM3 is gradually increased to make the drain potential of the second N-MOS transistor NM3 at V _OZ -V _T , the second N-MOS transistor NM3 is no longer present. ) Does not turn on.

As described above, the output buffer having the tolerance for the input level of the present invention is designed to reduce the carrier injection phenomenon occurring in the output buffer, to operate stably by varying the input level, and to have a small number of additional components. There is little effect on city burden.

Claims (1)

The source of the first P-MOS transistor and the source of the second P-MOS transistor having the gate connected to the pull-up signal input terminal are connected to the power supply voltage in common, and the drain of the first P-MOS transistor is connected through the node 1. A second P-connected to a drain and a pad of a first N-MOS transistor, a gate of the first N-MOS transistor having a source connected to ground, connected to a pull-down signal input terminal, and a gate connected to the node 1; The drain of the MOS transistor is connected to the substrate bias terminal of the first and second P-MOS transistors in common with the drain of the second N-MOS transistor, and the gate and the source of the second N-MOS transistor are commonly connected to the node. Output buffer having a tolerance for input level, characterized in that configured in connection with 1.