JPS589514B2 - Semiconductor memory common data line load circuit - Google Patents
Semiconductor memory common data line load circuitInfo
- Publication number
- JPS589514B2 JPS589514B2 JP56187029A JP18702981A JPS589514B2 JP S589514 B2 JPS589514 B2 JP S589514B2 JP 56187029 A JP56187029 A JP 56187029A JP 18702981 A JP18702981 A JP 18702981A JP S589514 B2 JPS589514 B2 JP S589514B2
- Authority
- JP
- Japan
- Prior art keywords
- common data
- data line
- semiconductor memory
- load circuit
- line load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
Landscapes
- Static Random-Access Memory (AREA)
Description
【発明の詳細な説明】
本発明はｐ．ｎチャンネル両方の型の
ＭＯＳＦＥＴを用いた、スタティック型メモリ回路のコ
モンデータ線の負荷回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention is based on p. This invention relates to a load circuit for a common data line of a static memory circuit using both types of n-channel MOSFETs.
従来、第１図に示す如き回路で、読み出しは次のように
行われていた。Conventionally, in a circuit as shown in FIG. 1, reading was performed as follows.
メモリセル２２を形成するトランジスタ５，６，７．８
より読み出された信号電流がスイッチ用のＦＥＴ９，１
０を通してコモンデータ線１１０，１１１（書込み、読
み出しのための共通データ線）に接続された負荷ＦＥＴ
３，４を流れ、そのとき生じた電位差が差動増巾器１１
により増巾される。Transistors 5, 6, 7.8 forming memory cell 22
The signal current read out from switch FET9,1
Load FET connected to common data lines 110 and 111 (common data line for writing and reading) through 0
3 and 4, and the potential difference generated at that time is applied to the differential amplifier 11.
The width is increased by
いっぽう、書き込み時にはＦＥＴ１，２を通してデータ
入力端子１１２，１１３より高、低両レベルの電圧がコ
モンデータ線に伝えられる。On the other hand, during writing, both high and low level voltages are transmitted from data input terminals 112 and 113 to the common data line through FETs 1 and 2.
このような従来回路の欠点は以下のようである。The drawbacks of such conventional circuits are as follows.
（１）読み出し時、コモンデータ線の電圧は、高レベル
の線がｖｃｃ−ｖＴ、低レベルの線がＶＣＣ一ｖＴ−Δ
Ｖ（ただし、Δｖは数１００ｍＶの信号振巾）となり、
ＦＥＴ３，４のしきい電圧ｖＴに差があると読み出し電
圧を生じ、アクセスタイムのばらつきの原因となる。(1) When reading, the voltage of the common data line is vcc-vT for the high-level line and VCC-vT-Δ for the low-level line.
V (however, Δv is a signal amplitude of several hundred mV),
If there is a difference between the threshold voltages vT of the FETs 3 and 4, a read voltage is generated, which causes variations in access time.
（２）書き込み時、コモンデータ線には十分な電圧振巾
が必要であるが、ＦＥＴＩ，２を通してＦＥＴ３，４の
負荷素子が接続された状態で十分低いレベルにコモンデ
ータ線の電圧を落とすことがむずかしい。(2) When writing, the common data line requires sufficient voltage amplitude, but the voltage of the common data line must be reduced to a sufficiently low level with the load elements of FETs 3 and 4 connected through FETI and 2. It's difficult.
そこで、第２図の如《、しきい電圧分の電圧降下を生せ
しめるｎチャンネルＭＯＳＦＥＴ１６と書込み時には切
り放され、読み出し時には抵抗の役目のするｐチャンネ
ノレＭＯＳＦＥＴ１７，１Ｂより成るコモンデータ線（
書込み、読み出しのための共通データ線）の負荷回路を
提供するのが本発明の骨子である。Therefore, as shown in Fig. 2, a common data line consisting of an n-channel MOSFET 16 that causes a voltage drop equal to the threshold voltage and a p-channel MOSFET 17, 1B that is disconnected during writing and serves as a resistor during reading (
The gist of the present invention is to provide a load circuit for a common data line for writing and reading.
本発明において、負荷素子１７，１ＢはｐチャンネルＭ
ＯＳＦＥＴであり、そのゲート電圧は読み出し時には接
地電位となってオン状態となる。In the present invention, the load element 17, 1B is a p-channel M
It is an OSFET, and its gate voltage becomes the ground potential during reading and turns on.
したがって１７，１Ｂは通常非飽和領域にバイヤスされ
、単なる抵抗として動作するためしきい電圧のばらつき
はコモンデータ線電位に何ら影響を与えない。Therefore, since 17 and 1B are normally biased in the non-saturation region and operate as mere resistors, variations in threshold voltage have no effect on the common data line potential.
また、書き込み時には書込み信号の端子４４への印加に
よりＭＯＳトランジスタ１７，１８はカット・オフとな
り、ＶＣＣ から流れる電流は完全に切断される。Furthermore, during writing, the MOS transistors 17 and 18 are cut off by applying a write signal to the terminal 44, and the current flowing from VCC is completely cut off.
したがって、コモンデータ線１１０，１１１の低レベル
となるべき線を十分低電圧に落とすことは容易である。Therefore, it is easy to reduce the voltage of the common data lines 110 and 111, which should be at a low level, to a sufficiently low voltage.
この他の効果として、書き込み信号端子４４よりのパル
スによりデータのオン・オフを行うＦＥＴ１４，１５お
よび、Ｙアドレス１１５の信号により選択されたビット
のデータ線とコモンデータ線のオン・オフを行うＦＥＴ
１９，２０の巾と長さ（Ｗ７Ｌ）比を大きくとらなくて
済むため、チップ面積の低減ができ、同時に高速の読み
出し、書き込みを行うことができる。Other effects include FETs 14 and 15 that turn on and off data by pulses from the write signal terminal 44, and FETs that turn on and off the data line of the selected bit and the common data line by the signal of the Y address 115.
Since the width to length (W7L) ratio of 19 and 20 does not have to be large, the chip area can be reduced and high-speed reading and writing can be performed at the same time.
図において、１１６はゲート線であり、２１は差動増巾
器である。In the figure, 116 is a gate line, and 21 is a differential amplifier.
第１図は従来のメモリ回路を示す図、第２図は本発明の
メモリ回路を示す図である。
２２……メモリセル、１１０，１１１……コモンデータ
線。FIG. 1 is a diagram showing a conventional memory circuit, and FIG. 2 is a diagram showing a memory circuit according to the present invention. 22...Memory cell, 110, 111...Common data line.
Claims (1)
みに共通の対をなすコモンデータ線に接続された半導体
メモリにおいて、前記対をなすコモンデータ線と電源端
との間にそれぞれ接続され、それぞれのゲートに印加さ
れるタイミング信号により前記メモリの書込み時にはカ
ットオフ状態、非書込み時にオン状態とされる対をなす
負荷用ＭＯＳトランジスタを有することを特徴とする半
導体メモリのコモンデータ線負荷回路。 ２ 前記メモリセルはｎ（ｐ）チャネルＭＯＳトランジ
スタで構成され前記負荷用ＭＯＳ｝ランジスタはｐ（ｎ
）チネネルＭＯＳ｝ランジスタである特許請求の範囲第
１項記載の半導体メモリのコモンデータ線負荷回路。[Claims] 1. In a semiconductor memory in which memory cells are connected to a pair of common data lines common for reading and writing via selection gates, between the pair of common data lines and a power supply terminal. A semiconductor memory common comprising a pair of load MOS transistors which are connected to respective gates and are cut off when writing to the memory and turned on when not written by a timing signal applied to each gate. Data line load circuit. 2 The memory cell is composed of an n(p) channel MOS transistor, and the load MOS transistor is a p(n
2. The common data line load circuit for a semiconductor memory according to claim 1, wherein the common data line load circuit is a transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56187029A JPS589514B2 (en) | 1981-11-24 | 1981-11-24 | Semiconductor memory common data line load circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56187029A JPS589514B2 (en) | 1981-11-24 | 1981-11-24 | Semiconductor memory common data line load circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57117181A JPS57117181A (en) | 1982-07-21 |
| JPS589514B2 true JPS589514B2 (en) | 1983-02-21 |
Family
ID=16198938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56187029A Expired JPS589514B2 (en) | 1981-11-24 | 1981-11-24 | Semiconductor memory common data line load circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS589514B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0636108U (en) * | 1992-10-14 | 1994-05-13 | 市光工業株式会社 | Vehicle lighting |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4791613A (en) * | 1983-09-21 | 1988-12-13 | Inmos Corporation | Bit line and column circuitry used in a semiconductor memory |
| JPS60154394A (en) * | 1983-09-21 | 1985-08-14 | ソーン、イーエムアイ、ノース、アメリカ、インコーポレーテッド | Bit line load for semiconductor memory |
| JPS6251092A (en) * | 1985-08-29 | 1987-03-05 | Sony Corp | Data line drive circuit |
| JPH087998B2 (en) * | 1985-11-21 | 1996-01-29 | ソニー株式会社 | Memory-circuit |
| JPS6376192A (en) * | 1986-09-19 | 1988-04-06 | Fujitsu Ltd | Semiconductor memory device |
-
1981
- 1981-11-24 JP JP56187029A patent/JPS589514B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0636108U (en) * | 1992-10-14 | 1994-05-13 | 市光工業株式会社 | Vehicle lighting |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57117181A (en) | 1982-07-21 |
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