JPS59207084A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To materialize a semiconductor memory device provided with a sensing circuit and characterized by low power consumption and high speed by connecting a data input to a gate with high input impedance and dividing a data output into inputs to the drain of a transistor (TR) and an output gate. CONSTITUTION:When a data input terminal DI3 is reduced from one level to the VTH value of a TR T11 while keeping a data input terminal DI4 at one level, the TR T11 is turned on and charging to the gate of a TR T16 is started. Since the gate capacity of the TR T16 is designed so as to be small, the charging will be completed comparatively fast. Consequently, a node N8 is turned to one level and the TR T16 is turned on. Since a TR T14 is off and the TRs T15, T16 are on, a node N9 is fixed at a GGN level. Therefore, no DC current including through current flow into the whole sensing circuit.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a static type semiconductor memory device.
0 [Prior Art] FIG. 1 is a block diagram showing a general static type semiconductor memory device. In the same figure, (11) is the X address terminal where the X address is input, (2) is the X address buffer where the
Y address input terminal where the address is input, (4) Y address buffer where the other Y address is read, (5)
is the memory part, (6) is the sense circuit that shows the data to humans, (
9) is an output buffer, and 001 is a data output terminal from which data is output.

Next, although there is no need to explain the overall operation of the semiconductor memory device with the above configuration, the sense circuit is installed at the location where memory data is transmitted to the output circuit, and the main electrical aspects such as operating margin and access time are This is a circuit that plays an important role in determining the physical characteristics of the vehicle. That is,
Due to the circuit configuration, when the data line from the memory cell is input to the sense circuit, for example, when VCC=5V, 'X1 level is 3.5V.

The 0# level was approximately 2.5V, and the common method was to sense the signal level with a sense circuit (8) and amplify it. However, in light of today's demands for faster speeds and lower power consumption in memory devices, the two data lines as inputs to the sense circuit are first set to VCC, then one of the data lines is set to the 10 level, and the difference between the two data lines is set to VCC. An operation method that senses and amplifies the current (precharge operation method) is becoming mainstream. First, the conventional sense circuit (8) shown in FIG. 2 is the most common circuit used in the precharge system, and basically has a flip-flop configuration. In the figure, (T1) and (T3) are P-channel transistors (Tz).

(T4) to (T6) are N-channel transistors, (I
NI) and (INz) are control input terminals to which sense circuit control signals shown in FIG. 3(b) and FIG. 3(c) are input, respectively.

Note that transistors (T1) and (T2)
Configures an inverter, transistors (T3) and (T
4) Configure the second inverter. Then, the first inverter and the second inverter are connected to the node (N2
)&- node (N4) and connect the node (N3) and node (N5) to form a flip 70 tube.

The transistors (T5) and (T6) are used to determine whether or not to drive the sense circuit (8), and more specifically, they are control transistors that control the set of the flip 70 knobs. 5)<<(Ts)K
design. Also, node (N2) and node (N5)
is connected to the data input and data output common terminals (DIl) and (DI 2 ).

Next, the operation of the sense circuit (8) having the above configuration will be explained with reference to FIGS. 3(a) to 3(c).

First, as shown in FIG. 3 (,), at time to,
Node (N2) = 11〃Leher, Node (Ns) =
Assume that the latch is tight at the 'Q' level.

In this state, the node (N2) = 10 level, the node (N5) = % 1 # To amplify the inverted data of the level, first at time t1, the input terminal (INl) =
u0 level, input terminal (lNz) 'Q' level, control transistors (T5) and (T6) "off"
Then, the sense circuit (8) is placed in a floating state. Next, from time tl to time t2, node (N2
) and node (N5) are precharged. Next, from time t2 to time t3, a signal that gradually drops toward the ground level (ゝゝ0〃 level) is input to the common terminal (DII). Then, when a level 11 is applied to the gate of the control transistor (Ts) from time t3 to time t4, the level of the node (N2) is amplified slowly because im of the control transistor (T5) is small.

Next, the '1〃level of node (N5) and node (N2)
The control transistor (T6) is activated at time t4 when there is a certain degree of difference between the levels of the control transistor (T6). By applying level 2 to the gate of the 9m large control transistor (T6), the level of the node (N'2) suddenly becomes 0.0. In this way, the common terminal ( DII) =SO#
The amplification operation of the sense circuit for the common terminal (DI2)=11/I level is completed. In addition, the common terminal (
DI 1)-ゝゝ1 L/to k, common m terminal (DI2
) = '0〃 The amplification operation for level 2 is performed in the same way. There are still common terminals (DI 1 ) and (DI2
) is the same signal as the common terminals (Dxl) and (DI2), which will be explained later in the circuit operation, but the difference is that in the case of 7 lip and 70 lip, the output is common mate, so the amplification time t
Up to 3, it operates as an input node, and after that it operates as an output node. The input and output of the circuit described later are separate.

In addition, the ``conventional differential amplification type sense circuit'' shown in Fig.
8), (T7) and (Tri are P-channel transistors, (T8) and (Tto) are N-channel transistors.
The gate of the transistor (T9) and the gate of the transistor (T9) are connected to the node (N6) in common. Further, the node (N7) is set as data output (Do). The operation of this sense circuit (8) is to transfer the signal from the input terminal (DI 1) to the transistor (T9).
This voltage is replaced by the potential difference between the drain and gate of the voltage, and the level difference between this voltage and the signal at the input terminal (DI2) is looked at and amplified.

However, in a conventional semiconductor memory device, when the basic configuration of the sense circuit is a 7-lip-flop configuration, noise occurs during the time (between t2 and t4) when the flip-flop data is divided into "1" and "10" after precharging. If the voltage difference between the node (N2) and the node (N5) is small, there is a possibility that the data will be inverted.If the transition goes to time t4 in this state, the inverted data will be amplified to 7 and 70 bits and set. The stored data will not return to its original state, leading to equipment malfunction.Also, if the control input terminal (INl) reaches level 11 too early at time t3, that is, the potential difference between the node (N2) and the node (N5) If the control input terminal (IN1) is set to the power level 1 when the control input terminal (IN1) is not in use, it will cause the flip-flop to malfunction.In this way, the sense circuit with the 70-tube flip configuration has a low input impedance at the input/output terminals, making it less susceptible to the effects of noise. easy to receive,
Furthermore, since the timing is controlled to operate, the control is difficult and the peripheral circuits are also complicated. Furthermore, when the control transistor is operated, a through current flows. on the other hand,
If the basic configuration of the sense circuit is a differential amplifier circuit, the input is connected to the gate with high input impedance and the output is connected to the drain to separate the input and output, so there is less worry about noise and data inversion. Due to the circuit configuration, DC current always flows through the circuit, making it difficult to reduce power consumption.

[Summary of the invention]

Therefore, an object of the present invention is to connect the data input to a gate with high input impedance, and to divide the data output into an input and an output gate that serve as the drain of a transistor. To provide a low-oil-power, high-speed semiconductor memory device equipped with a sense circuit that is strong, has no timing-related difficulties, consumes no DC power at all, and has extremely low AC power consumption. It is.

To achieve such an object, the present invention provides a first transistor of a first conductivity type, the drain of which is connected to a power supply voltage terminal, the source of which is connected to a first node, and the gate of which is connected to a first input terminal; a second transistor of a second conductivity type whose drain is connected to the first node; and a third transistor of a second conductivity type whose drain is connected to the source of the second transistor and whose source is connected to the reference voltage terminal. ,
a fourth transistor of a fourteenth conductivity type whose drain is connected to the power supply terminal, whose source is connected to the second node, and whose gate is connected to the second input terminal; and a second conductive type whose drain is connected to the second node. a sixth transistor of a second conductivity type, the drain of which is connected to the source of this fifth transistor, and the source of which is connected to the reference voltage terminal; the gate of the second transistor is connected to the first human power terminal; and when the gate of the fifth transistor is connected to the second input terminal, the gate of the third transistor is connected to the second input terminal.
node, the gate of the sixth transistor is connected to the first node, the gate of the third transistor is connected to the first input terminal, and the gate of the sixth transistor is connected to the second input terminal. The device includes a sense circuit in which the gate of the second transistor is connected to the second node, and the gate of the fifth transistor is connected to the first node, and will be described in detail below using an embodiment.

[Embodiments of the invention]

FIG. 5 is a circuit diagram showing one embodiment of a sense circuit used in a semiconductor memory device according to the present invention. In the same figure, (Tll) and (T14) are P-channel transistors, (TI, 2), (T13), (T15) and (Tls) are N-channel transistors, (N8) and (N9) are nodes, (DI s ) and (DI4)
is a data input terminal.

Note that the node (N8) and the node (N9) are connected to the data output terminal. Also, Fig. 6(,) and Fig. 6(
b) is the inverter circuit and its input voltage (Vcc)
- It is a diagram showing power supply current (I) characteristics. In the same figure,
(Tl7) is a P-channel transistor, (Tt s)
is an N-channel transistor, (I'N) is an input terminal,
(OUT) is an output terminal O. Next, the operation of the sense circuit used in the semiconductor memory device having the above configuration will be explained. First, when the data input terminals (DI 3 ) and (DI 4 ) are precharged to the "1" level, the transistors ('r+z) and (Tls) are turned "on" and the transistor (Tz
t ) and (T14) are 6 off. Therefore,
Nodes (N8) and (N9) are at floating level, but the initial state is set by setting them to ground (GND) level. Now, the data input terminal (DI
a) remains at the 'X1〃 level, and the data input terminal (D
I s ) from level 11 to transistor (Tlt)
When the VTH value of this transistor (Tst) decreases to
turns 1 on and starts charging the gate of the transistor (T16).
Since the gate capacitance of 16) is designed to be small, charging is completed relatively quickly. With this, the node (N8) is 11"
When the level is low, the transistor (T16) becomes "on". Also, the transistor (T14) is not “off”.
Since the transistors (T15) and (T16) are turned on, the node (N9) is fixed at the ground (GND) level.Now, in the case of a normal inverter, as shown in FIG.
, ) and as shown in Figure 6(b), when the input voltage is -V
When cc is at an intermediate level, a through current flows even during the period when both the P-channel transistor and the N-channel transistor are turned on. Therefore, in this embodiment, the transistors (T13) and (T16)
This through current can be prevented.

That is, as the data input terminal (DI 3 ) decreases, a through current tends to flow between the transistors (T11) and (Tlz), but since the node (N) is at the ground (GND) level, the transistor (T13) )teeth"
Since the transistor (Tl 1 ) - transistor (T12) -) transistor (T13) - ground (GND) is turned off, no current flows in the series path. Also, the transistors (T15) and (Tts) are turned on. ”
However, since the transistor (T14) is 1 off, the transistor (T14) -)
ls) - Transistor (T16) - Ground (GND
) no current flows in the series path. Therefore, no DC current, including through current, flows through the entire sense circuit.

FIG. 7 is a circuit diagram showing another embodiment of the sense circuit used in the semiconductor memory device according to the present invention. In the figure, (T19) and (T22) are P-channel transistors, (T20), (T21), (T23) and (T24) are N-channel transistors, and (N, , ) and (N11) are nodes. be.

It should be noted that the operation of the sense circuit with the above configuration is not only the same as that described in FIG. 5, but also the transistors (T20) and (T23) prevent through current. Moreover, during precharging, the source potential of transistors (T2O) and (T23) is (SO
Since it enters a standby state at the // level, the circuit configuration can immediately respond to the next data input change operation.

Next, FIGS. 8(a) and 8(b) show an example of a circuit operation simulation comparing the characteristics of the sense circuit shown in this embodiment and a conventional sense circuit.
T) A waveform diagram and a power supply current (I) waveform diagram. Here, the voltage waveform is the output voltage waveform when the data input terminal (DI4) = VCC and the data input terminal (DI3) is changed from VCC to GND level in 100 ns.
i, VCC is a condition of 5V. In the sense circuits shown in the embodiments of FIGS. 5 and 7, the output voltage waveform (Ll) of the input inversion output terminal (for example, the node (N4 o ) in FIG. 7) is shown. In addition, in a conventional sense circuit with a differential amplifier configuration, the output voltage waveform (L2) is shown at the inverted output terminal of the input (node (N7) in FIG. 4), whereas in a conventional sense circuit with a flip-flop configuration, the output voltage waveform (L2) is Figures 5 and 7 show the output voltage waveforms (L3) and (L4) of nodes (N2) and (N5) at node 2-. In the sense circuit shown in the figure, approximately 51
It operates at a time of ns, and operates at 2 Ins after the data input terminal (DI3) changes.

In this way, it can be seen that the rising edge waveform is sharper than that of the conventional sense circuit. Also, the output waveform rises at 46ns, which means that vth is 0.
．． Since it is set to 7V, operation starts at a voltage of Vcc -vth. Therefore, sensitivity can be changed depending on Vth.

Next, to explain the power supply current (I) shown in FIG. 8(b), in the conventional sense circuit having a differential amplifier configuration shown in FIG. flows. 1. In the conventional flip-flop sense circuit shown in FIG.
A through current of about mA flows.

Unfortunately, the sense circuits shown in the embodiments of FIGS. 5 and 7 are curved; no through current flows as shown in vM3
The charging current only flows during the short time it takes to sense the input voltage. In this example, the peak value is 0.1 mA. In this way, the power supply current is dramatically small and it is resistant to Vcc fluctuations.

Although the above embodiments have been described with respect to the sense circuit, it goes without saying that the same can be applied to other circuits such as inverters that are characterized by low power consumption.

In addition, the P-channel transistor is a transistor of the first conductivity type, and the N-channel transistor is a transistor of the second conductivity type, but the N-channel transistor is a transistor of the first conductivity type, and the P-channel transistor is a transistor of the second conductivity type. Of course, a conductive type transistor may also be used.

〔Effect of the invention〕

As explained in detail above, according to the semiconductor memory device according to the present invention, no through current flows due to the precharge operation method, and a sense circuit with a wide operating margin can be realized.
There are effects such as being able to provide a semiconductor memory device that is high speed and consumes low power.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a static type semiconductor memory device, Fig. 2 is a circuit diagram showing a conventional sense circuit, and Figs. 4 is a circuit diagram showing another conventional sense circuit, FIG. 5 is a circuit diagram showing an embodiment of the sense circuit used in the semiconductor memory device according to the present invention, and FIG. 6 is a diagram showing waveforms of various parts. (a) and FIG. 6(b) are diagrams showing an inverter circuit and its input voltage (Vcc)-power supply current (I) characteristics, and FIG. 7 is a circuit showing another embodiment of the sense circuit shown in FIG. 5. Figure, 8th
Figure (IL) and Figure 8 (b) are output voltage (VOUT) waveform diagrams and power supply current (I) waveform diagrams showing examples of circuit operation simulations comparing the characteristics of the sense circuit according to the present invention and the conventional sense circuit. It is. (1)...X address input terminal, (2)...X
Address buffer, (3)...X address input terminal, +41...Y address buffer, (51...
Memory section, (6)...Data input terminal, (7)...
...Control circuit, (8)...Sense circuit, (9)...
...Output buffer, α0) write...Data output terminal, (
T1) (T24)...Transistor, (Nz)~
(Nl 1)・Fist・・Node, (DIt) and (DI
2)...Fist common terminal, (DI3) and (DI4)
...Data input terminals, (INI) and (IN2)
...Control input terminal. Agent Masuo Oiwa Fig. 1 Y At L7 Fig. 3 Fig. 4 Fig. 5 Fig. 6 (Q) (b) CC Fig. 7 1L1 "Indication of 1 horse 1988-81908 No. 2
1 Name of the invention Semiconductor memory device 3 Name of the province to be amended Name (601) - Hitsubishi Electric Co., Ltd. Representative Hitoshi Katayama 8th Department Address 2-3 Marunouchi 2-chome, Chiyo 1i1 Ward, East East Goryo Electric Co., Ltd. Company name (7375) Patent attorney Masu Oiwa) jV. 5. Correction. Target (,:zH″H5/,l,・03
:2+1+) +! :, :11″′□″′″″ (1) Detailed explanation of the invention column 6 of the specification, contents of amendment (1) r (IN,) and (
IN2) J is corrected as “(IN1) and (IN2) J. (2) r(INt)J in page 5, line 11 of the same book is corrected as r(Il
'h) Correct as j. (3) In line 12 of the same page of the same book, r(ll'h)j is
2)”. (4) r(IN+)J on page 7, line 20 of the same book
t) Correct with J. (51 Ibid., page 8, line 3, r(INl)J
) Correct as J. (6) In the same book, page 12, lines 12-13, "therefore" is amended to "however." (7) The word "-transferable" in line 20 of page 16 of the same ministry is corrected to "general, targeted."that's all

Claims (1)

[Claims] a first whose drain is connected to the power supply voltage terminal, whose source is connected to the first node, and whose gate is connected to the first input terminal;
a first transistor of a conductivity type; a second transistor of a second conductivity type, the drain of which is connected to the first node; and a second transistor, the drain of which is connected to the source of the second transistor, and the source of which is connected to the reference voltage terminal. a third transistor of a second conductivity type, a fourth transistor of a first conductivity type whose drain is connected to the power supply terminal, whose source is connected to the second node, and whose gate is connected to the second input terminal; a fifth transistor of a second conductivity type connected to the second node; and a sixth transistor of a second conductivity type whose drain is connected to the source of the fifth transistor and whose source is connected to the reference voltage terminal.
transistors, the gate of the second transistor is connected to the first input terminal, the gate of the fifth transistor is connected to the second input terminal, the gate of the third transistor is connected to the second node, and the gate of the sixth transistor is connected to the second node; The gate of the transistor is connected to the first node, and if the gate of the third transistor is connected to the first input terminal and the gate of the sixth transistor is connected to the second input terminal, the gate of the second transistor is connected to the first input terminal. 1. A semiconductor memory device comprising: a sense circuit connected to two nodes, the gate of a fifth transistor being connected to the first node.