JP2914311B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit composed of MOS field effect transistors.

[0002]

2. Description of the Related Art A memory cell in a DRAM (Dynamic Random Access Memory) constituted by MOS field effect transistors comprises one N-channel transistor and one capacitor. In this DRAM, information is stored depending on whether a "High" level charge or a "Low" level charge is stored in a capacitor.

[0003] The transfer of information to and from a memory cell, that is, the reading and writing of data, is performed by turning an N-channel transistor "ON" / "OFF". At this time, the power supply (VCC) level is ideal for the "High" level write voltage, and the level of the gate (word line) for switching the N-channel transistor is VCC + VtN (where VtN is the threshold value of the N-channel transistor). The above is required.

That is, the level of a word line is boosted to a level higher than VCC + VtN at the time of reading or writing, and a conventional semiconductor integrated circuit for generating this boost level has, for example, a configuration as shown in FIG. Have been.

In FIG. 4, I361 to I310 denote inversion circuits (inverters), NA31 denotes a NAND circuit, and NO31 denotes a NOR circuit.
Circuit, QP31 to QP33 are P-channel transistors, QN31
QN37 to N-channel transistors, C31 to C33 to capacitors, and N301 to N316 to nodes.

FIG. 5 is a signal waveform diagram for explaining the operation of the circuit shown in FIG. The operation of the circuit shown in FIG. 4 will be described below with reference to the signal waveform diagram of FIG.

The internal signals φ31 to φ34 are external input signals RA
The signal is generated by each signal internal generation circuit from S￣ (Row-address-strobe).

First, in the standby state, RAS # is set to "High", φ32 and φ34 are both "High" at the VCC level, and φ31 and φ33 are "L" at the GND level.
ow ", so that the output signal φ35 is at the GND level. At this time, the level of the word line of each memory cell is also at the G level.
ND level.

At this time, the node N306 is at VCC + VTN
(VTN is the threshold value of the N-channel transistor) or more, so that the transistor QN36 is turned on.
State. Therefore, node N303 is, in this case, VC
Held at C level.

However, since the node N306 is in a floating state when boosted, the level of the node N306 decreases due to leakage or the like.
Is turned off, and the VCC level of the node N303 cannot be guaranteed.

When the power supply is turned on and the boost at the node N306 fails, the node N303 is connected to the transistor QN.
32, the voltage is precharged up to the level of VCC-VTN.
It will be precharged to the level.

Since the transistor QP32 is for ensuring the level of the node N303 in the standby state, the capability (current driving capability) may be small.

Next, RAS # is changed from "High" to "Lo".
When it becomes w "(active), an internal Row address is generated according to the external Row (row) address.

On the other hand, the internal signal φ32 is changed from “High” to “Low” by each signal internal generation circuit, and the node N
305 becomes the VCC-VTN level.

Next, the signal φ34 changes from “High” to “Lo”.
When "w", the node N316 becomes "Low" and the transistor QN37 is turned off.

Next, the signal φ31 changes from “Low” to “Hig”.
h ", the node N302 becomes" Low "at the GND level.
, The transistor QP32 changes from the ON state to the OFF state.

Next, the signal φ33 is changed from “Low” to “High”.
h ", the node N305 is boosted to a level of VCC + VTN or more, so that the transistor QN34 is turned on.
Then, the node N306 goes down to the VCC level. For this reason,
The transistor QN36 turns off.

Thereafter, the node N309 changes from the GND level to VC.
Since the level is at the C level, the node N303 is boosted from VCC to VCC + VTN level or more.

Since the transistor QP31 is ON,
The node N302 performs the same operation as the node N303. At about the same time, the transistor QP33 is also turned on, so that the signal φ35 is raised from the GND level to a level higher than VCC + VTN.

By this signal φ35, the word line selected by the internal Row address is raised to a level of VCC + VTN or higher. As a result, data can be read from or written to the memory cells on the selected word line.

Next, RAS # changes from "Low" to "Hig".
When the signal becomes "h", the active state changes to the standby state, and the signal .phi.32 first changes from "Low" to "High." Then, the node N305 changes to the "Low" level, so that the transistor QN34 is turned off.

Next, the signal φ34 is changed from “Low” to “Hig”.
h ”and then the signal φ33 changes from“ High ”to“ Lo ”.
w ”.

As a result, the transistor QN37 is turned on and the transistor QP33 is turned off, so that the signal φ35 changes from the level higher than VCC + VTN to the GND level. At the same time, the selected word line also goes to the GND level.

At this time, the node N303 is set to "Hi"
gh ”is changed to“ Low ”, so that it is pulled to a level lower than the power supply voltage Vcc by the couple (capacitive coupling) of the capacitor C33. Similarly, the node N302 is pulled to a level lower than Vcc.

Immediately thereafter, the node N306 is boosted to a level higher than VCC + VTN and the transistor QN36 is turned on, so that both the nodes N303 and N302 are precharged to the VCC level.

However, the signal φ31 changes from “High” to “L”.
As a result, the node N302 becomes GND level "Low", and the transistor QP32 is turned on.

Thus, as described above, the node N306
Is at a level lower than VCC + VTN due to leakage or the like, and even if the transistor QN36 is turned off, the transistor QP32 is turned on in the standby state, so that the VCC level of the node N303 is guaranteed.

[0028]

In the conventional semiconductor memory device, the time chart shown in FIG.
S￣ changes from “Low” to “High” (FIG. 5), the signal φ32 changes from “Low” to “High” (FIG. 5), and then the signal φ34 changes from “Low” to “High”.
h "(FIG. 5), the signal .phi.33 changes from" High "to" Low "(FIG. 5), and when the node N303 is pulled to a level lower than VCC by the couple of the capacitor C33 (FIG. 5). 5), the drain of transistor QP32
Since it is fixed to the VCC level, the transistor QP32
Has a problem in that the well potential becomes lower than the drain potential, and latch-up easily occurs in this portion.

In this case, the latch-up is likely to occur when the level of the node N303 becomes equal to or lower than VCC-VT (VT is the threshold value of the transistor).

Accordingly, the present invention has been made in view of the above problems, and has as its object to precharge to a power supply level during standby and to raise the voltage to a higher level during active standby. It is an object of the present invention to provide a semiconductor memory device having a configuration for preventing latch-up in a circuit that guarantees the level of the above.

[0031]

In order to achieve the above object, a semiconductor memory device according to the present invention includes a node which is precharged to a power supply level in a standby state and boosted to a power supply level or more in an active state. In a semiconductor integrated circuit having a circuit for ensuring the following, the P-channel transistor of the circuit is configured such that both the source and the well are connected to the node, and the drain is controlled by an internal signal. Features.

Also, in the present invention, when the source and the well of the P-channel transistor are boosted at the time of active, the drain of the P-channel transistor is connected when the potential of the node falls below the power supply potential. Is controlled to be lower than the node potential.

[0033]

Embodiments of the present invention will be described below. The present invention, in a preferred embodiment thereof, is precharged to a power supply level during standby,
A node that is boosted above the power supply level when active (Fig. 1
N105), a P-channel transistor (QP12 of FIG. 1 or QP22 of FIG. 3) of a semiconductor integrated circuit having a circuit for guaranteeing a standby level.
Means that both the source portion and the well portion are at this node (N10 in FIG. 1).
5, N204 in FIG. 3), the drain portion is not fixed to the power supply potential as in the prior art, but is controlled by a predetermined internal signal (φ11 in FIG. 1, inverters I102 and I103, or φ21 in FIG. 3). , CR circuit, etc.) and immediately after resetting the row address strobe signal (RAS), the node (N10 in FIG. 1)
When the potential of 5) falls below the power supply potential, the drain potential is controlled to be the ground potential.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a circuit configuration of a semiconductor memory device according to one embodiment of the present invention. In FIG.
I112 is an inverting circuit (inverter circuit), NA11 is a NAND
Circuit, NO11 is a NOR circuit, QP11 to QP13 are P-channel transistors, QN11 to QN17 are N-channel transistors, C11 to C13 are capacitors, and N01 to N118 are nodes.

Next, the operation of the circuit shown in FIG. 1 will be described with reference to the timing chart of FIG.

The internal signals φ11 to φ14 are generated by each signal internal generation circuit from the external input signal RAS # (row address strobe signal) in the same manner as in the above-mentioned prior art.

First, RAS # is set to "H" in the standby state.
The signals φ12 and φ14 are both “High” at the VCC level, the signals φ11 and φ13 are “Low” at the GND level, and the output signal φ15 is at the GND level. Word line level is also GND
Level. At this time, the node N108 is connected to VCC.
Since the voltage is boosted to a level equal to or higher than + VTN, the transistor QN16 is turned on.

Therefore, the node N105 is held at the VCC level at this time. At this time, as in the above-described prior art, in order to ensure the VCC level of the node N105, the node N102 is set to the GND level and the transistor QP
12 is turned on, and the node N104 is at the VCC level. The operation of the other signals is the same as in the above-described related art.

Next, RAS # is changed from "High" to "Lo".
When it becomes w ", an internal Row address is generated in accordance with the external Row address as in the above-described conventional technique.
The internal signal φ12 is set to “High” by each signal internal generation circuit.
"h" to "Low", and the node N107 becomes the level of VCC-VTN.

Next, the signal φ14 is changed from “High” to “Lo”.
When "w", the node N118 becomes "Low" and the transistor QN17 is turned off.

Next, the signal φ11 changes from “Low” to “High”.
h ”, the node N102 becomes“ Low ”at the GND level.
, The transistor QP12 is turned off.

After a short delay, the node N104 changes from "High" at the VCC level to "Low" at the GND level.

Next, the signal φ13 is changed from “Low” to “High”.
h ", the node N107 is boosted to a level of VCC + VTN or more, so that the transistor QN14 is turned on.
Then, the node N108 goes down to the VCC level. For this reason,
The transistor QN16 turns off.

Thereafter, the node N110 changes from the GND level to VC.
Since the level becomes the C level, the node N105 is changed from VCC to VCC + VTN.
Boosted to above level. Since the transistor QP11 is ON, the node N102 operates similarly to the node N105. Almost at the same time, the transistor Q
Since P13 is also turned on, the signal φ15 is raised from the GND level to a level equal to or higher than VCC + VTN (FIG. 2).

The word line selected by the internal Row address by the signal φ15 is raised to a level of VCC + VTN or higher, as in the above-mentioned prior art.

Next, RAS # is changed from "Low" to "Hig".
When the signal becomes "h", the active state changes to the standby state, and the signal φ12 first changes from "Low" to "High." Then, the node N107 changes to the "Low" level, so that the transistor QN15 is turned off.

Next, the signal φ14 changes from “Low” to “Hig”.
h ”and then the signal φ13 changes from“ High ”to“ Lo ”.
As a result, the transistor QN17 is turned on and the transistor QP13 is turned off, so that the signal φ15 changes from the level higher than VCC + VTN to the GND level (FIG. 2). At the same time, the selected word line is also set to GN.
It becomes D level.

At this time, the node N105 is set so that the node N110 is "Hi".
Since "gh" changes to "Low", the node C102 is pulled to a level lower than VCC by the couple of the capacitor C13 (FIG. 2).

Immediately thereafter, the node N108 is boosted to a level higher than VCC + VTN (FIG. 2), and the transistor QN1
6 is turned on, so both nodes N105 and N102 have VCC
It is precharged to the level (FIG. 2).

However, when the level of the signal φ11 becomes close to the VCC level to some extent, the signal φ11 changes from “High” to “Low”, so that the node N102 becomes “Low” of the GND level.
After a short delay, the node N104 changes from "Low" at the GDN level to "High" at the VCC level. Therefore, in the standby state, the VCC level of the node N105 is guaranteed in the standby state. In addition, the potential of the node N104 does not become higher than that of the node N105.

FIG. 3 is a diagram showing a circuit configuration of a second embodiment of the present invention. Referring to FIG. 3, the present embodiment is different from the above-described embodiment shown in FIG. 1 in that two inverting circuits I102 and I103 functioning as a non-inverting type delay circuit are replaced by a CR integrating circuit comprising a resistor R21 and a capacitor C21. Is replaced by

In FIG. 3, the movement of each signal is represented by the signals φ11 → φ21, φ12 → φ22, φ
13 → φ23, φ14 → φ24, φ15 → φ25, Node N102 → N20
2, N104 → N203, N105 → N204, N108 → N207, N114
→ This corresponds to N213, and the waveform operation is the same as that of the first embodiment.

In the embodiment shown in FIG. 3, since the two inverting circuits I102 and I103 in FIG. 1 are replaced by the resistor R21 and the capacitor C21, the number of elements is small. To the node N2
03 can be easily adjusted from “Low” to “High” irrespective of the signal φ21.

[0054]

As described above, according to the present invention,
Node N1 which is the drain of P-channel transistor QP12
04 by operating the signal φ11 generated internally,
Immediately after the AS @ reset, when the node N105 falls below the VCC level, the node N104 is set to the GND level to prevent latch-up.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing internal signal waveforms for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a second embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a conventional technique.

FIG. 5 is a diagram showing internal signal waveforms for explaining the operation of the conventional technique.

[Explanation of symbols]

C11 to C13, C21 to 24, C31 to C33 Capacity I101 to I112, I201 to I210, I301 to I310 Inverting circuit NA11, NA21, NA31 NAND circuit NO11, NO21, NO31 NOR circuit N101 to N118, N201 to N217, N301 to N316 Nodes QN11 to QN17, QN21 to QN27, QN31 to QN37 N-channel transistors QP11 to QP13, QP21 to QP23, QP31 to QP33 P-channel transistors

Claims (3)

(57) [Claims] 1. A semiconductor integrated circuit having a circuit for preserving a standby level of a node which is precharged to a power supply level in a standby state and boosted to a power supply level or more in an active state. A semiconductor integrated circuit, wherein the transistor has a source portion and a well portion both connected to the node, and the drain portion is controlled by an internal signal. 2. The method according to claim 1, wherein the boost is activated when the source is connected to the well of the P-channel transistor.
2. The semiconductor integrated circuit according to claim 1, wherein the potential of the drain of the channel transistor is controlled to be lower than the node potential. 3. A semiconductor integrated circuit provided with a circuit for preserving a standby level of a node which is precharged to a power supply level in a standby state and boosted to a power supply level or more in an active state. The source and the well are both connected to the node, and the drain is not fixed to the power supply potential but is controlled by a predetermined internal signal. Immediately after resetting the row address strobe signal (RAS), the potential of the node is changed to the power supply potential. A semiconductor integrated circuit wherein the drain potential is controlled to a ground potential when the potential drops below a potential.