JPH038016A - Latch data bit operating circuit - Google Patents

Latch data bit operating circuit

Info

Publication number
JPH038016A
JPH038016A JP14363989A JP14363989A JPH038016A JP H038016 A JPH038016 A JP H038016A JP 14363989 A JP14363989 A JP 14363989A JP 14363989 A JP14363989 A JP 14363989A JP H038016 A JPH038016 A JP H038016A
Authority
JP
Japan
Prior art keywords
bit
data
output
circuit
select
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14363989A
Other languages
Japanese (ja)
Inventor
Hisashi Nonaka
野中 久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Computertechno Ltd
Original Assignee
NEC Computertechno Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Computertechno Ltd filed Critical NEC Computertechno Ltd
Priority to JP14363989A priority Critical patent/JPH038016A/en
Publication of JPH038016A publication Critical patent/JPH038016A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve efficiency in a software by providing first and second select circuits to select whether the respective bits of latch data are maintained as they are, converted to new values or 0 or 1 is made effective as the new value of the bit. CONSTITUTION:The most significant bit of the latch data is defined as D7 and bit data written by a CPU in a select circuit 2a is defined as input D7. Effective bit data select inputs SL0 and SL1 are applied to set whether the input D7 is made effective when the value of the bit is 0, made effective when the value is 1 or made always effective. The output of the circuit 2a is the output of a gate in a block. Then, when the bit data of preceding time are remained as they are, 0 is outputted and when the bit data are newly written, 1 is outputted. A select circuit 1a is a select circuit to output either the bit data of the preceding time or the newly written bit data to a latcher 3a. For a control signal to be the selection, the output of the circuit 2a is used.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は出力ポートのラッチデータの操作に関し、特に
ラッチデータビット操作回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the manipulation of latch data of an output port, and more particularly to a latch data bit manipulation circuit.

〔従来の技術〕[Conventional technology]

従来、ソフトウェアによっである出力ポートのラッチデ
ータの任意のビットを変更する場合、他のビットに影響
を与えないなめにはソフト上でそのポートに書きこんだ
データを記憶(RAMエリア上に確保)しておき、ラッ
チデータのあるビットを操作する時に前回のデータを参
照し必要とするビットのみを変更した後、出力ポートに
変更した出力データを書きこみ、その値を再び記憶(R
AMエリア上に確保)する手法をとっている。
Conventionally, when changing arbitrary bits of the latch data of an output port using software, the data written to that port was stored in the software (reserved in the RAM area) in order to avoid affecting other bits. ), and when manipulating a certain bit of latch data, refer to the previous data and change only the necessary bits, then write the changed output data to the output port and store the value again (R
We are taking a method to secure it in the AM area).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の手法では出力ポート毎に出力データを記
憶するRAMエリアの設定が必要であり、またソフト的
に1回のラッチデータのライトを行う毎にデータ情報を
RAMエリアから引き出し参照し変更した後、再度RA
Mエリアに格納する操作が必要となっている。したがっ
てソフト的に効率も悪く高速な変更が必要な場合に対応
しきれないという欠点がある。
In the conventional method described above, it is necessary to set a RAM area to store output data for each output port, and each time latch data is written by software, data information is pulled out from the RAM area, referenced, and changed. After that, RA again
An operation is required to store it in the M area. Therefore, it has the disadvantage that it is inefficient in terms of software and cannot respond to cases where high-speed changes are required.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のラッチデータビット操作回路は、出力ポートに
出力したラッチデータの各ビットをそのままにしておく
か新たな値に変更するかを選択する第一のセレクト回路
と、新たなビットの値として0を有効にするか1を有効
にするかを選択する第二のセレクト回路とを有する。
The latch data bit manipulation circuit of the present invention includes a first select circuit that selects whether to leave each bit of latch data output to an output port as it is or change it to a new value, and a first select circuit that selects whether to leave each bit of latch data output to an output port as it is or change it to a new value, and a new bit value of 0. and a second select circuit that selects whether to enable 1 or 1.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示す構成図である。同図に
おいてラッチデータビット操作回路は、前回の出力ポー
トのラッチデータの各ビットの値を有効とするか新たな
ビットの値を有効とするかを選択するための制御信号を
出すセレクト回路2と、上記の制御信号を受はラッチャ
3への入力に前回のビットデータか新たに書きこんだデ
ータかを選択するセレクト回路1とを有する。
FIG. 1 is a block diagram showing an embodiment of the present invention. In the same figure, the latch data bit manipulation circuit includes a select circuit 2 that outputs a control signal for selecting whether to validate each bit value of the latch data of the previous output port or to validate a new bit value. , and a select circuit 1 which receives the above control signal and selects the previous bit data or newly written data to be input to the latch 3.

第2図はデータの最上位ビット(D7)を例にした具体
的な回路図である。セレクト回路2aにおいてCPUが
書き込んだビットデータ入力D7と、それをOの時有効
にするか1の時有効にするかもしくは常に有効にするか
設定する有効ビットデータセレクト入力SLO,SLI
がある。セレクト回路2aの出力はブロック内のゲート
出力であり、前回のビットデータをそのまま残す時″0
″′、新たに書き込んだビットデータにする時1″が出
力される。
FIG. 2 is a specific circuit diagram using the most significant bit (D7) of data as an example. Bit data input D7 written by the CPU in the select circuit 2a and valid bit data select inputs SLO and SLI that set whether to enable it when it is O, enable it when it is 1, or always enable it.
There is. The output of the select circuit 2a is the gate output within the block, and when the previous bit data is left as is, it becomes ``0''.
``'', 1'' is output when newly written bit data is written.

セレクト回路1aは前回のビットデータが新たに書きこ
んだビットデータかのどちらかをラッチャ3aに出力す
る選択回路であり、選択となる制御信号はセレクト回路
2aの出力を使用する。
The select circuit 1a is a select circuit that outputs either the previous bit data or the newly written bit data to the latch 3a, and the output of the select circuit 2a is used as the control signal for selection.

第2図はビット7についてのみの例であるが、データが
8bitの場合には同様なつなぎを行えばよい。
Although FIG. 2 is an example of only bit 7, if the data is 8 bits, similar connections may be made.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ソフトウェアがあるポー
トの出力したラッチデータの任意のビットのみを変更す
る場合、他のビットに影響を与えないためのソフトウェ
アの操作を最小限にし、ソフトウェアの容量を減らし効
率を上げる効果がある。
As explained above, in the present invention, when software changes only an arbitrary bit of latch data output from a certain port, the software operation is minimized so as not to affect other bits, and the capacity of the software is reduced. It has the effect of reducing and increasing efficiency.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す構成図、第2図は回路
図である。 1.2・・・セレクト回路、3・・・ラッチャ。
FIG. 1 is a configuration diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram. 1.2...Select circuit, 3...Latcher.

Claims (1)

【特許請求の範囲】[Claims] 出力ポートに出力したラッチデータの各ビットをそのま
まにしておくか新たな値に変更するかを選択する第一の
セレクト回路と、新たなビットの値として0を有効にす
るか1を有効にするかを選択する第二のセレクト回路と
を有することを特徴とするラッチデータビット操作回路
A first select circuit that selects whether to leave each bit of the latch data output to the output port as is or change it to a new value, and enable 0 or 1 as the new bit value. A latch data bit manipulation circuit comprising: a second select circuit for selecting one of the latch data bits;
JP14363989A 1989-06-05 1989-06-05 Latch data bit operating circuit Pending JPH038016A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14363989A JPH038016A (en) 1989-06-05 1989-06-05 Latch data bit operating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14363989A JPH038016A (en) 1989-06-05 1989-06-05 Latch data bit operating circuit

Publications (1)

Publication Number Publication Date
JPH038016A true JPH038016A (en) 1991-01-16

Family

ID=15343449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14363989A Pending JPH038016A (en) 1989-06-05 1989-06-05 Latch data bit operating circuit

Country Status (1)

Country Link
JP (1) JPH038016A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005247207A (en) * 2004-03-05 2005-09-15 Hayashi Engineering Inc Sun visor for automobile
US7566088B2 (en) 2003-09-29 2009-07-28 Hayashi Engineering Inc. Sun visor for automobiles

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59170937A (en) * 1983-03-18 1984-09-27 Nec Corp Logical operation circuit
JPH02213937A (en) * 1989-02-15 1990-08-27 Hitachi Ltd Data processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59170937A (en) * 1983-03-18 1984-09-27 Nec Corp Logical operation circuit
JPH02213937A (en) * 1989-02-15 1990-08-27 Hitachi Ltd Data processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7566088B2 (en) 2003-09-29 2009-07-28 Hayashi Engineering Inc. Sun visor for automobiles
JP2005247207A (en) * 2004-03-05 2005-09-15 Hayashi Engineering Inc Sun visor for automobile

Similar Documents

Publication Publication Date Title
JPH06162228A (en) Data flow processor device
JPH038016A (en) Latch data bit operating circuit
JP3057749B2 (en) I / O port
JP3221003B2 (en) I / O port
JPS6148174B2 (en)
JPH0135376B2 (en)
JPH04181347A (en) Address setting system for input/output port of microcomputer
JPH0795265B2 (en) Comparison circuit
JPS6378265A (en) Process controlling system
JPH01191966A (en) Data processing system
JPS63263526A (en) Information processing system
JPS6367052A (en) Transmitter for serial data
JPS6375849A (en) Memory device control system
JPH0895781A (en) Arithmetic and logic unit of processor
JPS5947339B2 (en) data processing unit
JPS63305405A (en) Method and device for processing sequence control
JPS6133554A (en) Zone control circuit
JPH11249958A (en) Memory control system
JPH01271990A (en) Ram
JPS62160550A (en) Memory write system
JPH03219497A (en) Memory device
JPH03141425A (en) Logic arithmetic system
JPH02136951A (en) Dma transfer system
JPS6113345A (en) Processor of tagged data
JPS6031663A (en) Switching device of memory