JP3221003B2 - I / O port - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output port,
In particular, the present invention relates to a circuit for improving operability for a plurality of specific bits and reducing a load on software.

[0002]

2. Description of the Related Art A conventional input / output port includes an input / output terminal, an internal bus, an output latch for setting a value between the input / output terminal and the internal bus by a dedicated instruction, a state of the input / output terminal or an output. It has an input circuit for taking the value of the latch into the internal bus by a dedicated instruction, and each dedicated instruction has realized an operation in units of 8 bits or 1 bit.

[0003]

The above-mentioned conventional input / output port has the following disadvantages.

First, a dedicated instruction for operating on an input / output port is in units of 8 bits or 1 bit. For example, when operating on a specific plurality of bits, an output is performed to hold the contents of a port other than the operation target. Read the latch value (8 bits) Calculate the read value and the bit to be operated Set the operation result (8 bits) in the output latch, etc. There is a disadvantage that the output is delayed during the operation.

[0005]

An input / output port according to the present invention comprises a control register, a gate circuit controlled by the control register between an internal bus and an output bus, and the output latch via the gate circuit. There is a dedicated instruction to set the value to.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of an embodiment of the present invention.

As shown in FIG. 1, an input / output port of the present embodiment has a control register 3 between an internal bus 1 and an output latch 2.
, And only the bits specified by the setting of the control register are given to the output latch 2 via the gate circuit 4 for the data according to the write-only instruction A to the input / output port.

Next, the operation of this embodiment will be described.

In this embodiment, the gate circuit 4 is constituted by an AND gate, and outputs data corresponding to the set bit of the control register 3 of the internal bus data in response to a write instruction A to the input / output port. Latched by latch 2. At this time, since the latch signal of the output latch 2 is given only to the set bit of the control register 3, the data latched in the output latch 2 by the write instruction A to the input / output port is Only the bits that have been set to “1” and the data of the output latch 2 corresponding to the bits that have been reset to “0” in the control register 3 retain the values before the execution of the write instruction A to the input / output port I do.

[0011]

As described above, the present invention has the gate circuit controlled by the control register between the internal bus and the output latch, and the data by the write-only instruction A to the input / output port is set by the control register. Since only specified bits are given to the output latch via the gate circuit,
The update of the value of the output latch by the write-only instruction A to the input / output port is only the bit specified by the control register, and the bits not specified retain the value before the execution of the write instruction A to the input / output port.

Therefore, when only a specific bit of an input / output port is operated, setting a bit to be operated in a control register in advance can be realized by executing a write instruction to the input / output port, thereby reducing software burden. This has the effect of reducing the output and increasing the output speed of the input / output port.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

[Explanation of symbols]

1 Internal bus 2 Output latch 3 Control register 4 Gate circuit 5 Output buffer 6 Input circuit 7 Input / output terminal A Input / output port write-only instruction (controlled by control register) B Input / output port write-only instruction C Input / output port read Dedicated instructions

Claims (1)

(57) [Claims] 1. An input / output terminal, an internal bus, an output latch for setting a value between the input / output terminal and the internal bus by a dedicated instruction, an output buffer for outputting the contents of the output latch, In an input / output port having an input circuit for taking the state of a terminal or the value of an output latch into the internal bus by a dedicated instruction, a control circuit, and a gate circuit controlled by the control register between the internal bus and the output latch And a dedicated instruction for setting a value in the output latch via the gate circuit.