JPH04299480A - Data latch with bit operation - Google Patents

Abstract

PURPOSE:To operate the only necessary single bit or plural bits at the same time without influencing the output of other bit by the input/output control device which outputs plural bit data from the output terminal for plural bit to outside and performs the latch control. CONSTITUTION:Regarding an output terminal A, for instance, of output terminals A-H for plural bits, a corresponding data selector 16 selects the output of a flip-flop(F/F) 14 at the time of a bit D8='0' of the bit selection instruction data from CPU 10 and the signal level for the output terminal A remains unchanged. At the time of D8='1', D0 bit of the output data from CPU 10 is selected and the value of D0 is outputted in the output terminal A as an input end D of F/F 14 becomes data D0 outputted from CPU 10. When the value of the output terminal for plural bits is changed, the value of bit in the bit selection instruction data is set so that the corresponding selector 16 may select the data outputted from CPU 10.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input/output control device that outputs multi-bit data output from a CPU, for example, to the outside from a multi-bit output terminal to control the latch output of an external device. The present invention relates to a data latch with bit manipulation that simultaneously changes only desired plural bits of bit data.

0002

2. Description of the Related Art Hitherto, there have been known input/output (I/O) control devices that perform latched output to external devices, including those using a parallel data access method and those using a bit-by-bit access method.

An I/O control device using a parallel data access method has a circuit configuration as shown in FIG.
By enabling the write signal, 8-bit output data from the PU 100 is written into the 8-bit D-type flip-flop (D-F/F) 102 at once and output from output terminals A to H. That is, (B) in FIG.
As shown in the figure, the data ports D0 to D7 of the CPU 100
There is a one-to-one correspondence between the contents of and the output data from output terminals A to H. Also, the output data of the output terminals A to H, that is, the latch data of the 8-bit D-F/F102, is
By enabling the read signal, 8 bits 3
The data is input to the data ports D0 to D7 of the CPU 100 via the state buffer 104, and the state of data output from the output terminals A to H can be monitored.

[0004] Furthermore, the I/O control device using the bit-by-bit access method has a circuit configuration as shown in FIG. It is something. That is, as shown in FIG. 4(B), by appropriately setting the contents of the data ports D1 to D3 of the CPU 106, the decoder 108 that decodes the contents is provided corresponding to each output terminal A to H. DF/F 110 is activated. These D-
Since the contents of the data port D0 of the CPU 106 are supplied to each F/F 110, the contents of the activated D-F/F 110 are rewritten to the contents of the data port D0. In addition, the data output state of the output terminals A to H is changed by enabling the read signal to transfer the latch data of each D-F/F 110 to the data ports D0 to D7 of the CPU 106 via the 8-bit 3-state buffer 104. It is now possible to monitor by inputting it to . However, unless the specification is to "invert the currently output signal level", this read circuit part is not particularly necessary.

[0005]

[Problem to be Solved by the Invention] In the above-mentioned parallel data access type I/O control device, all bits of output data are written at once, so only certain bits that are less than all bits are written. Even if you want to manipulate or change the bit, you must reset it without changing the bits that are not the target of the operation. Therefore, the CPU
100 disables interrupts to prevent access to the same I/O port during bit manipulation, and then
A series of processing steps is required, including inputting the state of the /O port, operating on specific bits of the value, re-outputting the data, and releasing the interrupt disabled state.

[0006] The external device connected to the output terminals A to H is
If you have a certain amount of time, such as an ED lamp,
These processes can be executed in sequence. However, in areas where shortening of real time is required, such as masking interrupt requests and controlling interface signals with the host, this imposes a considerable burden on software design.

Furthermore, unlike the I/O control device using the parallel data access method described above, the I/O control device using the bit-by-bit access method is capable of holding bits that are not subject to manipulation, and it is possible to hold bits that are not subject to manipulation. You can change the output state of the bit with . However, since it can only be manipulated one bit at a time, such as outputting interface signals with the host,
If a plurality of outputs need to be manipulated at the same time and the timing is specified, this method cannot be used because a time lag occurs for each bit operation. Further, even if there is no such designation, in order to change the output state of all bits, the process must be repeated for the number of bits, which increases the execution time.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a data latch with bit manipulation that allows only necessary bits to be manipulated singly or in plural at the same time without affecting other bit outputs. shall be.

[0009]

[Means for Solving the Problems] In order to achieve the above object, the data latch with bit manipulation of the present invention outputs multi-bit data output from a control means to the outside from a multi-bit output terminal. In an input/output control device that performs latch output control of a device, the control means outputs change data including latch data and selection data for each output terminal to the plurality of output terminals; , each inputs the latch data currently being output from the output terminal and the latch data of the output terminal included in the change data from the control means, and outputs the latch data of the output terminal included in the change data from the control means. a selector means for selectively outputting one of the input latch data according to the specification of selection data; and flip-flop means for maintaining the output as the output of the output terminal.

0010

[Operation] In the data latch with bit operation of the present invention, when change data including latch data and selection data for each output terminal is output from the control means to a plurality of output terminals, the selector provided for each output terminal The means selects the latch data currently being output from the output terminal and the corresponding change data included in the change data from the control means, in accordance with the designation of the selection data of the output terminal included in the change data from the control means. Either one of the latched data of the output terminal is selectively output, and the flip-flop means provided for each output terminal maintains the output of the selector means corresponding to the output terminal as the output of the output terminal. Therefore,
It becomes possible to operate only the necessary bits singly or multiple bits at the same time without affecting the output of other bits.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an input/output (I/O) control device to which a data latch with bit manipulation is applied according to an embodiment. In the figure, reference number 10 is an address signal,
CPU that outputs data, write signals, read signals, etc.
12 is an address decoder that decodes the address signal output from the CPU 10. Reference numeral 14 denotes a D-type flip-flop (F/F) that is provided corresponding to each of the output terminals A to H, and holds 1-bit data output from the output terminal. 16 is provided corresponding to each output terminal A to H, and according to a selection instruction from the CPU 10, the output data of the output terminal and the CPU
10 to the corresponding F/F.
This is a data selector that selectively outputs data to 14. In addition,
18 and 20 are AND gates, and 22 is an 8-bit 3-state buffer.

Data D0 to D output from the CPU 10
15, as shown in FIG. 2(A), data D0 to D7
as 8-bit data to be output to output terminals A to H, and data D8 to D15 to each data selector 16.
It is used as bit selection instruction data for. That is, the data D0 and D8 are supplied to the data selector 16 corresponding to the output terminal A, and the data D1 and D8 are supplied to the data selector 16 corresponding to the output terminal A.
9 is supplied to the data selector 16 corresponding to the output terminal B, and data D7 and D15 are supplied to the data selector 16 corresponding to the output terminal H. Here, when the bit selection instruction data is "0", the selector 16 selects and outputs the data held in the corresponding F/F 14, that is, the output data of the output terminal, and when it is "1",
It is configured to selectively output output data given from the CPU 10.

Note that if the read circuit part in FIG. 1 is not designed to "invert the currently output signal level,"
Not particularly necessary.

The operation in such a configuration will be explained below. Generally, when writing data to an I/O port or memory, the CPU 10 first outputs an address, then outputs data, and enables a write signal, as shown in FIG. 2(B).

That is, since a plurality of various devices such as memories and I/O ports are connected to the CPU 10, the output terminals A to H of the target I/O port operate only when a specific address is output. Decode the address as follows. In this embodiment, the output of the address decoder 12 and the C
The output of the AND gate (negative logic in FIG. 1) 18 that performs AND with the write signal output from the PU 10 is sent to each F/F1.
This is realized by applying it to the clock input terminal CK of No. 4.

The data input terminal D of each F/F 14 is connected to the selection output terminal Y of the corresponding data selector 16. Each data selector 16 is selected by bit selection instruction data from the CPU 10. Hereinafter, output terminal A will be explained as a representative. The other terminals B to H will be self-explanatory from this description.

That is, the data selector 16
It is selected by the D8 bit of the bit selection instruction data from the input terminal A, that is, F/F when D8="0"
Select the output of 14, and when D8="1", input terminal B
That is, the D0 bit of the output data from the CPU 10 is selected. If a negative pulse occurs at the clock input terminal CK of the F/F 14 when D8="0", that is, the CPU 10
When the output terminal A is write-accessed with 8="0", the F/F 14 outputs the signal level currently being output, so the signal level of the output terminal A does not change. Also,
When D8="1", the input terminal D of F/F14 is connected to CPU1.
0 becomes the output data D0, so output terminal A has D
A value of 0 is output (F/F 14 latches the value of D0).

As described above, in the example of FIG. 1, since there are eight similar circuits, it is possible to select any number of bits up to eight bits (A to H) and change the terminal level. For example, if "0" is currently being output from all of the output terminals A to H and it is desired to output "1" from only the output terminals A, B, and F, the CPU 10 will perform the operations shown in FIG. 2(C). You can output data like this.

[0019] In this way, only the necessary bits can be operated singly or in plural at the same time without affecting the output of other bits.

[0020]

[Effects of the Invention] As detailed above, according to the present invention,
It is possible to provide a data latch with bit manipulation that allows only necessary bits to be manipulated singly or in plural at the same time without affecting other bit outputs.

[0021] Therefore, when operating only a specific bit that is less than all bits of the latch output I/O, it is possible to do so with a single output command without affecting bits that are not subject to operation.
The burden on software is reduced. Additionally, since multiple bits can be specified simultaneously, no time lag occurs. Therefore, the data latch with bit manipulation of the present invention is effective even when shortening the execution time is required or when it is necessary to manipulate multiple outputs simultaneously and the timing is specified. be.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an input/output control device to which a data latch with bit manipulation according to an embodiment is applied.

[Figure 2] (A) is a diagram showing the contents of the data port of the CPU, (B) is a timing chart when accessing the I/O port, and (C) is a diagram showing the operation of multiple bits of the CPU.
FIG. 2 is a diagram showing the contents of a data port.

FIG. 3(A) is a circuit configuration diagram of a conventional parallel data access type input/output control device, and FIG. 3(B) is a diagram showing the contents of a data port of a CPU.

FIG. 4(A) is a circuit configuration diagram of a conventional input/output control device using a bit-by-bit access method, and FIG. 4(B) is a diagram showing the contents of a data port of a CPU.

[Explanation of symbols]

10...CPU, 12...Address decoder, 14...Flip-flop, 16...Data selector, 18, 20...AND gate, 22...8-bit 3-state buffer, A to H
...Output terminal.

Claims (1)

[Claims] Claim 1. An input/output control device that outputs multi-bit data output from a control means to the outside from a multi-bit output terminal to control latch output of an external device, comprising:
the control means for outputting change data including latch data and selection data for each output terminal of each bit to the plurality of output terminals; data and the latch data of the output terminal included in the change data from the control means are input, and the input latch data is a selector means for selectively outputting one of the output terminals; and a flip-flop means provided for each output terminal and maintaining the output of the selector means corresponding to the output terminal as the output of the output terminal. A data latch with bit operation.