JPH02183874A - Depicting circuit - Google Patents

Abstract

PURPOSE:To attain high speed depicting with simple hardware by outputting a read signal to a frame buffer and controlling the switching of a latch circuit and first and second gates when data are all bits writing designated from a register. CONSTITUTION:A control circuit 8 judges it according to a signal from an OR circuit 10 whether the data are the all bits writing or not. Then, a ready signal line 3 to a CPU is made inactive and simultaneously, the read signal is outputted to a frame buffer 9. Gates 21-29 and 31-39 are controlled according to the contents of a register 5. On a data line to the frame buffer 9, writing data are sent from the CPU to the bit in a writing area X and data are sent from a latch 6 to the bit excepting for the writing area X. At such a time, the control circuit 8 outputs a write signal to the frame buffer 9 and writes the depicted data. Simultaneously, the ready signal line 3 to the CPU is made active. Thus, the processing of read-modify-write can be executed at high speed by the simple hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a drawing circuit that performs drawing by writing data to a drawing frame buffer.

[Conventional technology]

Conventionally, this type of drawing circuit consists of a drawing frame buffer simply using a semiconductor memory.
When writing data to a part of a certain address in a semiconductor memory, software must be used to read, change, and write the data at the address to be written.

In addition, when performing this with hardware, a dedicated brafix controller or the like is used.

Figures 2 (a) to (c) show data array diagrams at the time of drawing,
FIG. 3 is a flow diagram showing the drawing process when data is written using software.

First, in step 101, it is calculated in which bit of the address of the drawing frame buffer data should be written. In the next step 102, write data is calculated and obtained. It is assumed that the data obtained here is shown in FIG. 2(b), and that the writing area X is obtained in the process of step 101. In the software, step 103
Then, it is determined whether the write area X shown in FIG. 2(b) is for all bits or not. If it is for all bits, data may simply be written in step 106. If not all bits are present, the data at the address to be written is read once in step 104, changed in step 105, and written in step 106. Figure 2(a) shows the data read from the address to be written, and the second
Figure (C) shows the data after the change. Read/modify the cycle of steps 104 to 106 of this flow.
It's called light.

[Problem to be solved by the invention]

The above-mentioned conventional drawing circuit has the disadvantage that it cannot be made faster because the data to be written is checked by software when writing drawing data, and it is not possible to increase the speed when writing drawing data. The drawback was that it was expensive.

An object of the present invention is to provide a drawing circuit that eliminates these drawbacks and enables high-speed drawing by adding very simple hardware.

[Means to solve the problem]

The present invention provides a drawing circuit that performs drawing by writing data to a drawing frame buffer made of a semiconductor memory, including: a latch circuit that holds data at a specified address of the semiconductor memory to be written; a register that holds data for specifying a write area on the side where the drawing data is written, and first and second registers that control the drawing data and the output data of the latch circuit, respectively, by the output and inverted output of this register. When the specified data from the gate and the register is all-bit writing, a read signal is output to the frame buffer, and the latch circuit and the first . and a control circuit that switches and controls the second gate.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. This embodiment includes a frame buffer 9 made of a semiconductor memory, registers for storing data to be written in write area X, and frame buffer 9 for storing data other than write area X.
A latch 6 for reading data from and storing it, and a control circuit 8
and OR circuit 10. Inverters 11, 12. gate 21
~29. Consisting of 31~39.

When the CPU needs to write data to the frame buffer 9 for drawing, the software calculates the write bits and write data (step 101 in FIG. 3).
102 processing). The CPU sends data specifying write bits to the data line 4A and write data to the data line 4B. The write bit designation data sets the write area Send. Register 5 stores write pin I/designated data.

The control circuit 8 is connected to the frame buffer 9 from the CPU.
When a write signal is received, it is determined whether all bits have been written based on the signal from the OR circuit 10, and the ready signal line 3 is sent to the CPU.
At the same time as inactivating frame buffer 9
A read signal is output from the read/write control line 7. Since the data to be written is read from the frame buffer 9, the gate 31 and the latch 6 are controlled, and the signal read from the frame buffer 9 is stored in the latch circuit 6. Gates 21 to 29 and 31 to 39 are controlled by the contents of register 5, so on the data line to frame buffer 9, bits in write area X receive write data from the CPU, and bits other than write area X receive latched data. Data from 6 is sent out. At this time, the control circuit 8 outputs a write signal to the frame buffer 9, and at the same time writes the drawing data, the CPU sends a write signal 3.
Activate and end the write cycle.

Furthermore, in the case of all-bit writing, the control signal 8 controls each control line to execute a normal memory write cycle.

〔Effect of the invention〕

As explained above, the present invention improves read and write operations that were previously performed using software or dedicated LSI when writing to a frame buffer.
This has the effect of increasing the speed of modify write processing by simply adding hardware. Further, since read/modify/write can be performed by simply writing when writing to the frame buffer, there is an effect that the software becomes simpler when processing is performed by software.

This is a diagram.

1... Address line, 2, 7... Read/write control line, 3... Ready signal, 4A, 4B... Data line,
5...Register, 6...Latch circuit, 8...Control circuit, 9...Frame buffer, 10...
OR circuit, 11.12...inverter, 21-29.
31-39...Gate circuit.

Claims (1)

[Claims] A drawing circuit that performs drawing by writing data to a drawing frame buffer consisting of a semiconductor memory includes a latch circuit that holds data at a specified address of the semiconductor memory on the writing side, and a latch circuit to which the drawing data is written. a register that holds data for specifying a writing area on the side; first and second gates that respectively control the drawing data and the output data of the latch circuit by the output and inverted output of this register; A drawing characterized in that it includes a control circuit that outputs a read signal to the frame buffer and switches and controls the latch circuit and the first and second gates when the specified data from the register is all-bit writing. circuit.