JP2577071B2 - Digital signal processor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor that executes arithmetic processing on a signal sequence heavily.

[Conventional technology]

FIG. 7 shows, for example, P401 “A50NS FLOATING-POINT SIGN”, Proceedings of the International Conference on Sound, Speech and Signal Processing 1986 (ICASSP86).
FIG. 2 is a simplified block diagram showing a configuration of a digital signal processing processor described in "AL PROCESSOR VLSI", where (1) is an instruction memory for storing instruction words, and (2) is a command memory for decoding and calculating instruction words. An instruction execution control unit for performing operation control; (3) a data input bus for interconnecting the following units to perform heavy data transfer; (4) an internal data memory for storing operation data; and (5) a data input bus Bus (3)
(6) is an address generator capable of simultaneously generating up to three addresses, and (7) is read / output to an external data memory (not shown). An external data memory connection unit for controlling writing, (8) an external address bus, (9) an external data bus, (10) an external device control signal bus, and (11) an external device (not shown). Serial port (hereinafter abbreviated as SIO) to execute serial transfer with (12) SIO
A DMA control unit (hereinafter, referred to as DMAC) that directly controls data memory transfer (hereinafter, abbreviated as DMA) between (11) and the external data memory connection unit (7).

FIG. 8 is a diagram showing an external data memory access timing of the digital signal processor shown in FIG. 7, FIG. 8 (a) is a read timing diagram, and FIG. 8 (b) is a write timing diagram. . FIG. 8 (a),
In (b), (901) is an external address terminal, (902)
Is a strobe signal for controlling read timing from the external data memory, (903) is an external data terminal, and (904) is a strobe signal for controlling write timing to the external data memory.

Next, the operation will be described. First, in FIG.
The instruction word at the designated address is read from the instruction memory (1) and input to the instruction execution control unit (2) via the input / output path (501). The control signal and data decoded by the instruction execution control unit (2) are sent to a data input bus (3) via an output path (502).

By this control signal, the operation data from the internal data memory (4) to the data input bus (3) is transferred to the output path (503).
Via the data input bus (3) to the operation unit (5)
From the data bus (3) via the output path (504), and outputs the data from the data bus (3) via the output path (505) to the data input bus (3). Output data to the data memory (4) in the path (506)
Various operations such as writing and external data memory access are controlled via the.

The address of the input data from the internal data memory (4) to the arithmetic unit (5) and the write destination address of the output data from the arithmetic unit (5) to the internal data memory (4) are determined by using three address generators. It is controlled by the address generation unit (6). The address generator (6) generates an address based on readable / writable data input from the data bus (3) via the input / output path (510), and outputs the address via output paths (508) and (509). The control of the internal data memory (4) and the control of the external data memory connection section (7) are performed by the data, and the input data and the output data write destination to the arithmetic section (5) are determined.

On the other hand, the data bus (3) is assigned to a specific register of the DMAC (12).
When data is set via a route not shown, DM
A is started.

When the DMA is started, all operations other than those involved in the DMA transfer are stopped, and the data is transferred from the SIO (11) to the external data memory connection unit (7) via the output path (515) and the data input bus (3). The transfer is performed. The number of words to be transferred is determined by the DMAC (12) according to the instruction output via the output path (501) in advance.
Set in a specific register. The number of transfer words that can be set is
Only 64,128,256,512 words can be selected.

Next, FIG. 8 will be described. When reading the external data memory shown in FIG. 8 (a), the RE terminal of the external device control signal bus (10) becomes active for one machine cycle, and the strobe signal (902) notifies the external device of data reading. And external address bus (8)
Output address data for one machine cycle, and read data from an external device is taken in at the trailing edge of the same cycle.

When writing to the external data memory shown in FIG. 8 (b), the WE terminal of the external device control signal bus (10) becomes active for one machine cycle, thereby notifying the external device of the data write and the external address bus. (8)
And write data from the external data bus (9) are output for one machine cycle.

[Problems to be solved by the invention]

Since the conventional digital signal processor is configured as described above, there are the following problems.

a) Since the data cannot be directly transferred between the internal data memory and the external data memory, the processing efficiency of the internal operation is reduced.

b) When the external data memory is accessed by direct data transfer, the address of the external data memory is in a simple ascending order, and the number of words to be transferred cannot be arbitrarily specified. Therefore, it is difficult to directly transfer the two-dimensional block data. .

c) When direct data transfer is performed, the internal operation of the processor is stopped, so that the processing efficiency of the internal operation is extremely reduced.

d) Since the external address output is fixed to 12 bits, the access area of the external data memory is narrow.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described conventional problems, and an object of the present invention is to provide a high-speed digital signal processor having a high flexibility and a simple device configuration.

[Means for solving the problem]

A digital signal processor according to the present invention includes: an internal data memory for storing operation data; an operation unit for performing an operation on the operation data; and an operation unit for outputting the operation data output from two output paths of the internal data memory. A plurality of data input buses for transferring the operation result to the operation unit; a data output bus for transferring the operation result output from the operation unit to an input path of the internal data memory; and a data output from the data output bus to an external data memory An external data memory connection unit for inputting data from an external data memory to the data input bus, and a separate direct data transfer input and output path between the external data memory connection unit and the input path and output path of the internal data memory. Connected to the output path and a direct data transfer bus separate from the data input bus and data output bus. A direct data memory transfer control unit for controlling the external data memory connection unit so as to perform direct data transfer between the internal data memory and an external data memory by the direct data transfer bus; Is the start address of the area in the internal data memory where direct data memory transfer is performed,
A transfer parameter setting unit for setting a head address, a block horizontal size, and the number of words of a two-dimensional block for performing direct data memory transfer in the external data memory;
A direct data memory transfer address calculator for calculating a transfer data address in the internal data memory and an address of each word of the two-dimensional block in the external data memory based on each parameter set by the transfer parameter setting unit. It was done.

[Action]

The digital signal processor according to the present invention comprises:
The upper address and lower address can be output from the address terminals in the external data memory connection unit over two machine cycles, and the direct data memory transfer control unit has a DMA bus to perform internal calculation of two-dimensional block transfer. Without sacrificing efficiency. Also, by having the mode register and the direct data memory control register, the external address output method and the connection memory in the program and direct data memory transfer can be set independently. Enables access to large areas.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram schematically showing a digital signal processor according to the present invention. The same or corresponding parts as those in FIG. 7 are denoted by the same reference numerals, and redundant description is omitted.

In FIG. 1, (13) is a mode register for setting an access method of the external data memory, (101) is a data output bus for outputting an operation result, and (102) is a direct data transfer bus.

(511) is a data input / output path from the data input bus (3) to the mode register (13), (512) is a control signal output path from the mode register (13) to the external data memory connection unit (7), An input / output path (604) as a direct data transfer input / output path for directly transferring data between the direct data memory transfer bus (102) and the internal data memory (4) is connected to the direct data memory transfer bus (102). Data input / output path between the external data memory connection (7), (60
5) is a data output path from the data output bus (101) to the external data memory connection section (7).

FIG. 2 is a block diagram showing a configuration example of the DMAC (12) in FIG. 1. In FIG. 2, a frame horizontal size register (dmfh) indicating the horizontal size of the two-dimensional address space is shown.
r) and (202) are block horizontal size registers (dmbhr) indicating the horizontal size of the rectangular portion in the two-dimensional address space;
(203) is a block start address register (dmbsr) indicating the start address of the external data memory for performing DMA transfer, (2)
04) is the internal memory start address register (dmssr) that indicates the start address of the internal data memory for DAM transfer, (2)
05) is a word register (dmwc) indicating the number of DMA transfer words
r) and (206) are DMAC registers (dmcr) for performing an external address output method in DMA transfer, selection of an external memory, and the like.
(207) is the external data memory address calculation unit, (208) is
A DMA transfer control unit that controls DMA transfer.

(701) is the input / output path of the frame horizontal size register (201), (702) is the block horizontal size register (202)
(703) is an input / output path of the block start address register (203), (704) is an input / output path of the internal memory start address register (204), and (705) is an input / output of the word register (205). A path (706) is an input / output path of the DMAC register (206).

(707) is an output path of the internal data memory address of the DMA transfer from the DMA address calculation unit (207), (708) is an output path of the external data memory address of the DMA transfer from the DMA address calculation unit (207), and (709) ) Is the DMA transfer control unit (208)
This is an output path for outputting a control signal such as the number of DMA transfer words to the DMA address calculation unit (207).

FIG. 3 is a diagram showing an example of a transfer area between the internal data memory (4) and the external data memory (14) in the DMA transfer performed by the DMAC of FIG.

FIG. 4 shows the mode register (13) of FIG.
FIG. 4 is a diagram showing a bit configuration of a DMAC register (206);
In FIG. 4, A is a spare bit, B is the first bit in the address output mode, and C is the 0th bit in the memory connection mode.

FIG. 5 is a diagram showing an example of timing when an external data memory access is made from a program and a DMA.

Next, the operation will be described. The command word read from the command memory (1) is input to the command execution control unit (2) via the input / output path (501), and the control signal decoded by the command execution control unit (2) causes The operation data from the internal data memory (4) to the data input bus (3) is read out via the output path (503), and the data from the data input bus (3) is output to the operation unit (5) via the output path (504). Through the input and the operation processing result in the operation unit (5), the output path (50
5) to the data output bus (101), and the output path (5) from the data output bus (101) to the internal data memory (4).
06) Data writing via the data output bus (101)
Output path (605) to the external data memory connection (7)
Various operations such as data writing are controlled via the.

The address of the input data input from the internal data memory (4) to the arithmetic unit (5) via the output path (504) and from the arithmetic unit (5) to the data output bus (101) via the output path (505) The write destination address of the output data to be output to the internal data memory (4) is controlled by an address generation unit (6) having three types of address generators.

The address generation unit (6) generates an address based on readable / writable data supplied from the data input bus (3) via the input / output path (510), and outputs the output path (50).
8) control of the internal data memory (4) and control of the external data memory connection unit (7) by the data output through (509), and writing of input data and output data to the arithmetic unit (5) Decide ahead.

The external data memory (not shown) is accessed by the external data memory connection unit (7) in accordance with an instruction word read from the instruction memory (1) to the mode register (13) via the data input bus (3). Determined by the set value.

On the other hand, when data is set in a specific register of the DMAC (12) via the data input bus (3) by the above-mentioned instruction word, DMA transfer is started. When the DMA transfer is started, the external data memory connection (7) is controlled by the DMAC (12) via the output path (507) independently of the internal operation, and the internal data memory (4) and the external data memory (7) are controlled. Between the input and output paths (603) and (604) and the direct data transfer bus (10
Perform data transfer via 2).

The DMA transfer control unit (208) uses the data set in the DMA address calculation unit (207) through the data input bus (3).
The DMA address calculation unit (207) starts the DMA transfer, and the DMA address calculation unit (207) uses the values of the frame horizontal size register (201), block horizontal size register (202), block start address register (203), and internal memory start register (204). A two-dimensional block address (708) is generated for an address of an external data memory (not shown), and an ascending one-dimensional address (707) is generated for an address of the internal data memory (4).

In the DMA transfer control unit (208), the word register (20
When the number of DMA transfer words set in 5) ends, the end is notified to the DMA address calculation unit (207).

As shown in FIG. 3, the DMA transfer starts at an arbitrary address (in FIG. 3, address S) of the internal data memory (4).
From an arbitrary address (address t in FIG. 3) of an external data memory (not shown) to an arbitrary rectangular area (k rows × l in FIG. 3)
Column).

As shown in FIG. 4, the mode register (13) and the DMAC
When the bit indicating the memory connection mode of both the register (206) is “0”, the mode waits until the read / write completion signal from the external device is detected when the low-speed memory is used. When the indicated bit is "1", the read / write mode is completed in one machine cycle after the lower address is output.

When the bit indicating the address output mode is "0", the upper and lower bits of the address are output over two machine cycles, and when the bit is "1", the lower bit of the address is output only for one machine cycle.

By independently setting the mode register (13) and the DMAC register (206), the external memory access from the program and the DAM can be performed independently.

FIG. 5 shows the mode register (1) shown in FIG.
3) External data memory when the address output mode is set to “1”, the memory connection mode is set to “1”, the address output mode of the DMAC register (206) is set to “0”, and the memory connection mode is set to “0”. (Not shown).

The access of the external data memory (not shown) from the DMA is completed by detecting the read / write completion signal from the external device using the low-speed memory (n 'machine cycle in FIG. 5), and the external data memory from the program is used. Access is performed in one machine cycle using a high-speed memory, and the / write operation is completed.

The external data memory access by the DMA is continuously performed unless the external data memory access from the program is performed. When the external data memory access is performed from the program, the access from the DMA is interrupted and resumed after the access from the program is completed.

FIG. 6 is an external data memory access timing (reading) at the external data memory connection part (7) in FIG.
The same or corresponding parts as those in FIG. 8 are denoted by the same reference numerals, and redundant description is omitted.

In FIG. 6, (301) is a signal for controlling an upper address timing when outputting an address (hereinafter abbreviated as AHE), and (302) is a signal for controlling a lower address timing when outputting an address (hereinafter referred to as ALE). (Abbreviated), (303)
Is a signal that notifies the external device whether the external data memory access is a processor or DMA (hereinafter abbreviated as P / D),
(304) is an external read / write completion signal (hereinafter D
TACK).

When the high-speed memory shown in FIG. 6A is used, AHE (301) is asserted in the first machine cycle, the upper address is output from the external address terminal (901) of the address bus (8), and ALE is issued in the second machine cycle. (302) and RE
(902) is asserted, and data is taken in from the external data terminal (903) of the external data memory at the trailing edge of the second machine cycle.

When the low-speed memory shown in FIG. 6 (b) is used, AHE (301) is asserted in the first machine cycle, the upper address is output from the external address terminal (901) of the address bus (8), and ALE is issued in the second machine cycle. (302) and RE
(902) is asserted, RE (902) is negated at the trailing edge of the cycle in which the external device asserts DTACK (304), and data is fetched from the external data terminal (903) of the external data memory (not shown). And then DTACK
ALE (302) at trailing edge of negated cycle (304)
To negate.

As described above, the external data memory connection section (7) has the following two methods: (a) an address output method to the external data memory of two methods, and one of the two methods outputs the upper and lower addresses of the address over two machine cycles, and Of the external data memory area (not shown) can be accessed at a high speed by outputting only the lower part of the address in one machine cycle. Switching is performed by a mode register value set by an instruction.

(B) Two types of external data memories (not shown) can be connected, and one of them is output after the lower address is output.
A high-speed memory that completes read / write in a machine cycle, and a low-speed memory that waits until an external read / write completion signal is detected, and switches between the two modes by the value of the mode register. I do.

Further, the direct data memory transfer unit (c) uses the direct memory control register set by the instruction, independently of the external data memory access by the internal instruction based on the value of the mode register, and the address output method of the two methods. It is characterized in that connection of an external data memory of the system is possible.

(D) An address instruction to the external data memory connection part is sequentially given by a k-row × l-column (k, l is an integer) rectangular portion in an m-row × n-column (m, n is a positive integer) two-dimensional address space. Instructing the address to the internal data memory from an arbitrary start address in ascending order, and performing two-dimensional data transfer between the external data memory and the internal data memory; and starting the data transfer. In this case, the transfer direction and the number of transfer data are designated by an instruction, so that data input / output to / from an external data memory and internal arithmetic processing are performed in parallel in units of the k-row × l-column rectangular block.

In the above embodiment, the number of external address terminals is 16 bits.
However, other numbers of terminals may be used.

Further, it is apparent that the detailed specifications of the above embodiment are not related to the essence of the present invention and do not limit the content of the present invention.

〔The invention's effect〕

As described above, according to the present invention, the direct data transfer input / output path for performing the direct data transfer in the internal data memory and the direct data transfer bus connected thereto are provided, and the two-dimensional block is provided in the DMA control unit. Since data is generated, it is possible to transfer data in a rectangular area between the internal data memory and the external data memory without lowering the processing efficiency of the internal operation. Also, by outputting the address over two cycles,
It is possible to expand the data memory area due to the limitation of the number of external terminals. In addition, since the high-speed memory and the low-speed memory can be connected to the external data memory,
There are effects such as that the flexibility of the signal processor can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital signal processor according to one embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a direct data transfer control unit in FIG. 1, and FIG.
FIG. 4 is a diagram showing an example of a transfer area between an internal data memory and an external data memory for DMA transfer, FIG. 4 is a diagram showing a processor and an example of a register configuration for setting an external data memory access method for direct data transfer, and FIG. FIG. 6 is a timing diagram when an external data memory is accessed from a program and direct data transfer, FIG. 6 is an external data memory access timing diagram at an external data memory connection portion in FIG. 1,
FIG. 7 is a block diagram showing the configuration of a conventional digital signal processor, and FIG. 8 is an external data memory access timing diagram of the conventional processor. In the figure, (1) is an instruction memory, (2) is an instruction execution control unit, (3) is a data input bus, (4) is an internal data memory, (5) is an operation unit, (6) is an address generation unit,
(7) is an external data memory connection unit, (12) is a direct data memory transfer control unit (DMAC), (13) is a mode register,
(101) is a data output bus, and (102) is a direct data transfer bus. In the drawings, the same reference numerals indicate the same or corresponding parts.

Continuation of the front page (56) References JP-A-59-177631 (JP, A) JP-A-62-152061 (JP, A) JP-A-61-208537 (JP, A) "Interface" Vol. 13, No. 11 (November 1987; CQ Publishing Co., Ltd.) PP. 300-313 "Interface" Vol. 10, No. 12 (December 1984; CQ Publishing Co., Ltd.) PP. 252-261

Claims (1)

(57) [Claims] 1. An internal data memory for storing operation data, an operation unit for performing an operation on the operation data stored in the internal data memory, and an output from two output paths of the internal data memory. A plurality of data input buses for transferring operation data to the operation unit; a data output bus for transferring operation results output from the operation unit to an input path of the internal data memory; and an external data memory from the data output bus An external data memory connecting portion for outputting data to the external data memory and inputting data from an external data memory to the data input bus; and separates the input path and the output path of the external data memory connecting portion and the internal data memory. Connect the direct data transfer input / output path and the direct data transfer bus separate from the data input bus and data output bus. And a direct data memory transfer control unit for controlling the external data memory connection unit so as to perform direct data transfer between the internal data memory and the external data memory by the direct data transfer bus. The control unit is configured to set a start address of a region in the internal data memory for direct data transfer, a start address of a two-dimensional block for direct data transfer in the external data memory, a block horizontal size, and a transfer parameter for setting the number of words. A setting unit; and a direct data memory transfer address calculation for calculating a transfer data address in the internal data memory and an address of each word of the two-dimensional block in the external data memory based on each parameter set by the transfer parameter setting unit. Part and Digital signal processor which in accordance with an address serial direct data memory transfer control unit generates and performing direct data memory transfer of a two-dimensional block data.