JPH0553976A - Inter-computer parallel data transfer method and bus adapter - Google Patents

Abstract

PURPOSE:To simplify configuration concerning the inter-computer parallel data transfer method and the bus adapter. CONSTITUTION:This is equipped with a host side control circuit 22, r/w (read/ write) flag 20F, address buffer register 20A, data write buffer register 20W, data read buffer register 20R and slave side control circuit 24. Corresponding to the contents of the r/w flag 20F, the data of addresses held in the register 20A of a buffer RAM 12a are read out and held in the register 20R or the contents of the register 20W are read out and stored in the address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer-to-computer parallel data transfer method for transferring parallel data between a high-order computer and a low-order computer, and a bus adapter for connecting the two computers for this transfer.

[0002]

2. Description of the Related Art In a bus adapter of this type, a parallel interface board, for example, a GP-IB interface board, is provided in each of a high-order computer and a low-order computer having different processing speeds, and the boards are connected by a cable. The configuration is complicated.

[0003]

SUMMARY OF THE INVENTION An object of the present invention is to provide a parallel data transfer method between computers capable of simplifying the hardware configuration and a bus adapter having a simple configuration.

[0004]

FIG. 1 is a flow chart showing the principle configuration of an inter-computer parallel data transfer method according to the present invention. This method has the following steps 1 to 7.

(1, 2) An interrupt request signal rqirt is supplied to the lower computer based on the data on the address bus of the upper computer.

(3) The read / write signal r / w from the host computer, the address hadr on the address bus of the host computer, and the data on the data bus are held in the buffer storage means.

(4) In response to the interrupt request signal rqirt, the lower computer executes the following step 5 when the read / write signal r / w held in the buffer storage means indicates read. If the read / write signal r / w held in the buffer storage means represents a write, the following step 6 is executed.

(5) The data held at the address A'corresponding to the address A held in the buffer storage means of the lower computer is transferred to the higher computer via the buffer storage means. Addresses A and A '
The relationship is, for example, A ′ = A, A ′ = (indirect address of address A) or A ′ = A + (base address).

(6) At the address corresponding to the address held in the buffer storage means of the lower computer,
The data held in the buffer storage means is transferred.

(7) After the data transfer is completed, a data transfer completion signal is sent from the lower computer to the upper computer.

This method can be implemented by using the bus adapter according to the present invention, and the bus adapter will be described with reference to the reference numerals of the corresponding components in FIG. 2 of the embodiment.

The bus adapter includes an upper control circuit 22 and
Read / write storage element 20F and address storage means 20
A, a data storage means 20W, 20R, and a lower-order side control circuit 24 are provided and have a relatively simple configuration.

The upper control circuit 22 supplies the interrupt request signal rqirt to the lower computer 12 based on the data on the address bus 18A of the lower computer 12, and outputs the upper timing signal wtrg *.
Data on the address bus 18A of the lower computer 12 and a data read signal d from the lower computer 12
The output control signal rcrl * is output based on oe *.

The read / write storage element 20F responds to the upper timing signal wtrg * and the upper computer 1
The read / write signal r / w from 0 is held.

The address storage means 20A holds the data on the address bus 16A of the host computer 10 in response to the host timing signal wtrg *.

The data storage means 20W holds the data on the data bus 16D of the host computer 10 in response to the host timing signal wtrg *, and the data storage means 2
The 0R outputs the stored contents onto the data bus 16D of the host computer 10 in response to the output control signal rcrl *.

The lower control circuit 24 is based on a signal output by the lower computer 12 executing interrupt processing in response to the interrupt request signal rqirt.
Lower side timing signals rdst *, aoe *, doe
*, Dwps *, wcrl * are generated, the contents of the read / write storage element 20F and the address storage means 20A are read out according to these generated signals, and the lower computer 1
2 to read the contents of the data storage means 20W and supply it to the lower computer 12 or the lower computer 1
2 is read out and stored in the data storage means 20R, and after the data transfer is completed, the data transfer end signal wcr
l * is supplied to the host computer 10.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

(1) First Embodiment FIG. 2 is a block diagram of the bus adapter of the first embodiment.

Host computer 10 having different processing speed and the like
In order to transfer parallel data between the computer and the subordinate computer 12, a bus adapter 14 is connected between the two.

The bus 16 of the host computer 10 comprises an address bus 16A, a data bus 16D, and a control bus. The control bus is a control line 161 for sending a read / write signal r / w and a weight control signal wcrl. It includes a control line 162 for receiving * (* indicates negative logic, and so on). on the other hand,
The bus 18 of the lower computer 12 is the address bus 18
A, a data bus 18D, and a control bus. The control bus is MPU (MPU is DS
P, an image processor, etc.) includes a control line 181 for receiving the interrupt request signal rqirt.

The address bus 16A is connected to the input terminals of the address buffer register 20A and the upper control circuit 22, and the data bus 16D is connected to the input terminal of the data write buffer register 20W and the output terminal of the data read buffer register 20R. ing. The data bus 18D is connected to the output terminal of the address buffer register 20A, the output terminal of the data write buffer register 20W and the input terminal of the data read buffer register 20R, and the address bus 18A is connected to the lower control circuit 24.
Connected to the input terminal of.

The control line 161 is connected to the input terminal of the r / w flag 20F, and the output terminal of the r / w flag 20F is connected to, for example, the 0th bit data line of the data bus 18D. The control line 181 is connected to the output terminal of the upper control circuit 22, and the control line 162 is connected to the lower control circuit 2.
4 is connected to the output terminal.

Latch signal wtr from the upper control circuit 22
The control line 261 for taking out g * is the r / w flag 2
0F, the address buffer register 20A and the data write buffer register 20W are connected to the clock input terminals. Output control signal rcr from upper control circuit 22
The control line 262 for taking out l * is connected to the output enable terminal of the data read buffer register 20R. From the lower control circuit 24, a flag read signal rdst *, an address read signal aoe *, a data read signal doe *, and a data write pulse dwps.
Control lines 281 to 284 for extracting * are r / w flag 20F and address buffer register 20A, respectively.
And output enable terminal of the data write buffer register 20W and the data read buffer register 20R
Is connected to the clock input terminal of.

As described above, the structure of the bus adapter 14 is considerably simpler than the conventional one. Next, the operation of the system connected as described above will be described.

Data transfer between the high-order computer 10 and the low-order computer 12 is performed based on an interrupt request signal from the high-order computer 10 to the low-order computer 12. When data is transferred from the upper computer 10 to the lower computer 12, the data is written from the upper computer 10 to the buffer RAM 12a of the lower computer 12 via the data write buffer register 20W. Lower computer 12 to higher computer 1
Data transfer to 0 is performed from the buffer RAM 12a via the data read buffer register 20R.

The host computer 10 is a buffer RAM
When a data write command to 12a is executed, as shown in FIG.
As shown in (C), the read / write signal r / w becomes low level, and when the data read command from the buffer RAM 12a is executed, the read / write signal r / w becomes high level as shown in FIG. 5 (C). The upper control circuit 22 is
A change in the address hadr shown in FIG. 4 (A) or FIG. 5 (A) is detected to generate a latch signal wtrg * as shown in FIG. 4 (D) or FIG. 5 (D), which is r / w. Flag 2
0F, the address buffer register 20A and the data write buffer register 20W are supplied to the clock input terminals, and the read / write signal r / w, the address hadr, and the data hdata are respectively supplied to the r / w flag 20F, the address buffer register 20A, and the data write buffer register. Hold at 20W. When the upper control circuit 22 determines that the address hadr specifies the address of the buffer RAM 12a, it supplies the interrupt request signal rqirt as shown in FIG. 4E or 5E to the MPU of the lower computer 12. To do. In addition, the upper control circuit 2
2 supplies the output control signal rcrl * to the output enable terminal of the data read buffer register 20 when the data is read from the lower computer 12 (when the data read signal doe * is asserted (valid)). Then, the contents of the data read buffer register 20 are taken out onto the data bus 16D.

The lower computer 12 responds to the interrupt request signal rqirt to perform the interrupt processing as shown in FIG. Hereinafter, the numerical value in the parentheses indicates the step identification number in the figure.

(30) First, normal interrupt preprocessing such as register content saving is executed.

Next, an instruction to load the contents of the r / w flag 20F into the register A is executed. As a result, the lower control circuit 24 decodes the address based on the data on the address bus 18A (that is, the same applies below), asserts the read signal rdst *, and sets the r / w flag 20.
The contents of F are read onto the data bus 18D. The read data is loaded into the register A of the MPU of the lower computer 12.

Next, an instruction to load the contents of the address buffer register 20A into the register B is executed. As a result, the lower control circuit 24 asserts the address read signal aoe * as shown in FIG. 4 (F) or FIG. 5 (F) based on the data on the address bus 18A, and sets the contents of the address buffer register 20A. Read on the data bus 18D. The read data mdata is loaded into the register B of the MPU of the lower computer 12.

(31) The 0th bit of register A is "1"
Is executed, the process branches to step 32 if it is '0', and step 3 if it is '1'.
Branch to 3.

(32) Data write buffer register 2
An instruction to move the contents of 0W to the address of the contents of the register B in the buffer RAM 12a is executed. As a result, the lower control circuit 24 asserts the data read signal doe * as shown in FIG. 5 (G) based on the data on the address bus 18A to transfer the contents of the data write buffer register 20W onto the data bus 18D. Read. The read data is stored in the address of the buffer RAM 12a.

Next, after executing a normal post-interruption process such as restoration of register contents, the interrupt process is terminated.

The lower side control circuit 24 negates (invalidates) this data read signal doe *, and then, FIG.
Weight control signal wcrl as shown in (H)
* Is asserted and supplied to the MPU of the host computer 10 via the control line 162. In response to this, the high-order computer 10 sets the read / write signal r / w to a high level,
Execute the next instruction. On the other hand, when the wait control signal wcrl * is asserted, the upper control circuit 22 causes the interrupt request signal rqirt as shown in FIG.
Negate.

(33) An instruction to move the data stored in the address of the contents of the register B in the buffer RAM 12a to the data read buffer register 20R is executed. As a result, this data is read out from the buffer RAM 12a onto the data bus 18D, and the lower control circuit 24, based on the data on the address bus 18A,
As shown in FIG. 4G, the data write pulse dwps *
Is asserted to hold the data on the data bus 18D in the data read buffer register 20R.

Next, after executing the normal post-interruption processing, the interruption processing is ended.

The lower control circuit 24 negates (invalidates) the data write pulse dwps *, and then, FIG.
Weight control signal wcrl as shown in (H)
Assert * and set this to the MPU of the high-level computer 10.
Supply to. The high-level computer 10 responds to this,
After reading the data on the data bus 16D, the read / write signal r / w is set to low level and the next instruction is executed.
On the other hand, when the wait control signal wcrl * is asserted, the upper control circuit 22 negates the interrupt request signal rqirt as shown in FIG.

In this way, data is transferred between the upper computer 10 and the lower computer 12.

(2) Second Embodiment FIG. 6 is a block diagram of the bus adapter of the second embodiment. Figure 2
The same components as those of the above are given the same reference numerals and the description thereof will be omitted.

This bus adapter 14A is model 6803.
Host computer 10 with 0 MPU and model MP
It is connected to the lower computer 12 having the 86232 DSP. The bus 16 is a VME bus.
In the second embodiment, the upper control circuit 22 shown in FIG.
Address decoder 22a, mono multivibrator 22
b, an inverter 22c and an AND gate 22d, the lower side control circuit 24 shown in FIG. 2 is composed of an address decoder 24a, an AND gate 24b and a VME weight control circuit 24c, and the address buffer registers 20A and r / shown in FIG. Instead of w flag 20F,
The buffer register 20B is used, and instead of the data read buffer register 20R and the data write buffer register 20W shown in FIG.
0T is used.

At the input terminal of the address decoder 22a,
Address bus 1 consisting of address lines A24 to A11
6A2 is connected, and the address decoder 22a determines that the address on the address bus 16A2 is lower computer 12.
When the buffer RAM 12a of No. 2 is specified, the coincidence signal BS is sent to the trigger input terminal of the mono-multivibrator 22b, the clock input terminal CK of the buffer register 20B,
Clock input terminal CK of the bidirectional buffer register 20T
1 and to one input terminal of the AND gate 22d via the inverter 22c. In response to this, the mono-multivibrator 22b outputs an interrupt request signal XIT0 * having a constant time width and supplies it to the DSP of the lower computer 12. The data read signal doe * from the address decoder 24a is supplied to the other input terminal of the AND gate 22d.

At the input terminal of the buffer register 20B,
Address bus 1 consisting of address lines A10 to A02
6A1 and a control line 161 for transmitting a data transfer direction designation signal WRITE * corresponding to the read / write signal r / w in FIG. Lower computer 12
Can read both the address and the data transfer direction on the buffer RAM 12a by reading the contents of the buffer register 20B. As a result, the data transfer rate is improved as compared with the case of the first embodiment.

In the bidirectional buffer register 20T, a data transfer direction designating signal WRITE * is supplied to its transfer direction control input terminal DIR, a data write pulse dwps is supplied to the clock input terminal CK2, and an output enable terminal OE * is supplied. The output of the gate 22d is supplied.

The bidirectional buffer register 20T is composed of registers A and B and an input / output gate, and operates as follows. That is, when the transfer direction control input terminal DIR is at the low level, the data on the data bus 16D is transferred to the register A in synchronization with the signal supplied to the clock input terminal CK1.
When the output enable terminal OE * is at a low level, the contents of the register A are output onto the data bus 18D. When the transfer direction control input terminal DIR is high level, the data on the data bus 18D is read into the register B in synchronization with the signal supplied to the clock input terminal CK2, and the output enable terminal OE * is low level. The contents of the hour register B are output onto the data bus 16D.

Further, the data write pulse dwps * and the data read signal do from the address decoder 24a.
The e * is supplied to the input terminal of the VME weight control circuit 24c via the AND gate 24b. The VME weight control circuit 24c is an AND gate 24d.
Based on the output of the weight control signal wcrl
The normal end signal DTACK * corresponding to * is output.

The address & control line 18B is a signal line for supplying the address lines EA01 and EA00, the extended data memory address strobe signal XAS * indicating that the address on the address bus is fixed, and the extended memory read / write control signal RXW. Consists of. Here, the expansion memory is an external memory of the DSP, and means the buffer RAM 12a in this embodiment.

Other points are the same as those of the first embodiment.

[0049]

As described above, the inter-computer parallel data transfer method and bus adapter according to the present invention have the effect of simplifying the configuration thereof, and greatly contribute to the simplification of the computer system configuration.

[Brief description of drawings]

FIG. 1 is a flowchart showing the principle configuration of a method invention.

FIG. 2 is a configuration diagram of a bus adapter according to the first embodiment of this invention.

FIG. 3 is a flowchart showing a data transfer procedure of a lower computer.

FIG. 4 is a RAM of a lower computer as a higher computer
4 is a timing chart of the operation of writing data to the.

FIG. 5 is a timing chart of an operation in which a high-order computer reads data from low-order computers.

FIG. 6 is a configuration diagram of a bus adapter according to a second embodiment of the present invention.

[Explanation of symbols]

10 High-order computer 12 Low-order computer 12a Buffer RAM 14, 14A Bus adapter 16, 18 Bus 16A, 16A1, 16A2, 18A Address bus 16D, 18D Data bus 161, 162, 181, 182, 261, 281-2
85 control line 20F r / w flag 20A address buffer register 20B buffer register 20W data write buffer register 20R data read buffer register 20T bidirectional buffer register 22b mono multivibrator r / w read / write signal rqirt interrupt request signal hadr address hdata, mdata data wtrg * Latch signal rcrl * Data read signal aoe * Address read signal doe * Data read signal dwps * Data write pulse rdst * Read signal wcrl * Weight control signal XIT0 * Interrupt request signal BS match signal WRITE * Data transfer direction designation signal XAS * Extended data memory address strobe signal RXW Extended memory read / write control Signal DTACK * normal end signal DIR transfer direction control input terminal CK, CK1, CK2 clock input terminal OE output enable terminal

Claims (2)

[Claims] 1. A computer-to-computer parallel data transfer method for transferring parallel data between a high-order computer (10) and a low-order computer (12), the method being based on data on an address bus (16A) of the low-order computer. An interrupt request signal (rqirt) is supplied to the lower computer (1, 2), and a read / write signal (r /
w) holding the address on the address bus of the higher-level computer and the data on the data bus (16D) in the buffer storage means (20F, 20A, 20W, 20R) (3), and the lower-level computer sends the interrupt request signal. When the read / write signal held in the buffer storage means indicates a read operation, the data is held in the lower computer at an address corresponding to the address held in the buffer storage means. Data stored in the host computer via the buffer storage means (4,
5) If the read / write signal held in the buffer storage means represents a write, the buffer storage means is set to an address corresponding to the address held in the buffer storage means of the lower computer. (4) A data transfer end signal is transmitted from the lower computer to the upper computer (7) after the data transfer is completed, and then the data is transferred to the upper computer (7). 2. A bus adapter connected between a high-order computer (10) and a low-order computer (12) in order to transfer parallel data between the computers, on an address bus (16A) of the low-order computer. An interrupt request signal (rqirt) is supplied to the lower computer based on the data, and a higher timing signal (wtrg *) is output, and the data on the address bus (16A) of the lower computer and the lower computer are output. Of the output control signal (r
and a read / write memory element (20F) which holds a read / write signal (r / w) from the host computer in response to the host timing signal. Address storage means (20A) for holding data on the address bus of the upper computer in response to the upper timing signal, and data on the data bus (16D) of the upper computer in response to the upper timing signal. Data storage means (20W, 20R) for holding and outputting the stored contents on the data bus of the host computer in response to the output control signal
And the lower-level timing signals (rdst *, aoe *, d) based on the signal output by the lower-level computer executing interrupt processing in response to the interrupt request signal.
oe *, dwps *, wcrl *) is generated, the contents of the read / write storage element and the address storage means are read and supplied to the lower computer according to the lower timing signal, and the contents of the data storage means are read. And a lower side control circuit (24) for supplying data to the lower computer or reading data from the lower computer and holding the data in the data storage means and supplying a data transfer end signal to the upper computer after the data transfer is completed. A bus adapter characterized by having.