JPH09160689A - Data transfer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute data transfer at a high speed between the plural sets of data transfer origins and data transfer destinations by inputting transfer control data and outputting transfer origin bus switching signals and transfer destination bus switching signals by a bus control part. SOLUTION: Information for indicating which one of buses 4a, 4b and 4c is to be used is included in the transfer control data 7 outputted to a transfer control data input terminal 10 and the bus control part 1 inputs them and outputs the transfer origin bus switching signals 5 and the transfer destination bus switching signals 6. Then, a data transfer origin bus switching part 2 inputs the transfer origin bus switching signals 5 and sets a specified bus for data output and a data transfer destination bus switching part 3 inputs the transfer destination bus switching signals 6 and sets the specified bus for data input. Thus, a data transfer origin output terminal is connected through the data transfer origin bus switching part 2, the bus and the data transfer destination bus switching part 3 to a data transfer destination input terminal. As a result, the data transfer is executed at a high speed between the plural sets of the transfer origins and the transfer destinations.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention is in the technical field of interconnection or transfer of information or other signals between memories or input / output devices in digital computers. The present invention provides a data transfer circuit capable of executing high-speed data transfer simultaneously for a combination of a plurality of data transfer sources and data transfer destinations in a system having a data transfer source and a data transfer destination on a system bus or the like. Regarding

[0002]

2. Description of the Related Art Generally, when transferring data in a computer system, a CPU (Central Processing Unit) requires two operations of reading data from a data transfer source and then writing the data to a transfer destination. is there. Also,
Generally, a CPU is used as a means for executing high-speed data transfer.
DMA (Direct Memory Access) that operates independently of
A method called transfer is used.

[0003]

The former case has a drawback that the execution speed of the program processing by the CPU and the data transfer speed become slow. Also, since the DMA uses the system bus, it has a drawback that program processing using the system bus is stopped during that period. Further, in both cases, since the system bus is shared by the entire system, data transfer can be executed only between a pair of data transfer source and data transfer destination. Therefore, the purpose of the present invention is CP
It is an object of the present invention to provide a data transfer circuit that executes high-speed data transfer between a plurality of sets of data transfer sources and data transfer destinations without reducing the execution speed of program processing by U and the like.

[0004]

The above objects are achieved by the present invention described below. That is, the present invention has a "data transfer source bus switching unit, a data transfer destination bus switching unit, and a bus control unit, and the data transfer source bus switching unit inputs a transfer source bus switching signal from a plurality of buses. A specific bus is set as a data output bus, and the data transfer destination bus switching unit inputs a transfer destination bus switching signal to set a specific bus from a plurality of buses as a data input bus, and the bus control is performed. The unit is a data transfer circuit which receives the transfer control data and outputs the transfer source bus switching signal and the transfer destination bus switching signal.

According to the present invention, the data transfer source bus switching unit, to which the transfer source bus switching signal is input, sets a specific bus from a plurality of buses as a data output bus, and inputs the transfer destination bus switching signal. A specific bus is set as a data input bus from the plurality of buses by the transfer destination bus switching unit, and the transfer source bus switching signal and the transfer destination bus switching signal are output by the bus control unit to which the transfer control data is input.
That is, since there are a plurality of buses, the above specific bus can be a dedicated bus. As a result, data transfer can be performed at high speed between a plurality of sets of data transfer sources and data transfer destinations without reducing the execution speed of other processes that use the bus.

Further, the present invention is "a data transfer circuit which is at least one of the plurality of buses which is a system bus interposed between the CPU and the input / output device". This allows
Data transfer can be performed at high speed between a plurality of sets of data transfer sources and data transfer destinations without reducing the execution speed of program processing by the CPU using the system bus. According to the present invention, "the data output bus and the data input bus are FIFO (first in first out).
A data transfer circuit connected via a memory ". As a result, even if the data transfer rate differs between the data transfer source and the data transfer destination, the data transfer can be executed. According to the present invention, "a write control unit that controls writing of data on the bus for data output to the FIFO memory based on write control data output by the bus control unit and the bus control unit outputs the data. A data transfer circuit having a read control unit for controlling reading of the data of the FIFO memory to the data input bus based on the read control data ". As a result, the bus control unit can centrally control the control operation of the FIFO memory in data transfer, and the data transfer can be executed efficiently.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments. FIG. 1 is a diagram showing an example of a data transfer circuit of the present invention. In FIG. 1, 1 is a bus control unit, 2 is a data transfer source bus switching unit, 3 is a data transfer destination bus switching unit, 4a, 4b and 4c are buses, 5 is a transfer source bus switching signal, and 6 is a transfer destination bus. Switching signal, 7 is transfer control data, 8a, 8b, 8c, 8d and 8e are data transfer source output terminals, 9a, 9b, 9c, 9d and 9e are data transfer destination input terminals, and 10 is transfer control data input terminal. . A "bus" is a bundle of common signal lines for transferring information from any of a number of starting points to any of a number of ending points.

In the above structure, the transfer control data 7 is output from the other control mechanism to the bus control unit 1 through the transfer control data input terminal 10. For example, the transfer control data input terminal 10 is connected to the system bus, the CPU inputs the transfer control data stored in the memory via the system bus, and the transfer control data is input to the transfer control data input terminal 10 via the system bus. Output. The transfer control data 7 output to the transfer control data input terminal 10 includes the bus 4
Information about which of a, 4b, and 4c is used is included, and the bus control unit 1 inputs the transfer control data 7 and outputs the transfer source bus switching signal 5 and the transfer destination bus switching signal 6.

The data transfer source bus switching unit 2 inputs the transfer source bus switching signal 5 and sets a specific bus (for example, 4a) as a data output bus from the plurality of buses 4a, 4b and 4c. Further, the data transfer destination bus switching unit 3 inputs the transfer destination bus switching signal 6 and receives a plurality of buses 4a, 4b, 4c.
To set a specific bus (for example, 4a) as a data input bus. Normally, the same bus is set for the data output bus and the data input bus. As a result, the data transfer source output terminal (for example, 8a) is connected to the data transfer destination input terminal (for example, 9a) via the data transfer source bus switching unit 2, the bus 4a, and the data transfer destination bus switching unit 3.

In the example of FIG. 1, there are five data transfer source output terminals 8a to 8e and nine data transfer destination input terminals.
It is five of a-9e. The transfer control data 7 includes information as to which of the data transfer source output terminals 8a to 8e is used and which of the data transfer destination input terminals 9a to 9e is used. According to the information, any combination of the data transfer source output terminals 8a to 8e and any of the data transfer destination input terminals 9a to 9e is arbitrarily performed.

FIG. 2 is a diagram showing an example of the data transfer circuit of the present invention using a FIFO memory. 2, the same parts as those in FIG. 1 are designated by the same reference numerals. The same applies to the drawings for explaining the present invention. In FIG. 2, 11
Is a FIFO memory, 12 is a write controller, and 13 is a read controller. The write control unit 12 controls the writing of the data of the data output bus into the FIFO memory 11 based on the write control data output from the bus control unit 1. Further, the read control unit 13 controls the data of the FIFO memory 1 to be read to the data output bus based on the read control data output from the bus control unit 1.

The operations of the write controller 12 and the read controller 13 differ depending on the design specifications of the FIFO memory 11. FIG. 3 is a diagram showing an example of a FIFO memory. Description will be made based on the FIFO memory shown in FIG. In this case, the data output bus is connected to the terminals A0 to A17 of the FIFO memory, and the data input bus is B of the FIFO memory.
0 to B17 terminals are connected. Further, the output terminals of the write control unit are "CLOCKA", "W / R (BAR) A",
"CSA (BAR)", which are "WRTCLK", "WRTEN1", and "WRTEN" of the FIFO memory, respectively.
2 (BAR) ". The output terminals of the read control unit are" CLOCKB "and" W / R (BAR) ".
B "and" CSB (BAR) ", each of which is a FIFO
"RDCLK", "OE1 (BAR)", "R" of memory
It is connected to DEN (BAR) "and" OE2 (BAR) ".

The write clock "WRTCLK" and the read clock "RDCLK" may be asynchronous or the same without any restriction. "WRTEN1" is High
And when “WRTEN2 (BAR)” is Low, “WR
Data is written to the memory at the rising edge of TCLK. Also, "RDEN (BAR)", "OE1 (B
AR) "and" OE2 (BAR) "are all Low, data is read from the memory at the rising edge of" RDCLK ". In FIG. 2, the operation of the parts other than the FIFO memory is the same as in the case of FIG. Therefore, the description is omitted.

[0014]

FIG. 4 is a diagram showing a computer system using the data transfer circuit of the present invention. In FIG.
Is a CPU, 15 is a work memory, 16 is a display memory, 1
Reference numeral 7 is a display controller, and 18 is a display. 4a is CP
A system bus is interposed between the U14 and the input / output device, and 4b is one of the buses other than the system bus. As described above, in the present invention, at least one of the plurality of buses can be the system bus.

Further, according to the present invention, the data transfer circuit having the configuration shown in FIGS. 1 and 2 can be added to the system bus of the computer body or the like. As a method of adding this, for example, a data transfer circuit having the configuration shown in FIGS. 1 and 2 is used as a unit board (sub-unit board) for plug-in connection and a plug-in type main device (computer main body or the like).
Connect to In this case, the terminals connected to the system bus are
A connection terminal between the bus (for example, 4a) and the data transfer source bus switching unit, a connection terminal between the bus and the data transfer destination bus switching unit, and a transfer control data input terminal.

The operation of the configuration shown in FIG. 4 will be described step by step. The CPU 14 sends to the bus control unit 1 as transfer control data 7 information including at least the read start address of the work memory 15 which is the data transfer source, the write start address of the display memory which is the data transfer destination, and the transfer data length. Output. The bus control unit 1 outputs the information for switching the bus connection from the system bus 4a to the other bus 4b to the data transfer source bus switching unit 2 as a transfer source bus switching signal 5. Similarly, the information for switching the bus connection from the system bus 4a to the other bus 4b is output to the data transfer destination bus switching unit 3 as the transfer destination bus switching signal 6 by the bus control unit 1 (see FIG. 1).

The data transfer source bus switching unit 2 connects the bus of the work memory 15 to the other bus 4b. The data transfer destination bus switching unit 3 connects the bus of the display memory 16 to the other bus 4b. Under the control of the bus control unit 1, the write control unit 12 outputs a read address and a read signal to the work memory 15 to transfer data to the bus 4b.
The data is read out (on the side of the work memory 15). The data read to the bus 4b is written in the FIFO memory 11 and the read address is incremented. Under the control of the bus control unit 1, the read control unit 13 reads the data written in the FIFO memory 11 onto the bus 4b (on the display memory 16 side).
The data read out to the bus 4b is output to the display memory 16 as a write address and a write signal and written to the display memory 16 to increment the write address.

The write controller 12 and the read controller 13 repeat this operation to transfer the data length included in the transfer control data 7. After the transfer is completed, the bus control unit 1 outputs information for switching the bus connection to the system bus 4a to the data transfer source bus switching unit 2 as a transfer source bus switching signal 5. Similarly, information for switching the bus connection to the system bus 4a is output to the data transfer destination bus switching unit 3 as a transfer destination bus switching signal 6. In this way, the bus connection is returned to the system bus, and then the transfer end signal is returned to the CPU 14.

In the above embodiment, an example of a combination of one set of data transfer source and one set of data transfer destination has been described. However, it is easy from the above description to perform data transfer by a plurality of combinations at the same time. is there. Of course, increasing the number of combinations results in faster data transfer. Further, in the above embodiment, the data transfer direction in the bus is unidirectional, but it can be bidirectional by a known technique such as using two FIFO memories.

[0020]

COMPARATIVE EXAMPLE Referring to FIG. 4, assuming that data for display is stored in the work memory 15, a process for displaying on the display 18 using the system bus 4a will be described as a comparative example. First, the CPU 14 is the system bus 4
Data for display is read from the work memory 15 through a. Next, the data is written in the display memory 16 by the CPU 14 through the system bus 4a. The data written in the display memory 16 is CR by the display control unit 17.
It is displayed on the display 18 such as T. Since only one word of data is transferred in the above process, the time required to transfer all the data becomes long. Further, when the system bus 4a is occupied by another while transferring data having a long data length, an extra time is required during that time. Further, since the system bus 4a is occupied by this data transfer, it takes time for other program processing for the time interval.

[0021]

As described above, according to the present invention, data transfer is performed at high speed between a plurality of sets of data transfer sources and data transfer destinations without reducing the execution speed of other processes using the bus. be able to. Further, according to the present invention, at least one of the plurality of buses is the system bus interposed between the CPU and the input / output device. Data can be transferred at high speed between the data transfer source and the data transfer destination of the set. Further, according to the present invention in which the data output bus and the data input bus are connected via the FIFO memory, even when the data transfer rate differs between the data transfer source and the data transfer destination, The transfer can be performed. A write control unit that controls writing of data on the bus for data output to the FIFO memory based on write control data output by the bus control unit and read control data output by the bus control unit. According to the present invention, which has a read control unit for controlling the reading of the data of the FIFO memory to the data output bus based on the above, the bus control unit can integrally control the control operation of the FIFO memory in the data transfer. Therefore, data transfer can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a data transfer circuit of the present invention.

FIG. 2 is a diagram showing an example of a data transfer circuit of the present invention using a FIFO memory.

FIG. 3 is a diagram showing an example of a FIFO memory.

FIG. 4 is a diagram showing a computer system using the data transfer circuit of the present invention.

[Explanation of symbols]

 1 bus control unit 2 data transfer source bus switching unit 3 data transfer destination bus switching unit 4a, 4b, 4c bus 5 transfer source bus switching signal 6 transfer destination bus switching signal 7 transfer control data 8a, 8b, 8c, 8d, 8e data Transfer source output terminal 9a, 9b, 9c, 9d, 9e Data transfer destination input terminal 10 Transfer control data input terminal 11 FIFO memory 12 Write control section 13 Read control section 14 CPU 15 Work memory 16 Display memory 17 Display control section 18 Display vessel

Claims (4)

[Claims] 1. A data transfer source bus switching unit, a data transfer destination bus switching unit, and a bus control unit, wherein the data transfer source bus switching unit inputs a transfer source bus switching signal and identifies from a plurality of buses. The data transfer destination bus switching unit inputs a transfer destination bus switching signal to set a specific bus from a plurality of buses as a data input bus, and the bus control unit Is input with transfer control data and outputs the transfer source bus switching signal and the transfer destination bus switching signal. 2. The data transfer circuit according to claim 1, wherein at least one of the plurality of buses is a system bus interposed between the CPU and the input / output device. 3. The data transfer circuit according to claim 1, wherein the data output bus and the data input bus are connected via a FIFO memory. 4. The data of the data output bus is written to the FI based on write control data output from the bus control unit.
A write control unit for controlling writing into the FO memory, and the FIFO control unit based on the read control data output from the bus control unit.
4. A read control unit for controlling reading of data from an O-memory to the data input bus.
The described data transfer circuit.