JPH04162159A - Write buffer - Google Patents

Abstract

PURPOSE:To output the write data in response to the bus through which the data to be inputted are outputted by building a bus sizing function into a write buffer. CONSTITUTION:In a 1st bus cycle, the date '1122H' is stored in a data buffer 14 provided at an output part prepared to an external bus 56 and the presence of the memory data is shown. Thus '1122H' is outputted to the bus 56 as the 32-bit date. In a 2nd bus cycle, the data '3344H' is stored in the buffer 14 end the presence of the I/O data is shown since the contents of a status buffer are equal to '0'. Thus a bus control part 19 outputs only '33H' as the 16-bit data. Then the bus sizing operations can be applied to the buses of different sizes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor system, and particularly to a write buffer suitable for interfacing with an external bus in a cache system.

[Prior art] RI SC (reduced In5 tructl)
In a microprocessor system using a high-speed cache memory, such as an on-set computer (on-set computer) processor, the time required to access an external memory or an I10 (input/output interface) greatly affects the performance of the entire system.

This is one of the techniques for speeding up external access.
One example is the write buffer. In a system using a write buffer, execution of a read access is basically suspended until data arrives, but in a write access, after outputting write data, the next execution starts even if the write cycle is not completed. It becomes possible to start.

That is, during writing, it is possible to perform all-write control regardless of the access time on the main memory side, which is the output light of write data.

FIG. 5 is a block diagram showing an example of a Canni memory system using a write buffer.

This system uses CPU (central pro
cesslngunit) 51, F P U (flo
atlng polnt unit) 52, cache memory 53, write buffer 54, and address/data buses 55 and 56. Address/data bus 5
5 is a bus that connects the write buffer 54 and the CPU 51, and an address/data bus 56 is a bus that connects the write buffer 54 and the main memory. In this example, when writing data, data is written to the cache memory 53 using a write-through method, and is also written to the write buffer 54, and from this write buffer 54 is also written to the main memory. At this time, since the access time of the main memory is considerably slower than that of the cache memory 53, writing to the cache memory 53 is completed before data writing from the write buffer 54 to the main memory is completed.
At that point, the CPU 51 starts the next operation. If the next write cycle occurs before data writing from the write buffer 54 to the main memory is completed, the CPU 51 side will have to wait.
The 51st side will not be forced to wait. However, if a write cycle occurs in a state where all data buffers have final data, the CPU 51 will be forced to wait.

Figure 6 shows four built-in data buffers with a four-stage configuration <7
) /<An example of the light buffer 54 as a sofa is shown. The data buffers 61 to 64 are connected in cascade, and the write buffer 54 sequentially transfers data input from the CPU bus 55 to a FIFO (first-in-f
irst-out) format to the external bus 56.

FIG. 7 shows an example of data transfer when the data bus is 32 bits. rl IXXHJ (H means hexadecimal number), r22XXHJ is a 16-bit IXXHJ data bus.
It is the transfer data for lo, and rXXHJ means undefined. That is, data buffer 61.62.83.64
, respectively r5566H", "3344H", "22XX
When rllXX[lJ, which is the content of the data buffer 64, is output to the external bus 56 while the contents of the data buffer 64 are stored, the data buffer 8L82.
The contents of 3 are transferred sequentially. Therefore, data buffer 6
The contents of 2.63.64 are r5566■, r334 respectively.
4HJ, r22XXl (J, data buffer 61
r7788 newly input from CPU bus 55
" is stored, and this time the contents of the data buffer 64, "22XXH", are output to the external bus 56.

[Problem to be solved by the invention] However, the conventional write buffer as described above has
Since the function is simply to output data received from the CPU bus to an external bus, for example, when writing 32-bit data to Ilo, which has a 16-bit data bus, the CPU must process the 32-bit data in advance. However, it was necessary to execute two write cycles as 16-bit data. In this way, when a conventional write buffer is used, bus sizing becomes a burden on the CPU, and other processing by the CPU is sacrificed accordingly.

The present invention has been made in view of such problems, and includes:
The write buffer itself, which buffers the data input from the bus on the processor side and outputs it to the external bus, has a bus sizing function, and the input data is converted into write data according to the bus size of the bus to be output. The purpose of this invention is to provide a write buffer that has a path sizing function for output.

Means for Solving the Problem] A write buffer according to the present invention has one or more data buffers for storing data, and transfers data input from a bus on the processor side to an external bus via the data buffer. A write buffer to be output includes storage means for storing information corresponding to a bus size to which data stored in the data buffer is to be written, and data in each of the data buffers in a bus cycle according to the contents of the storage means. and bus cycle control means for outputting the data to an external bus.

[Function] In the write buffer of the present invention, the write bus sofa itself has a bus sizing function, so that input data can be sized to the bus to which this data is to be output, regardless of the bus cycle on the input side. It can be output to an external bus as a bus cycle according to the size.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the structure of a write buffer according to a first embodiment of the present invention.

The write buffer 54 shown in FIG.
1 to 14, a status signal line 20, status buffers 15 to 18, and a bus control section 19. In this case, it is assumed that the CPU bus 55 and the external bus 56 are 32-bit data buses, and that the main memory and Ilo connected via the external bus 56 have 32-bit and 16-bit data buses, respectively. . The status signal line 20 is a signal line for status information M/IO indicating whether the data output by the CPU is memory data to the main memory or I10 data to Ilo.

Status buffers 15 to 18 are each data buffer 1
Holds the status of data stored in steps 1 to 4. The bus control unit 19 controls the transfer of data in the final stage data buffer 14 to the external bus 56. This bus control unit 19, when the data is I10 data,
It has a path sizing function that divides the data in the data buffer 14 into multiple transfers and transfers them to the external bus 56.

Next, the operation of the write buffer 54 shown in FIG. 1 will be explained with reference to FIG. First, in the first bus cycle, the data buffer 1 in the output section to the external bus 56
4 stores data rl122HJ, and the content of the status buffer 18 corresponding to this data is "1", indicating that the data is memory data. Therefore, "rl122H" is output to the external bus 56 as 32-bit data. In the second bus cycle, data "3344HJ" is stored in the data buffer 14, but the content of the status buffer is "0", indicating I10 data.

Therefore, the bus control unit 19 outputs only data r331]J as 16-bit data. At this time, the remaining 16 bits on the external bus 56 are undefined. Third
In the bus cycle, r is the same as in the second bus cycle.
Data 3344HJ is stored in the data buffer 4, and "44H" data is output as 16-bit data. In this way, the bus control unit 19
When it is detected that the data is 10 data, the NOHAS cycle is executed twice for each 32-bit data, and the data is outputted to the 16-bit bus.

This first embodiment performs sizing based on status information indicating the type of data, and is therefore suitable when the bus size differs depending on the type of data.

FIG. 3 is a block diagram showing the structure of a write buffer according to a second embodiment of the present invention.

In FIG. 3, the same parts as in FIG. 1 are given the same reference numerals and detailed explanation thereof will be omitted. This second embodiment and the first
The difference from the first embodiment shown in the figure is that in this second embodiment, a sizing address is set and stored in advance inside the write buffer 54, and the sizing address to which the designated address of the write data is set is The point is that when the value matches the value, a predetermined bus sizing is performed.

In the configuration of FIG. 3, address buffers 31 to 34 are set corresponding to each data buffer 11 to 14 for each write data stored in each of these data buffers 11 to 14, and further sizing addresses, for example, "
Sizing address storage unit 3 for storing “01H”
5 and a comparator 36 for comparing the address data in the address buffer 4 and the data stored in the sizing address storage section 35.

Next, the operation of the write buffer 54 according to the second embodiment shown in FIG. 3 will be described with reference to FIG. 4. First of all,
In the first bus cycle, data rl122HJ is stored in the data buffer 14 at the output section to the external bus 56, and the contents of the address buffer 31 corresponding to this data are "rsiu", and the sizing address does not match. Therefore, "1122H" is output to the external bus 56 as 32-bit data. In the second bus cycle, data r3344HJ is stored in the data buffer 14, but the contents of the address buffer 34 are roIHJ, which matches the sizing address. Therefore, the bus control unit 19
Only data "33H" is output as 16-bit data. At this time, the remaining 16 bits are undefined. In the third bus cycle, "33" is the same as in the second bus cycle.
The data ``44111J'' is stored in the data buffer 14, and the data ``44BJ'' is stored as 16-bit data.
Output. In this way, the bus control unit 19
If 10 data is detected, two bus cycles are executed for one 32-bit data and the data is output to the 16-bit bus.

This second embodiment performs bus sizing based on data addressing rather than status information indicating the type of data, so it can be applied even when the bus size cannot be specified depending on the type of data.

According to these embodiments of the present invention, since the bus sizing function is built into the write buffer, the CP
It becomes possible to perform path sizing using the write buffer itself for buses of different sizes without sacrificing U performance.

That is, as shown in FIG. 8, in the conventional path sizing by the CPU, it was necessary to execute two write cycles as a CPU bus cycle, but according to the present invention,
As shown in FIG. 9, the CPU only executes a write cycle as one 32-bit data, and the actual path sizing is performed by the write buffer side. Therefore, the CPU
It becomes possible to proceed to the next processing cycle such as instruction fetch and data read, and the performance of the CPU improves by one cycle.

The present invention is not limited to these embodiments, and can be implemented with various modifications, for example, by changing the number of stages of data buffers.

[Effects of the Invention] As described above, according to the present invention, by incorporating a path sizing function in the write buffer, the CPU
It is possible to provide a write buffer that can perform path sizing for buses of different sizes without sacrificing performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a write buffer according to a first embodiment of the present invention, FIG. 2 is a diagram schematically explaining the operation of the same embodiment, and FIG. FIG. 4 is a block diagram showing a schematic configuration of a write buffer according to the second embodiment, FIG. 4 is a diagram schematically explaining the operation of the second embodiment, and FIG. FIG. 6 is a block diagram showing a schematic configuration of an example of a conventional write buffer; FIG. 7 is a diagram for explaining the operation of the write buffer shown in FIG. 6; FIG. 9 is an explanatory diagram of the timing of a CPU bus cycle when a conventional write buffer is used, and FIG. 9 is an explanatory diagram of the timing of a CPU bus cycle when the write buffer of the present invention is used. 11 to 4; data buffer, 15 to 18; status buffer, 19; bus MIIBm, 20: M/l0 (f
lines, 31 to 34; address buffer; 35; sizing address; 36; comparator; 307; address signal line;
51; CPU152iFPU153; cache memory, 54; write buffer, 55; CPU bus, 56; external bus

Claims (1)

[Claims] (1) In a write buffer that has one or more data buffers for storing data and outputs data input from a bus on the processor side to an external bus via the data buffer, the data stored in the data buffer and a bus cycle control means for outputting the data in each data buffer to an external bus in a bus cycle according to the contents of the storage means. A light buffer featuring