JPH04227551A - Access control circuit - Google Patents

Abstract

PURPOSE:To rewrite data in a RAM with data which are generated at the same period by altering the data, bit by bit, while reading the data out of the RAM. CONSTITUTION:An address generating means 111 generates addresses of the RAM 101 in order in specific cycles and the output of the RAM 101 or alteration information is selected by a selecting means 114 in the former half of each cycle according to the comparison result of a comparing means 113 and written in the RAM 101 in the latter half of the cycle. Thus, respective address data are read out of the RAM 101 and altered, and the data which are altered in the same cycle are stored in the RAM 101, thus rewriting the data.

Description

[Detailed description of the invention] (Table of contents) Overview Industrial field of application Conventional technology (Figures 5 to 7) Means for solving the problem to be solved by the invention (Figure 1) Working examples (Figures 2 to 4) Effects of the invention [Summary] Regarding the access control circuit that reads the contents of RAM at a constant cycle, while reading the data from RAM, the data is changed bit by bit, and the data is changed at the same cycle. An access control circuit that uses the output of an address generation means that sequentially generates each address of the RAM at a predetermined cycle as an input address to the RAM, and sequentially outputs the corresponding data. , each period is divided into two partial periods, and in the first half period, the RAM is instructed to output data corresponding to the input address, and in the second half period, the data input to the RAM is sent to the input address. an instruction means for instructing writing; a comparison means for inputting a change address corresponding to the data to be changed; and a comparison means for comparing the input address to the RAM with the change address; and a comparison means for comparing the change address and the RAM.
If the input address to the RA does not match, the RA
A selection means for outputting the data outputted by M as is and outputting change information input when it is determined that they match, and an input means for inputting the data outputted by the selection means into the RAM. .

[Industrial application field]

The present invention relates to an access control circuit that reads the contents of a RAM at regular intervals.

There is a case where it is desired to sequentially designate each address of the RAM, read out the information stored in each address at a constant cycle, and transmit the information sequentially.

In such a case, it is desired to rewrite the information stored in the RAM without stopping the read operation from the RAM.

[Conventional technology]

FIG. 5 shows the configuration of a conventional access control circuit. Further, FIG. 6 shows a timing diagram showing the operation of the access control circuit.

In the figure, the access control circuit includes a counter 511, an enable signal generation circuit 512, and a read/write control circuit 51.
3, and operates in synchronization with the clock signal shown in FIG. 6(d), all addresses of the RAM 501 are sequentially generated (see FIG. 6(e)) and input to the RAM 501 as addresses. In addition, in accordance with the output enable signal output by the enable signal generation circuit 512, data corresponding to the input address is output as read data to the input/output port I/O of the RAM 501, and this data is Type flip-flop (
D-FF) 514 and then sent out as output data DO (Fig. 6 (f), (h)
, (see (i)).

The read/write control circuit 513 also includes a comparison circuit 530 and two set-reset flip-flops (SR-F
F) 531, 532 and four D-FFs 533, 534
, 535, 536, and a gate circuit 537. This read/write control circuit 513 receives a specified address Madr output by the processor 502,
The control signal Mre, the control signal Mwe, and the interrupt signal RWF are generated based on the read control signal Re, the write control signal We, and the output of the counter 511 described above, and the interrupt signal RWF is returned to the processor 502. ing.

Next, the operation of changing the data at address n without stopping the operation of sending out the output data DO as described above will be described. FIG. 7 shows a flowchart of such a change process.

First, the processor 502 executes the specified address Ma mentioned above.
Address n is output as dr (step 701), and one clock pulse is output as the above-mentioned read control signal Re (step 702, see FIG. 6(a)).
. Thereafter, the processor 502 controls the read/write control circuit 5.
Step 703 is repeated until logic "0" is returned as the interrupt signal RWF by 13.

After the readout control signal Re mentioned above is input, the counter 5
11 becomes "n", the D-FF 535 outputs a pulse for one clock as the control signal Mre in accordance with the comparison result by the comparison circuit 530 (FIG. 6(j), (see (k)). The D-FF 515 operates in synchronization with the AND of the control signal Mre and the clock signal CK, and the output data DO at this time is held in the D-FF 515 (see FIG. 6(m)). At this time, SR-FF
The output of 531 is reset, and the above-mentioned interrupt signal R
WF becomes logic "0".

In response to this, the determination in step 703 described above is affirmative, and the processor 502 outputs the control signal Mread (step 704, see FIG. 6(n)). In response, the operation of the 3-state buffer 514 is enabled, and the data held in the D-FF 515 is output to the bus (see FIG. 6(p)).

The processor 502 reads the data output to the bus as described above (step 705), rewrites the information of the bit to be changed in this data, and changes the data (step 706).

Also, output this changed data to the bus (step 7).
07, see FIG. 6(p)), outputs the address n as the designated address Madr, and outputs the write control signal We (steps 708, 709, see FIG. 6(b)).
.

After the write control signal We mentioned above is input, the counter 5
11 becomes "n", the gate circuit 537 outputs a pulse for one clock as the control signal Wre according to the comparison result by the comparator circuit 530 (Fig. 6(j) )reference).

In response to this control signal Wre, the enable signal generation circuit 512 masks the corresponding pulse of the output enable signal Oen, and outputs a pulse of half one cycle of the clock signal CK as the write enable signal Wen (
(See Figures 6(f) and (g)). In response to this write enable signal Wen, the operation of the 3-state buffer 517 is enabled, and the data output to the bus by the processor 502 is input to the input/output port I/O of the RAM 501 as write data (6th (See figure (q)). As a result, this write data is written to the address n of the RAM 501, and the output data D
Sent as O.

At this time, similarly to the read operation described above, logic "0" is returned as the interrupt signal RWF, and in response, the processor 502 makes an affirmative determination in step 710 and ends the process.

[Problem to be solved by the invention]

By the way, in the conventional access control circuit described above, the processor 502 must first read the relevant data, modify this data, and then write the modified data, which places a large processing load on the processor 502. There was a problem.

Furthermore, in both the procedure of reading and writing the corresponding data, it is necessary to wait until the specified address n is output by the counter 511, so at least the count value of the counter 511 is It took the time required to go around twice.

The present invention was created in consideration of these points, and provides an access control circuit that changes the data bit by bit while reading data from the RAM, and rewrites the data using the changed data in the same cycle. The purpose is to provide.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, the output of address generation means 111 that sequentially generates each address of RAM 101 at a predetermined period is
The instruction means 112 in the access control circuit inputs the input address to the access control circuit 101 and sequentially outputs the corresponding data.
Each period is divided into two partial periods, and in the first half period, the RAM 101 is instructed to output data corresponding to the input address, and in the second half period, the RAM 101 is instructed to output data corresponding to the input address.
Instructs to write the data input to the input address.

The comparison means 113 receives a change address corresponding to the data to be changed, and compares the input address to the RAM 101 with the change address.

When the comparison means 113 determines that the changed address and the input address to the RAM 101 do not match, the selection means 114 outputs the data outputted by the RAM 101 as is, and when it is determined that they match, the selection means 114 outputs the input changed information. Output.

The input means 115 inputs the data output by the selection means 114 to the RAM 101.

[Effect]

The address generation means 111 causes RAM1 to be
Each address of 01 is generated sequentially, and the output from the address generation means 111 is used as the input address to the RAM 101. Each cycle described above is divided into two partial periods by the instruction means 112, and in the first half period, the instruction means 112 instructs the RAM 101 to output data corresponding to the input address. The corresponding data will be output.

Furthermore, the comparison means 113 compares the changed address and RAM1.
If it is determined that the input address to 01 does not match,
The changing means 114 outputs the data output by the RAM 101 as is. On the other hand, comparison means 113
If it is determined that the changed address and the input address to the RAM 101 match, the selection means 114 selects
Change information is output. Further, the data outputted by the selection means 114 is inputted to the RA by the input means 115.
It is input to M101.

Thereafter, in the latter half period of each period, the indicating means 1
12 instructs the write operation to the RAM 101, and in response, the above-mentioned input means 115 writes the data into the RAM 101.
The data input to 01 is input to R corresponding to the input address.
Written to AM101.

In the present invention, in the first half of each cycle, the comparison means 1
13, the selection means 114 selects
Either the output of the RAM 101 or the change information is selected, and the output from the selection means 114 is input to the RAM 101 by the input means 115 and written to the RAM 101 in the latter half of each cycle. In this way, R
It is possible to change the data while sequentially reading the data at each address in the AM 101, and to rewrite the data in the RAM 101 using the changed data in the same cycle.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an access control circuit according to an embodiment of the present invention.

Here, the correspondence between FIG. 1 and the embodiment will be explained.

RAM101 corresponds to RAM201.

Address generation means 111 corresponds to counter 211.

The instruction means 112 corresponds to the enable signal generation circuit 212.

The comparison means 113 corresponds to the comparison circuit 231.

The selection means 114 includes a selector 214 and an AND gate 23.
5 and the gate circuit 236.

Input means 115 corresponds to 3-state buffer 216.

Assuming that the above-mentioned correspondence exists, the configuration and operation of the embodiment will be described below.

In FIG. 2, a counter 211, an enable signal generation circuit 212, a read/write control circuit 213, a selector 214, and a D-type flip-flop (D-FF) 215
and the 3-state buffer 216 constitute an access control circuit 210. This access control circuit 210 controls the RAM 201 according to instructions from the processor 202.
It is configured to control access to. The D-FF 215 and 3-state buffer 216 described above are
There are m pieces each corresponding to the number m of bits of data stored in each address of the RAM 201.

The enable signal generation circuit 212 also includes a frequency dividing circuit 22.
1, the frequency dividing circuit 221 divides the input first clock signal CK1 to generate a second clock signal CK2 having a period twice that of the first clock signal CK1.
It is configured to generate.

Furthermore, the enable signal generation circuit 212 is configured to generate an output enable signal Oen and a write enable signal Wen based on this second clock signal CK2 and the above-mentioned first clock signal CK1.

Here, the enable signal generation circuit 212 outputs, as the output enable signal Oen, a signal that becomes logic "0" for half the period of the first clock signal CK1 in the first half of the period of the second clock signal CK2, and in the second half of the period. It is sufficient to output a signal that becomes logic "0" for half the period of the first clock signal CK1 as the write enable signal Wen.

Further, the second clock signal CK2 mentioned above is applied to the counter 2.
The counter 211 performs a counting operation in synchronization with this second clock signal CK2. The output from this counter 211 is input to the RAM 201 as an address.

The RAM 201 outputs data corresponding to an input address to an input/output port I/O in response to an output enable signal Oen input to a control terminal OE, and outputs data corresponding to an input address to an input/output port I/O in response to a write enable signal Wen input to a control terminal WE. , the data input via the input/output port I/O is stored in the input address.

The input/output port I/O of this RAM 201 is the selector 2
14 input port P0 of the selector 214, and the input port P1 of this selector 214 is connected to the processor 20 via the bus.
Connected to 2.

This selector 214 selects the information of the corresponding bit from the data input to the input ports P0 and P1 according to each bit of the selection information SEL outputted by the read/write control circuit 213, and selects the information of the selected bit. The configuration is such that the information is output as m-bit data. for example,
When the relevant bit is logic "1", the corresponding bit of the data input to input port P1 is selected as the information of the corresponding bit of data, and when it is logic "0", it is input to input port P0. The configuration may be such that the corresponding bits of the data to be processed are selected. The m-bit data output by the selector 214 is input to the D-FF 215.

The above-mentioned output enable signal Oen is input to the clock terminal CK of this D-FF215, and this
The output of the FF 215 is sent out as output data DO and is also input to the 3-state buffer 216. Further, this 3-state buffer 216 has a control terminal S
It becomes valid in response to a write enable signal Wen which is inverted and inputted to input the output data DO to the input/output port I/O of the RAM 201.

Further, the read/write control circuit 213 operates according to a comparison circuit 231 that compares the output of the counter 211 and the modified address Madr outputted by the processor 202, and a write control signal WE outputted by the processor 202. Set-reset type flip-flop (SR-FF
) 232, two D-FFs 233 and 234 that operate in synchronization with the second clock signal CK2, an AND gate 235, and a gate circuit 236.

The output of the SR-FF 232 described above is input to the D-FF 233, and the output of the D-FF 233 and the output of the comparison circuit 231 are input to the AND gate 235. The output of this AND gate 235 is the gate circuit 236
The gate circuit 236 is configured to output the AND of each bit of the selection control information Dsel output by the processor 202 and the output of the AND gate 235 described above as the selection information SEL.

Moreover, the output of the AND gate 235 mentioned above is the D-FF
The output of this D-FF 234 is input to the reset terminal R of the SR-FF 232 mentioned above. Further, the output of this SR-FF 232 is returned to the processor 202 as an interrupt signal WF.

The operation of the access control circuit according to the embodiment will be described below.

FIG. 3 shows a timing diagram showing the operation of the access control circuit according to the embodiment.

The first clock signal CK shown in FIGS. 3(a) and 3(b)
1 and a second clock signal CK2, respectively.

As shown in FIG. 3(c), the output of the counter 211 is
The second clock signal CK2 is added in synchronization with the second clock signal CK2.
Addresses of the RAM 201 are sequentially designated every cycle of the clock signal CK2.

In addition, in response to the output enable signal Oen shown in FIG.
(see FIG. 3(f)) and is input to the input port P0 of the selector 214.

Here, in the initial state, S of the read/write control circuit
It is assumed that the R-FF 232 has been reset. In this case, the output of the AND gate 235 becomes logic "0", so regardless of the output of the comparison circuit 231, the gate circuit 236 treats all bits of the selection information as logic "0".
0” is output.

In this way, all bits of selection information SEL are set to logic “0”.
is output, the selector 214 selects and outputs all bits of the read data Rdat from the RAM 201 input to the input port P0 (see FIG. 3).
(see g)). Therefore, in response to the rise of the output enable signal Oen, the read data Rdat described above is
It is held in F215 and output as output data DO (see FIG. 3(h)).

Thereafter, the operation of the 3-state buffer 216 is enabled in response to the write enable signal Wen, and the D-FF 215
The read data Rdat held in the RAM 201 is input as write data to the input/output port I/O of the RAM 201 (see FIG. 3(i)), and is written in correspondence with the input address.

In this way, each address is usually
In the first half of one cycle of the clock signal CK2, the corresponding data is read out, and this read data Rdat becomes the output data D.
0, and the second clock signal CK2
The data is written to the RAM 201 in the latter half of the process.

Next, the operation of changing data at address n will be explained. FIG. 4 shows a flowchart representing the data changing operation.

The processor 202 first outputs the address n at which data is to be changed as the change address Madr (step 401). Next, the processor 202 processes the modified data W
dat and selection control information Dsel are output (step 402). Here, as the changed data Wdat, changed bit information may be output to the bit line of the bus corresponding to the bit to be changed. In addition, selection control information Dsel (
7) It is sufficient to indicate the bit to be changed by setting the corresponding bit to logic "1".

Thereafter, as shown in FIG. 3(j), the processor 202 outputs a positive pulse as the write control signal WE (step 403), and continues in step 404 until logic "0" is input as the interrupt signal WF. repeat.

In step 403 described above, the output of the SR-FF 231 of the read/write control circuit 213 becomes logic "1" in response to the write control signal WE output by the processor 202.
”, and as shown in FIG. 3(m), the interrupt signal W
A logic “1” is sent to processor 202 as F.

Also, the output of this SR-FF231 is the output of D-FF232.
The second clock signal CK2 is held in synchronization with the rising edge of the second clock signal CK2, and as a result, a logic "1" is input to one of the input terminals of the AND gate 235. Therefore, the output of the AND gate 235 becomes logic "1" in accordance with the output of the comparison circuit 231 when the output of the counter 211 reaches the numerical value "n" (see FIG. 3(k)).

At this time, the gate circuit 236 outputs the selection control information Dsel as the selection information SEL, and in response, the selector 214 outputs the selection control information Dsel.
The change data Wd input to the input port P1 of the selector 214 via the bus as data of the bit indicated by
The corresponding bit information of at is selected.

Therefore, in this case, the output of the selector 214 becomes new data D in which each bit indicated by the selection control information Dsel described above is changed according to the change data Wdat (
(See Figure 3(g)). This new data D is generated in synchronization with the rise of the output enable signal Oen mentioned above.
It is held in the FF 215 and output as output data DO (see FIGS. 3(d) and (h)).

This data D is generated according to the write enable signal Wen.
The data is input as write data to the input/output port I/O of the RAM 201 via the 3-state buffer 216, and written to address n (see FIG. 3(i)).

Further, in accordance with the change in the output of the AND gate 235 mentioned above, the output of the D-FF 234 becomes logic "1", and the SR-
The FF 232 is reset and logic "0" is output as the interrupt signal WF.

In response, the processor 202 determines that the data at address n has been changed, and ends the process.

As described above, the access control circuit is configured by providing the selector 214 that selects between the read data Rdat and the modified data Wdat in accordance with the selection information SEL. Also,
The period of the second clock signal CK2 to which each address is specified is divided into the first half and the second half, and in the first half, the RAM 20
1, the output of the selector 214 described above is output as output data DO, and in the latter half, this output data DO is written to the RAM 201.

In this way, while sequentially reading the data at each address in the RAM 201, it is possible to change the data at the change address n bit by bit, and at the same time, it is possible to rewrite the data in the RAM 201 using the changed data in the same cycle. Become.

This eliminates the need for the processor 202 to read the data at the change address n in the RAM 201 and change this data, thereby reducing the processing load on the processor 202. Further, unlike the conventional technology, there is no need for a processor to wait until a corresponding address is generated by a counter in order to read data, and data modification processing can be performed at high speed.

Further, it does not affect the operation of outputting each piece of data stored in the RAM 201 at a constant cycle.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to change data at a change address while reading RAM data at a constant cycle, and rewrite the RAM data using the changed data at the same cycle. Therefore, the procedure for reading and changing data can be reduced, the processing load on the processor can be reduced, and data in the RAM can be changed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the present invention. FIG. 2 is a configuration diagram of an access control circuit according to an embodiment of the present invention. FIG. 3 is a timing diagram showing the operation of the access control circuit according to the embodiment. FIG. 5 is a configuration diagram of a conventional access control circuit; FIG. 6 is a timing diagram representing the operation of a conventional access control circuit; FIG. 7 is a flowchart representing a conventional rewriting operation. be. In the figure, 101 is a RAM, 111 is an address generation means, 112 is an instruction means, 113 is a comparison means, 114 is a selection means, 115 is an input means, 201 and 501 are RAMs, 202 and 502 are processors, and 211 and 511 are counters. , 212, 512 are enable signal generation circuits, 213, 5
13 is a read/write control circuit, 214 is a selector, 215, 233, 234, 514, 515, 533, 5
34, 535, and 536 are D-type flip-flops (D-F
F), 216, 516, 517 are 3-state buffers, 231
, 530 are comparison circuits, 232, 531, and 532 are set-reset flip-flops (SR-FF), 235 is an AND gate, and 236 and 537 are gate circuits.

Claims (1)

[Claims] 1. Access in which the output of an address generating means (111) that sequentially generates each address of a RAM (101) at a predetermined period is used as an input address to the RAM (101), and the corresponding data is sequentially output. The control circuit divides each period into two partial periods, instructs the RAM (101) to output data corresponding to the input address in the first half period, and instructs the RAM (101) to output data corresponding to the input address in the second half period.
an instruction means (112) for instructing writing of data input to the RAM (101) to an input address; and a change address corresponding to the data to be changed is input, and the input address to the RAM (101) and the change are input. If the comparison means (113) determines that the changed address and the input address to the RAM (101) do not match, the address is outputted by the RAM (101). a selection means (114) that outputs the data as is and outputs input change information when it is determined that they match; and an input that inputs the data output by the selection means (114) to the RAM (101). An access control circuit comprising means (115).