JPS59178667A - Memory device - Google Patents

Abstract

PURPOSE:To prevent the delay of the access start of another memory circuit due to access competition of one memory access by adding a buffer having the FIFO function to a memory circuit. CONSTITUTION:A control signal indicated with lower 2-bit of data in a register 6 is sent to a memory circuit block 1a, and the operation of a control circuit 24 is started, and data except lower 2-bit in the register 6 is stored in an FIFO buffer 20. Simultaneously, a control circuit 15a sends a control signal to an FIFO buffer 25, and lower 2-bit in the register 6 are stored in the buffer 25. Data stored in the buffer 20 is outputted by the second clock pulse to start the access of a memory circuit 11. At this time, if the circuit is accessed by another address data, this data is outputted from the buffer 20, and address data stored by the first clock pulse is outputted after the end of this access, and the access of this data is started. Therefore, the write to a memory circuit which is not accessed is performed without delay.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to reducing delays due to memory access contention for vector data in, for example, pipeline computers.

As a conventional device of this type, there is one shown in Figures 1 and 2 (3). Mountains to (4) in Figure 1 are the same memory circuit blocks.
f: Shown in FIG. In the figure, (5) is a data register, (6) is an address register, +71. +81
1d register.

flol is the output register that lights the selection circuit, (n)
is a memory circuit, t12+, 03+ are 1-bit registers, [141 is register +71. +81
．． 021.113+, and the memory circuit (control circuit that controls 1υ, u5) is a register +61. +71
A6) is a control circuit that performs control to input the data into the memory circuit block mountain ~ (4), and a6) is the memory circuit block mountain ~ (4).
(4) A control circuit that controls the operation of storing the output in the register (101). A signal line that sends 1-bit information to the control circuit 1151 (105)
is the control circuit (
Buses sent to 15), (106) to (109) are controlled fa1
(116) is the signal line that sends the control signal of the control circuit 1161 to the register [01,
(117J, (118J are each register +51
．． bus inputting data to +61, (119)
is a bus that sends data in register (5) to register (71) and corresponding registers in memory circuit blocks (2) to (4).

(120) is the data obtained by dividing the lower 2 bits of register (6) into register (8) and memory circuit blocks (2) to (
4) path to the corresponding register, (121)
is a bus that sends the data of the register (8) to the memory circuit (11), and (122) to (125) are the outputs of the memo 9 circuits corresponding to the memory circuit (11) and memory circuit blocks (2) to (4), respectively. The path that sends to register (10),
(126J is a path to output the data of register t101, (127J is a path to input the data of register (7) to the memory circuit (11) as address data.

Next, the operation will be explained. In this case, memo 9 circuits (11
) cycle time is 2 times the machine cycle time
The timing pulse for this operation is shown in FIG. Pulse notch in the figure: The pulse shown in red is the timing pulse to latch the data (5) to be explained next.The pulse shown in broken line is the timing pulse to latch other data. show. First, we will explain the case of reading the data of the memo 9 circuit (1υ) corresponding to the memo 9 circuit (1υ) and memory circuit blocks (2) to (4). The following describes the case of reading out the data that has been set.

The same applies to the case where data is stored in the memory circuits of memory circuit blocks (2) to (4).

After the first clock pulse, the address of the data to be read is stored in the register (6).

The first two bits of the data stored in the register (6) indicate one of the memory circuit blocks ill to (4), and these two
Bit value is 0. 1. 2. 3, each memory circuit block ill, +21. 131. 141 is shown. Make a note of the data except for the lower 2 bits of register (6)! 1 circuit (11) and memory circuit blocks (2) to (4)
) indicates the address in the memory circuit corresponding to In this case, since the data to be read is stored in the memory circuit block ), the value of the lower two pits is /I'io. Next, the information of the lower two bits is sent to the control circuit port 5.

The information on whether or not the data is included is shown as 1.0 in each case.

The control circuit (15) connects the signal lines (10 to 4) from the memory circuit blocks (1) to (4) indicated by the lower two bits above.
When one signal of (104) is 0, a control signal is output to one of the signal lines (106) to (109) input to this circuit. In this case, if the register is O, the signal line (1
A control signal is output to the register (06), and with the second clock pulse, the data excluding the lower two bits of the register (6) is stored in the register +71KM, and the register (121) is set, and access of the memory circuit (group) starts. Subsequently, the register (6) and the control circuit 151 perform the operations described above with respect to the first clock pulse.The first clock pulse causes the signal line input to the control circuit (15j When the data of the signal line indicated by the data of the lower two bits of (101) to (104) is 1, in this case (
7) (When the data in 10 is 1, the operation with the above second clock pulse is in the waiting state until the clock pulse sent after the data on this signal line reaches 0, Execution starts from the above point. Register u2 is set, and then the 1.5 clock timer (information in 131 is signaled together with the information in the registers corresponding to registers (I3) of memory circuit blocks (2) to (4)). Lines (110) to (11
3) to the control circuit (16).
161 is the next clock pulse, and (16) is the register 031 mentioned above or other memory circuit blocks (2) to (
4) Store the output of the memo 9 circuit (1υ or the corresponding memo 9 circuit) in which the register corresponding to 1υ is set in the register aO. In this case, the output of the memory circuit (memory circuit) is stored.In this way, the address is input to the register (6) at the first clock pulse.
The data of 1υ is stored in the register Cl0) and output from the memory device. The data whose address is input to the register (6) with the second clock pulse is transferred from the stored memory circuit to the memory circuit block (2).
) to (4), since the access to this memo 9 circuit can be executed in parallel with the access to the memory circuit (11), the clock pulse in which the previous data was stored in the register (10) is Register (
10). In this way, the data stored at each address can be output.

Next, memory circuit (11) and memory circuit block (2)
The case of writing to a memory circuit corresponding to ~(4) (11,3K) will be explained.Memory circuit (11)
It is assumed that the cycle time of is the same as that for reading. On the first clock pulse register +51. +61
The data to be written to each address and the address data of this data are stored. Next, the information of the lower two (9) bits of the register (6) is sent to the control circuit (151), and as in the case of reading, the control signal is sent to the signal lines (106) to (109J).
The entire signal is sent to one of the memory circuit blocks (1) to (4).

At the second clock pulse, the registers +71 . +8
] Or, the data obtained by removing the lower two bits of register (6) and the data of register (5) are stored in other registers corresponding to 71 and +81, and the data of register (5) is stored in register a2 or this register IJ2+. Other corresponding registers are set and access to the memory circuit (11) or other memo 9 circuits corresponding to this memo 9 circuit (1υ) is started. As long as you do not try to access the Memo 9 circuit while it is being accessed, data can be written every clock pulse. Also, while the Memo 9 circuit you are trying to access is being accessed (10), the signal line (IOIJ If one piece of data corresponding to (104) is 1, it enters a waiting state as in the case of reading.

Since the conventional memory device is configured as described above, 1
For example, when attempting to access data within one clock time, the memo 9 circuit (11) is being accessed.
Alternatively, if the memory circuits of memory circuit blocks (2) to (4) <IK are attempted to access the corresponding memory circuits, not only this access occurs.

There was a drawback that the next access to another memory circuit was in a waiting state.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and provides a memory device that can operate without delaying access due to access contention in one Memo 9 circuit without delaying access in other memory circuits. is intended to provide.

The details are shown in Figure 2'5. In the figure, +51.
+61. 1101 (11) (IIJ, +131. (110) ~ (113),
(116) to (11B), (126) are.

This is exactly the same as shown in Figures IIJ and J-2. (15a), (16aJ is the control circuit, t20
1 to I22+ are FIFO (First In First
t Out buffer, '231 is selection circuit, +241
05aJ is a control circuit that controls the memory circuit 0υ, register f131, and buffers 121) to (23); The lower 2 bits of data are transferred to the control circuit (15a), buffer protection)
(to6a) to (109a) are signals for sending the control signals of the control circuit (15a) to the control circuits corresponding to the selection circuits (2a) to (4a), respectively. line, (119aJ is a path that sends the data of register (5) to the buffer (201 and the FIFO buffer of memory circuit blocks (2a) to (4a), FIFO buffer corresponding to the filtering, (], 20a)
The data excluding the lower two bits of the register 16) is transferred to the buffer 1211 and the memory circuit blocks ((2a) to (4).
(121a) is a bus that sends the output of buffer (21) to the memory circuit (11), (122aJ~(
125a) are paths input to the memory circuit (11) as data.

(128J is the buffer 0 for the output of the memory circuit (11)
21. (Bus that sends to 231, (129J is FI
The paths (130) and (131) that send the output of the FO buffer □□□ to the control circuit (16a) are respectively connected to the control circuit (16a).
15aL Signal to send the (x6a) control signal to the buffer □□□! , (132J is a path that sends the output of buffer (c) to buffer (c).

The operation of the memory device configured as described above will be explained in comparison with the operation of a conventional device. It is assumed that the memory cycle time is twice the machine cycle time as in the conventional device.

First, memo 9 circuit (1υ) and memory circuit block (2a
) to (4a), the case where data is read from the memo 9 circuit corresponding to the memory circuit (11) will be described.

After the first clock pulse, address data is stored in the register (6) at the same timing as in the conventional device. The information indicated by this data is the same as the conventional device (]:jl. The lower 2 bits of this data are sent to the control circuit (15aJ), and the lower 2 bits of data are sent to the memory circuit block'' (1a ).The above control signal starts the control operation of the example control circuit, and the data excluding the lower two bits of the register (6) is stored in the FIFO buffer.

At the same time, the control circuit (15a) is a FIFO buffer 125+
This buffer t25) sends a control signal to the register (6
) is stored. The second clock pulse outputs the data stored in the buffer arc and starts accessing the memory circuit (11). At this time, if the memo 9 circuit (1υ) has been accessed by other address data, this address data is output from the buffer example, and after this access is completed, it is stored at the first clock pulse. The specified address data is output, and access to the data indicated by this address data is started.

(14) Since the memory circuit blocks (1aJ to (4a)) have such a structure, register a2, which indicates that the memo 9 circuit of the conventional device is being accessed, is not necessary, but register (6 ) is sent to these circuits on the next clock pulse.

When access is started in the memory circuit (11), the register t131 is set by typing similar to the conventional device, and information indicating that access is possible is output at the ninth clock pulse.

With this clock pulse, if the FIFO buffer @ is empty, the output of the memo 9 circuit (11) is selected and output by the buffer access), and if selected by the control circuit (16aJ), it is stored in the register and output from the memory device. The register [31 is set to 9 at the same timing as in the conventional device.If there is no difference depending on the control circuit (16a), and if the buffer a is not empty (15 is stored in the buffer (2). (If 221 is not empty, register 13j is always set and output in sequence, stored in the register and output from this memory device. Next, memory circuit blocks (1a) to (4aJ
The control circuit (16aJ) that controls the movement f'F- to select one of the output data from the register and store it in the register will be explained. - Explain the case of arranging data input order.

The control circuit (16a) is indicated by the information in the register corresponding to [131] and is
It is input to J. On the other hand, in the FIFO buffer product (FIFO buffer product), the lower two bits of the input address data are stored in the input ()@ number, so every time data is stored in the register [101], the feeding control circuit 124 is )
By performing control such that the first data is output and the next data is placed at the beginning, the first data (16) of the control circuit □□□ is set to the address of the data stored in the above register.
The address data following the data becomes information indicating the selection of the sent memory circuit block (1aJ to (4a)).

Therefore, wait until the signal indicated by the head data of the buffer (c) is set for the signal lines (110) to (113J) from the memory circuit blocks (1a) to (4a).

The output from this circuit is stored in the register (101) at the timing of the clock pulse.
The order of data output from 101 corresponds to the order in which address data was input.

Next, the memory circuit (1υ) and the memory circuit block (2) are input.Next, the information in the lower two pits of the register (6) is input to the control circuit (15a), and the control signal is sent to the memo 9Fm path block (Ia) as in the case of reading. ) to (4a).

(J7) On the path to which the control signal is sent, the data in register (5) and the data excluding the lower two bits in register (6) are stored in FIFO buffers (20 I (21I or memory circuit blocks (2a) to (2)). 4a) by 77 at,
Store in the FIFO buffer corresponding to f211. For example, this is a buffer.

(If stored in 2D, the second clock pulse outputs this stored data from the buffer ■g, [211 starts accessing the memory circuit, followed by the first clock pulse) The third action is executed.
After the second clock pulse, the operation described for the second clock pulse is repeated. Buffer (4) F.

[In 21J, the data starts being output, and after two clock times, the output of the primary data starts.

If this data does not exist, the buffer (2υ) becomes empty and the access to the memory circuit (lυ ends.
At the time of the clock pulse of O1 (18), the above embodiment describes the case where data is output in the order in which the address data is input in the case of reading, but the control circuit (16aJ is Or register [13] of memory circuit blocks (2a) to (4a)
If the configuration is configured such that the data is stored in the register t101 in the order in which the register corresponding to 1 is set, the memory device can output the data to the face that has become possible to output from the memo 9 circuit, and the above The embodiment can also output data quickly. In this case, since the data pressed from the memory device is not necessarily the first input address data, it is necessary to output information indicating which address data the output data corresponds to. The circuit shown in Figure 26 is added to the circuit shown in Figure 4 and outputs the above information.
Each memory circuit block is a buffer waiting for the 'O function (
1aJ (19) corresponds to (4a), time is a register, an adder circuit that outputs data obtained by adding 1 to the data (ceramics is the register value), 157J is a register with a selection circuit, and Misaki is the above The entire circuit that generates data indicating the number, (2oυ
The path (207) for sending power to the register is a bus for outputting the data of register 6゛θ from the memory device.

In this circuit, new data is stored in the address/data register. This data is stored in the adder circuit described above.
Since it is the output of 65), the data stored in 65) is sequentially
1. 2. 3. ...changes. The above address data is memory circuit block (la) - (4aJ
At the same time as being sent to and stored in one of the memory circuit blocks (1aJ to (4)
It is stored in one of the FIFO buffers 6υ to 6υ corresponding to a). Next, the output data of the memory circuit corresponding to the above address data is stored in the register DO), and at the same time, the data stored in one of the above buffers IIJ-641 (20) is stored in the register η. Ru.

Along with the data output from the memory circuit.

This data and data indicating the number are also output.

In the above embodiment shown in Fig. 26, the circuit 68) that generates the data indicating the number 9 is composed of only an adder and a register, but as shown in Fig. buffer 151) to (5
4J, (20B) indicates a bus that sends register data as address data to the memory circuit.

Also, in the above embodiment shown in the off-diagram, the memory circuit (
59) is used, but the same effect can be expected even if this is replaced with a conversion circuit composed of a combination of an AND circuit and a 0-way circuit, for example.

Furthermore, in the above embodiment, registers +5), +61
゜1101, and control circuits (15a), (16a),
Although only one set of 21 circuits was used as shown in Figure 6, the same effect can be expected even if two or more sets are used.

As described above, this invention has a FIFO in the memo 9 circuit.
A simple structure of adding a functional buffer can prevent delays in the start of accesses of other memory circuits due to access conflicts in one memory circuit.

[Brief explanation of the drawing]

1.1 is a block diagram showing a conventional memory device. FIG. 2 is a block diagram showing the memory circuit blocks of FIG. 1, and FIG. 3 is a block diagram of a circuit that outputs data indicating the number of output data of a timing device in the operation of the conventional device. In the figure, (1υ is a memory circuit, 1201 to (2)
is F'IF'0 buffer, (15a), (1
6aJ is the control circuit, (51)-4541 is F'LF
The O buffer is a circuit that generates data (22) indicating the data number. Note that the same line numbers in Figure 9 indicate the same or conflicting parts. Applicant Makoto Ishiita, Director General of the Agency of Industrial Science and Technology (23) Figure 5 Figure 6

Claims (5)

[Claims] (1) A plurality of memory circuit blocks each having an address register that holds an address, a data register that holds write data, and a memory circuit that is connected to each of the above registers and reads and writes data, and each of the above memory circuit blocks and an output register for holding and outputting data from the respective memory circuit blocks. FIFO (
a first buffer having a FIFO function for inputting write data to the memory circuit; and a second buffer having a FIFO function for inputting output from the memory circuit. In addition to providing 3 buffers. A memory device comprising a control circuit for instructing which of the plurality of memory circuit blocks each data from the address register and the data register is to be applied to. (2) The memory device according to claim 1, wherein each output data read from each memory circuit block is outputted to the outside in the order of the address that is input next to the address register. . (3) Each output data outputted from each memory circuit block is outputted to the outside in the order in which the output data can be outputted from the memory circuit block. The memory device according to scope 1. (4) A plurality of memory circuit blocks each having an address register that holds an address, a data register that holds write data, and a memory circuit that is connected to each of the above registers and reads and writes data, and each of the above memory circuit blocks A memory device having an output register for holding and outputting data from the I' input register for inputting an address for the memo 9 circuit into each of the memory circuit blocks.
A first buffer having an IFO (Fjrit In Firat 0ut) function and inputting write data to the above memory circuit (2) A second buffer having a FIFO function and inputting the output from the above memory circuit. a control circuit that provides a third buffer having a FIFO function and instructs which of the plurality of memory circuit blocks each data from the address register and the data register is to be applied to;
and a circuit for generating data indicating numbers corresponding to addresses sequentially input to the address register when reading data. A memory device characterized in that the number data is added to the output data that is outputted from each of the memory circuit blocks, and the resultant data is output to the outside. (5) The memory device according to claim 4, wherein each output data read (from each memory circuit block) is outputted to the outside in the order of addresses sequentially input to the address register.