JPH04209046A - Memory access circuit - Google Patents

Abstract

PURPOSE:To protect a program from a runaway in case of stack area destruction by dividing a memory by use register segments at the time of memory access and extending a maximum memory area. CONSTITUTION:The memory access circuit has a CPU 1 which sends out address information 102 and use register segment information 101 indicating a register segment in current use at the time of the memory access. Then a selecting circuit 104 sends out addresses to memories 5a-5d according to the pieces of information 101 and 102 at the time of the memory access. Consequently, a 1024kbyte memory is made to correspond to respective code, data, stack, and extra segments of registers and the memory area can be extended up to 4096 kbytes in total.

Description

[Detailed description of the invention]

0O01】

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access circuit, and more particularly to a memory access circuit in a system including an 8086 CPU. [0002]

2. Description of the Related Art In general, in an 8086-based CPU, used register segment information is sent to an address bus at timings after the second cycle of a memory read/write cycle. This is status information indicating which register is used in memory access. [0003] The 8086 series CPU uses a segment addressing method, and the code segment (C3
), data segment (DS), stack segment (
There are four segments: SS) and extra segment (ES). [0004] A general configuration of a memory access circuit using an 8086-based CPU will be described with reference to FIG. In the figure, the conventional memory access circuit includes an address latch 2 that outputs an address signal 108 based on address information 1O2 output from an 8086 CPU, and an 8086 CPU
It has a bus controller 3 that outputs a bus control signal 207 based on the bus control information 103 output from the PU, and a decoder 4 that outputs a memory select signal 205, and controls access to the memories 5a and 5b. [0005] In such a configuration, the 8086 CPU
outputs address information 102 and bus control information 103 during memory access. address latch 2
inputs the address information 1O2 and outputs the address signal 108, and the bus controller 3 inputs the bus control information 1O2 and outputs the address signal 108.
03 and outputs the bus control signal 207. The decoder 4 inputs the address signal 108 and the bus control signal 207, selects the memory to be used from among the memories 5a and 5b, and outputs a selection signal 205. Each memory receives a selection signal 205 and a bus control signal 207, and reads and writes data to and from the 8086-series cPU through the data bus 105. [0006] In other words, in general, in programs for 8086 series CPUs, the memory area is often limited to a 1024 Kbyte area, and instead it is often assumed that any address can be accessed regardless of the register used, and the hardware also It is created that way. [0007] Furthermore, since the address information is 20 bits, it is not possible to specify an address of 1048 K bits or more. [0008] Therefore, the conventional memory access circuit described above has a drawback that the maximum usable memory area is 1024 Kbytes or less. Furthermore, since it is possible to access the memory area of the stack area using a segment other than the stack segment among the registers, there is a drawback that there is a risk that the stack area may be destroyed and a program runaway may occur. [0009]

OBJECTS OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and its purpose is to provide a memory access circuit that has a large maximum usable memory area and can prevent runaway programs. . [00101

[Structure of the Invention] A memory access circuit according to the present invention is a memory access circuit including a CPU that sends out address information and used register segment information indicating a segment of a register currently in use at the time of memory access. In this case, the memory device is characterized by comprising access control means for sending an address to the memory according to the address information and the used register segment information. [00111] [Example] Next, the present invention will be explained with reference to the drawings. [0012] FIG. 1 is a block diagram showing the configuration of an embodiment of a memory access circuit according to the present invention, and parts equivalent to those in FIG. 2 are designated by the same reference numerals. In the figure, the memory access circuit of the present invention expands the maximum usable memory area by using the used register segment information 101 sent from the 8086 CPU, and has a configuration in which a selection circuit 104 is added. . [00131 In other words, a total of 22 bits (20 bits of address information output to the address bus in the first cycle of the read/write cycle and 2 bits of used register segment information output to the same bus in the second and subsequent cycles) = 4096 Kbytes), the memory area that can be used can be expanded. [0014] The hardware configuration required to realize this is the well-known D-type flip-flop (hereinafter referred to as F
It is sufficient to provide 22 (abbreviated as F). Then, at the start timing of the first cycle of the read/write cycle, 20 bits of address information are latched by 20 D-type FFs, and furthermore, at the start timing of the second cycle, 2 bits of used register segment information are latched by two FFs. All that is required is to latch it with a D-type FF and output a total of 22 bits of information to the decoder 4. [00151 Next, the operation of the circuit will be explained. [0016] The 8086 series CPU outputs used register segment information 101 when accessing memory. These are the two bits mentioned above. Segment information 101 is input to selection circuit 104, which determines the register segment to be used and outputs selection signal 107. [0017] Furthermore, the 8086-based CPUI outputs address information 1O2 before sending the used register segment information during memory access. This is the 20 bits mentioned above. The address latch 2 inputs this address information 102 and outputs an address signal 108. [0018] The 8086-based CPUI outputs bus control information 103 when accessing memory. The bus controller 3 receives bus control information 103 and outputs a bus control signal 106. The decoder 4 inputs a selection signal 107, an address signal 108, and a bus control signal 106, and divides the memory into different memories depending on the register segment used.
Outputs 9. In other words, each segment of the register and the memories 5a to 5d are accessed in correspondence. The 8086 series CPUI then accesses each memory 5a to 5d through the data bus 105. [0019] In this embodiment, each of the code segment, data segment, stack segment, and extra segment of the register has 1024 Kbytes.
1024X 4 = 4096K
The memory area can be expanded to bytes. however,
Since each segment corresponds to a memory, a single address cannot be accessed using different segments. Therefore, software programs must be created with this in mind. [00201 In this example, 8086 series C
I explained the memory access circuit in the PU,
It is clear that the present invention is applicable to other CPUs as well. [0021] As described above, the present invention has the effect that the maximum usable memory area can be expanded because the memory is divided according to register segments used during memory access. Furthermore, since the stack area cannot be accessed using segments other than the register stack segment, destruction of the stack area has the effect of making it possible to protect against program runaway.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a memory access circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a conventional memory access circuit.

[Explanation of symbols]

1 8086 series CPU 2 Address latch 3 Bus controller 4 Decoders 5a to 5d Memory 101 Used register segment information 1O2 address information 104 Selection circuit

Claims (1)

[Claims] 1. A memory access circuit including a CPU that transmits address information and used register segment information indicating a segment of a register currently in use at the time of memory access, the memory access circuit including the CPU transmitting address information and used register segment information indicating a segment of a register currently in use. A memory access circuit comprising access control means for sending an address to the memory according to used register segment information.