JPH0520248A - Input/output port - Google Patents

Abstract

PURPOSE:To improve the operability of a specific bit and to reduce the load of software by connecting a gate circuit to be controlled by a control register between an internal bus and an output latch. CONSTITUTION:The gate circuit 4 to be controlled by the control register 3 is connected between the internal bus 1 and the output latch 2 and only the bit specified by the setting of the register 3 out of data based upon a write-only instruction A to an I/O port is applied to the latch 2 through the circuit 4. Namely only the bit specified by the register 3 out of the value of the latch 2 is updated based upon the exclusive write instruction A and unspecified bits store the value of the latch 2 obtained before executing the instruction A to the I/O port. Consequently the operation of only the specific bit of the I/O port can be attained by previously setting up the bit to be operated in the register 3 and executing the write instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an input / output port,
Particularly, the present invention relates to a circuit for improving the operability for a plurality of specific bits and reducing the load on software.

[0002]

2. Description of the Related Art In a conventional input / output port, an input / output terminal, an internal bus, an output latch for setting a value between the input / output terminal and the internal bus by a dedicated instruction, and a state or output of the input / output terminal. It has an input circuit for fetching the value of the latch to the internal bus by a dedicated instruction, and each dedicated instruction realizes operation in units of 8 bits or 1 bit.

[0003]

The above-mentioned conventional input / output port has the following drawbacks.

First, a dedicated instruction for operating an input / output port is in units of 8 bits or 1 bit. For example, when operating for a specific plurality of bits, an output is performed in order to retain the contents of ports other than the operation target. Reads the latch value (8 bits) and calculates the read value and the operation target bit. It is necessary to perform processing such as setting the operation result (8 bits) in the output latch. However, there is a drawback that the output is delayed.

[0005]

An input / output port of the present invention is a control register, a gate circuit controlled by the control register between an internal bus and an output bus, and the output latch via the gate circuit. It has a dedicated instruction to set the value to.

[0006]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

As shown in FIG. 1, the input / output port of this embodiment has a control register 3 between an internal bus 1 and an output latch 2.
Only the bit designated by the setting of the control register is given to the output latch 2 via the gate circuit 4 as the data by the write-only instruction A to the input / output port.

Next, the operation of this embodiment will be described.

In this embodiment, the gate circuit 4 is composed of an AND gate, and the data corresponding to the set "1" bit of the control register 3 of the data of the internal bus is output by the write command A to the input / output port. It is latched by the latch 2. At this time, since the latch signal of the output latch 2 is given only to the set bit “1” of the control register 3, the data latched in the output latch 2 by the write command A to the input / output port is stored in the control register 3. The data of the output latch 2 corresponding to the bit that is set "1" and that is reset "0" of the control register 3 retains the value before the execution of the write instruction A to the input / output port. To do.

[0011]

As described above, the present invention has the gate circuit controlled by the control register between the internal bus and the output latch, and the data by the write-only instruction A to the input / output port is set by the control register. Since only the designated bit is given to the output latch through the gate circuit,
The value of the output latch is updated only by the write-only instruction A to the input / output port, and only the bits designated by the control register are held. The bits not designated hold the value before the execution of the write instruction A to the input / output port.

Therefore, in the case of operating only a specific bit of the input / output port, it can be realized by executing a write instruction to the input / output port by setting the bit to be operated in the control register in advance, which is a burden on the software. This has the effect of reducing the output and increasing the output speed of the I / O port.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

[Explanation of symbols]

1 internal bus 2 output latch 3 control register 4 gate circuit 5 output buffer 6 input circuit 7 input / output terminal A input / output port write-only instruction (controlled by control register) B input / output port write-only instruction C input / output port read Dedicated instruction

Claims (1)

Claim: What is claimed is: 1. An input / output terminal, an internal bus, an output latch for setting a value between the input / output terminal and the internal bus by a dedicated instruction, and an output for outputting the content of the output latch. In a I / O port having a buffer and an input circuit for fetching the state of the I / O terminal or the value of the output latch to the internal bus by a dedicated instruction, a control register and the control register between the internal bus and the output latch And an exclusive instruction for setting a value in the output latch via the gate circuit.