JPH05250079A - Input/output port - Google Patents

Abstract

PURPOSE:To prevent data written in a port register for an input port from being changed by mistake by enabling write-in to the port data register only when an input/output switching register is set at output. CONSTITUTION:This input/output port is the input/output port herebefore in use added with a port data register control means 6, and this port data register control means 6 enables the write-in to the port data register 1 only when the input/output switching register 2 is set at the output. Then, even if the input/output switching register 2 is set at input, and the data inputted from an input terminal 7 is inputted to a data bus 8 through a signal input circuit 4, this input data is never substituted for the data in the port data register 1. Accordingly, the rewriting of the port data register 1 by the input data can be easily prevented by only adding this control means 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvements in input / output ports of microcontrollers and the like. In particular, in the method in which each of a plurality of input / output ports is used by switching to an input port or an output port for each bit, the port data register of this input port is stored in the input port by the data read from the outside. The present invention relates to an improvement intended to provide an input / output port that can easily prevent data that has already been written from being accidentally changed.

[0002]

2. Description of the Related Art FIG. 3 is a principle diagram of an input / output port according to the prior art. Referring to FIG. 3, reference numeral 1 denotes a port register that operates using a write signal as a trigger signal and inputs a signal from the data bus 8. Reference numeral 2 is an input / output switching register that operates using the write signal as a trigger signal and outputs 0 (Low) when it is set as an input and outputs 1 (High) when it is set as an output. Reference numeral 3 denotes an on / off means (for example, an output buffer) which turns on / off based on the output of the input / output switching register 2. Reference numeral 4 is a signal input circuit for inputting a signal output from the port data register 1 via the ON / OFF means 3 and a signal input from the output terminal 7 to the data bus 8. Reference numeral 5 denotes a means (for example, an input buffer) which is provided in the signal input circuit 4 and turns on / off using a read signal as a trigger signal.

Next, the operation of the input / output port will be described. First, when a write signal is applied to the port data register 1, the data signal is input from the data bus 8 to the port data register 1 and written. When the input / output port is used as an output port, when a write signal is given to the input / output switching register 2,
The output setting signal is input from the data bus 8 to the input / output switching register 2 and written therein, and 1 (High) is output from the input / output switching register 2. The output 1 of the input / output switching register turns on the on / off means 3, and the data written in the port data register 1 is output from the output terminal 7. The data output from the output terminal 7 is also input to the data bus 8 via the signal input circuit 4 when a read signal is applied to the ON / OFF means 5 provided in the signal input circuit 4, and the data bus 8
Is read by a CPU (not shown) connected to. Further, when the input / output port is used as an input port, when a write signal is given to the input / output switching register 2, the input setting signal is input from the data bus 8 to the input / output switching register 2 and written, The switching register 2 outputs 0 (Low). This 0 (Low
The output turns off the on / off means 3 and prevents the data in the port register 1 from being output. And
When a read signal is applied to the on / off means 5 of the signal input circuit 4, the signal input from the terminal 7 is input to the data bus 8 via the signal input circuit 4 and read by the CPU (not shown).

A plurality of the above-mentioned input / output ports are used according to the bus width of the CPU. For example, in the case of a 4-bit microcomputer, four input / output ports are used as shown in FIG. A common write signal / read signal is applied to the input / output port. Therefore, when the input port and the output port are mixed, the write signal applied to the output port is applied to the input port, and as a result, the write to the port data register of the input port is performed. Is possible.

[0005]

As described above, when a plurality of input / output ports according to the prior art are used and the input port and the output port are mixed, the output port in the input port is used. When the data input to the data bus through the signal input circuit is read by the CPU connected to the data bus, it also spills over to the port data register of the input port, resulting in this input There is a drawback that the data already written in the port data register in case the port is used as an output port is rewritten by the above-mentioned wrap-around input data. So in the prior art,
Since the software deals with the rewriting by the input data, the processing of the software is complicated.

An object of the present invention is to eliminate this drawback, and in a system in which each of the complicated input / output ports is used by switching to an input port or an output port for each bit, an external input port is used. Another object of the present invention is to provide an input / output port that can easily prevent the data already written in the port register of the input port from being accidentally changed by the data read from the input port.

[0007]

The above object is to connect one end to the data bus and the other end to the output terminal (7) through the on / off means (3), and operate by using the write signal as a trigger signal. A port data register (1) to which a signal is input from a data bus, and one end of which is connected to the data bus, operates by using a write signal as a trigger signal, and outputs the output to control the on / off means (3). An input / output port having a switching register (2) and a signal input circuit (4) which is connected to the output terminal (7) and operates by using a read signal as a trigger signal and inputs a signal to the data bus, When the I / O switching register (2) of is set to output, writing to the port data register (1) is not possible, and the I / O switching is performed. When the register (2) is set to the input is achieved by the input and output ports of the port data register control means makes it impossible to write to the port data register (1) (6) is provided.

[0008]

2 is a diagram showing the principle of the input / output port according to the present invention. As shown in FIG. 2, the input / output port according to the present invention is a conventional input / output port to which a port data register control means 6 is added. The port data register control means 6 switches input / output. Since writing to the port data register 1 is enabled only when the register 2 is set to output, the input / output switching register 2 is set to input and the data input from the output terminal 7 is input to the signal input circuit 4. Input to the data bus 8 via
This input data is never rewritten with the data in the port data register 1. Therefore, according to the present invention, it is possible to easily prevent the data rewriting of the port data register 1 by the above-mentioned input data simply by adding the port data register control means 6.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An input / output port according to an embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, one end of the data bus 8 is connected to a data bus 8 and a terminal thereof is connected to an output terminal 7 via an on / off means 3 (described later). Is a port data register (for example, D flip-flop) to which data is written. 2 has one end connected to the data bus 8 and operates in response to a write signal,
It is an input / output switching register (for example, a D flip-flop) that outputs 0 (Low) when input is set and outputs 1 (High) when output is set. 3 is interposed between the above port data register 1 and the output terminal 7,
On / off means for turning on / off in response to the output of the input / output switching register 2 described above, for example, a P-channel FET
31, N-channel FET 32, NAND gate 33, NOR gate 34
And an inverter 35. The data bus 8 receives the signal output from the port data bus 1 via the on / off means 3 and the signal input from the output terminal 7.
It is a signal input circuit for input to. Reference numeral 5 denotes an on / off means which is provided in the signal input circuit 4 and turns on / off in response to a read signal, and includes, for example, an inverter 51, a NOR gate 52 and an N channel FET 53. 6 is a port data register control means according to the gist of the present invention. The port data register control means 6 causes the port data register 1 to write data in response to a write signal when the input / output switching register 2 is set to output. For example, a NAND gate. It is composed of 61 and an inverter 62.

Next, the operation of the input / output port according to this embodiment will be described. When the input / output switching register 2 write signal is input, the input / output switching register 2 writes the data from the data bus, outputs 1 (High) in the output setting, and 0 (Low) in the input setting. Output. Output signal 1 of this input / output switching register 2
Only when (High) and a write signal are input to the port data register control means 6, the port data register control means 6 outputs a 1 (High) signal, and the output signal causes the port data register 1 to write data. ..
Therefore, when the input / output switching register 2 is set to input, writing of data to the port data register 1 is prevented. By the way, the output of the input / output switching register 2 is also input to the on / off means 3, and when the output of the input / output switching register 2 is set, the output of the input / output switching register 2 is 1 (High).
In response to the output of the port data register 1, the P-channel FET 31 or N-channel FET 32 of the on / off means 3 is turned on, and a signal at the same level as the output of the port data register 1 is output from the output terminal 7. The data output from the output terminal 7 is also input to the on / off means 5 provided in the signal input circuit 4, is output from the on / off means 5 to the data bus 8 in response to the read signal, and is connected to the data bus 8. It is read by the CPU (not shown) that has been created.
When the input / output switching register 2 is set for input, the P-channel FET 31 and the N-channel FE of the on / off means 3 are set.
It is turned off together with T 32, so port data register 1
Data is not output from the output terminal, and an external signal input from the output terminal is input to the data bus 8 via the signal input circuit 5 when the read signal is input to the on / off means 5, and the CPU (Fig. (Not shown)).

A plurality of the above-mentioned input / output ports are used according to the bus width of the CPU, and common write signals and read signals are given to the respective input / output ports to carry out collective bit operations (FIG. 4). See again).

[0013]

As described above, the input / output port according to the present invention is obtained by adding the port data register control means to the input / output port according to the prior art. The port data register control means is the input / output switching register. Since the port data register is controlled so that writing to the port data register is possible only when is set to output, the data input from the output pin when the input / output switching register is set to input is set. Is input to the data bus via the signal input circuit, the input data does not rewrite the data in the port data register.

Therefore, according to the present invention, in a system in which each of a plurality of input / output ports is used by switching to an input port or an output port on a bit-by-bit basis, this input is performed by the data read from the outside to the input port. It is possible to provide an input / output port that can easily prevent the data already written in the port register of the working port from being erroneously changed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an input / output port according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating the principle of an input / output port according to the present invention.

FIG. 3 is a diagram illustrating the principle of an input / output port according to a conventional technique.

FIG. 4 is a diagram illustrating the configuration of a plurality of input / output ports.

[Explanation of symbols]

 1 port data register 2 input / output switching register 3 on / off means (for output) 4 signal input circuit 5 on / off means (for input) 6 port data register control means 7 output terminal 8 data bus 31 P channel FET 32 N channel FET 33 NAND gate 34 NOR gate 35 Inverter 51 Inverter 52 NOR gate 53 N-channel FET Write signal (for port data register) Write signal (for input / output switching register) Read signal Read signal

Claims (1)

[Claims] 1. One end is connected to a data bus, and the other end is connected to an output terminal (7) through an on / off means (3),
A port data register (1) which operates by using a write signal as a trigger signal and inputs a signal from a data bus, and one end of which is connected to the data bus, which operates by using a write signal as a trigger signal, and whose output is the on / off means (3) And an input / output switching register (2) for controlling the input / output, and a signal input circuit (4) connected to the output terminal (7) and operating with a read signal as a trigger signal to input a signal to the data bus. In, when the input / output switching register (2) is set to output, a write signal to the port data register (1) is enabled, and the input / output switching register (2) is set to input. In this case, a port data register control means (6) is provided which makes writing to the port data register (1) impossible. Output ports, characterized in that is formed by.