JP2504837B2 - Semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a semiconductor integrated circuit device adapted to use an output data latch circuit of an input / output port section as a memory for storing data, wherein the input / output port section is either an input port or an output port. In order to improve the efficiency of data processing by allowing the data latched in the output data latch circuit to be read out to the internal data bus even in the case of functioning in the case of the output data latch circuit and the output gate. A circuit, an input / output port terminal, an output gate control signal latch circuit, and a first
And a second input terminal connected to the output terminal of the output data latch circuit and the input / output port terminal, respectively, and controlled by the read data selection signal to output the level value of the output terminal of the output data latch circuit. Alternatively, a read data selection circuit configured to output the level value of the input / output port terminal, and a read gate circuit having its input terminal and output terminal connected to the output terminal of the read data selection circuit and an internal data bus, respectively. An input / output port section including and is provided.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device adapted to use an output data latch circuit of an input / output port section as a data storage memory.

2. Description of the Related Art In recent years, semiconductor integrated circuit devices such as one-chip microcontrollers have become highly functional, and along with this, there has been a demand for more efficient data processing. Therefore, in such a semiconductor integrated circuit device, in addition to a data storage memory provided separately and independently, an output data latch circuit provided in an input / output port section is used as a data storage memory.

[Prior Art] Conventionally, as this type of semiconductor integrated circuit device, a semiconductor integrated circuit device in which a main part thereof, that is, an input / output port part is shown in FIG. 4 is proposed.

In FIG. 4, 10 is an internal data bus, 20 is an output data latch circuit, 30 is an output gate circuit, 40 is an input / output port terminal, 50 is an output gate control signal latch circuit, 60 is a read data selection circuit, and 70 is It is a read gate circuit.

Here, the output data latch circuit 20 is provided with an nMOS FET 21 that forms a transfer gate and a register 22 that forms a latch means, and connects the drain and source of the nMOS FET 21 to the input terminals of the internal data bus 10 and the register 22, respectively. This nM
By supplying the write command signal WR to the gate of the OS FET21 and setting the write command signal WR to the high level voltage “H”, the nMOS FET21 is turned on and the output data D _O is set in the register 22.
It can be latched to.

Further, the output gate circuit 30 is provided with a so-called three-state buffer 31, the input terminal and the output terminal are connected to the output terminal and the input / output port terminal 40 of the register 22, respectively, and the three-state buffer 31 is turned on. The output data D _O latched by the register 22 can be output to the input / output port terminal 40.

Further, the output gate control signal latch circuit 50 is provided with an nMOS FET 51 that forms a transfer gate and a register 52 that forms a latch means, and connects the drain and source of the nMOS FET 51 to the input terminals of the internal data bus 10 and the register 52, respectively. At the same time, the output terminal of the register 52 is connected to the control terminal of the three-state buffer 31, the write command signal WR is supplied to the gate of the nMOS FET 51, and the write command signal WR is set to the high level voltage “H” to output the signal. Gate control signal S _C
Is latched in the register 52 to control ON / OFF of the three-state buffer 31 constituting the output gate circuit 30.

That is, when the output gate control signal S _C is at the high level voltage “H”, the three-state buffer 31 is turned on, and when the output gate control signal S _C is at the low level voltage “L”, the three-state buffer 31 is turned off. To be done.

Further, the read data selection circuit 60 is configured by providing three-state buffers 61 and 62 and an inverter 63. Here, the three-state buffer 61 has its input terminal connected to the output terminal of the register 22 and its control terminal connected to the output terminal of the register 52. The three-state buffer 62 has its input terminal connected to the input / output port terminal 40 and its control terminal connected to the output terminal of the inverter 63. The inverter 63 has its input terminal connected to the register 52.

Therefore, when the output gate control signal S _C is at the high level voltage “H”, the three-state buffer 61 is turned on,
The three-state buffer 62 is turned off. On the other hand, when the output gate control signal S _C is at the low level voltage “L”, the three-state buffer 61 is off and the three-state buffer 62 is on.

Further, the read gate circuit 70 is provided with an nMOS FET 71, the drain thereof is connected to the output terminals of the three-state buffers 61 and 62, and the source thereof is connected to the internal data bus 10.
The read command signal RD is supplied to its gate, and when this read command signal RD is at the high level voltage “H”, this nMOS FET71
Is turned on.

In the semiconductor integrated circuit device thus configured, when the write command signal WR is set to the high level voltage “H”,
The nMOS FETs 21 and 51 are both turned on, and the output data D _O and the output gate control signal are input to the registers 22 and 52, respectively.
S _C is latched. Therefore, in this case, assuming that the output gate control signal S _C is at the high level voltage “H”, the three-state buffer 31 is turned on, and the output data D _O latched in the register 22 is output to the input / output port terminal 40. It That is, at this time, this input / output port section functions as an output port.

At this time, the three-state buffer 61 is turned on. Therefore, when the read command signal RD is set to the high level voltage “H” and the nMOS FET71 is turned on in this state, the output data latched in the register 22 is output. Internal data bus 10 via D _O via three-state buffer 61 and nMOS FET 71
Can be read.

Further, the output gate control signal S _C latched by the register 52 is
Is a low level voltage “L”, the three-state buffer 31 is turned off. Therefore, in this case, the output data D _O latched by the register 22 is not output, and the three-state buffers 61 and 62 are turned off and on, respectively, so that this input / output port section functions as an input port. However, the input data D _I is input to the input / output port terminal 40. Therefore, the read command signal RD is set to the high level voltage "H" and the nMOS FET71 is turned on to input the data input to the I / O port terminal 40.
D _I can be read to the internal data bus 10 via the three-state buffer 62 and the nMOS FET 71.

[Problems to be Solved by the Invention] As described above, in such a conventional semiconductor integrated circuit device, the output data D _O latched in the register 22 is provided only when the input / output port section is made to function as an output port.
Can be read to the internal data bus 10 and the I / O port section must function as an input port.
The output data D _O latched at 22 is transferred to the internal data bus 10
Can not be read. Therefore, although the register 22 can be used as a memory for data to be internally processed,
There is a problem that data processing cannot be performed efficiently.

In view of the above point, the present invention enables the data latched in the output data latch circuit to be read out to the internal data bus when the input / output port unit functions as an input port or an output port. An object of the present invention is to provide a semiconductor integrated circuit device capable of improving the efficiency of data processing.

[Means for Solving the Problem] The semiconductor integrated circuit device of the present invention includes an output data latch circuit 20 for latching output data D _O and an output data latch circuit 20 for latching the output data D _O , as shown in the principle block diagram of the main part of FIG. Output gate circuit 30 having its input terminal connected to the output terminal of data latch circuit 20, input / output port terminal 40 connected to the output terminal of this output gate circuit 30, and conduction / non-conduction of output gate circuit 30. An output gate control signal latch circuit 50 for latching the output gate control signal S _C to be controlled and controlling conduction / non-conduction of the output gate circuit 30, and first and second input terminals 80A and 8
0B, and these first and second input terminals 80A and 80B
Are respectively connected to the output terminal and the input / output port terminal 40 of the output data latch circuit, and are controlled by the read data selection signal S _S , and the output terminal 80C has a level value of the output terminal of the output data latch circuit 20 or the input / output port. Read data selection circuit 80 configured to output the level value at terminal 40
And a read gate circuit 70 whose input terminal and output terminal are respectively connected to the output terminal 80C of the read data selection circuit 80 and the internal data bus 10 and whose conduction and non-conduction are controlled by the read command signal RD. And an input / output port section.

[Operation] In the present invention, by turning on the output gate circuit 30, the input / output port section functions as an output port, and the output data D _O latched by the output data latch circuit 20 is input / output port terminal. 40 can be output.

At this time, by controlling the read data selection circuit 80 by the read data selection signal S _S , the output data D _O latched by the output data latch circuit 20 can be output to its output terminal 80C. Therefore,
In this state, by turning on the read gate circuit 70, the output data D _O latched by the output data latch circuit 20 can be read to the internal data bus 10. That is, according to the present invention, when the input / output port section is made to function as an output port, the output data latch circuit is
The output data D _O latched by 20 can be read to the internal data bus 10.

On the other hand, by turning off the output gate circuit 30,
The input / output port section can be caused to function as an input port, and the input data D _I can be input to the input / output port terminal 40.

At this time, by controlling the read data selection circuit 80 by the read data selection signal S _S , the output data 80 or the output data D _O latched by the output data latch circuit 20 or the input / output port terminal 40 is controlled. The input data D _I being input can be read. Therefore, by turning on the read gate circuit 70, the output data D _O latched by the output data latch circuit 20 or the input data D _I input to the input / output port terminal 40 is read to the internal data bus 10. You can That is, according to the present invention, the output data D _O latched by the output data latch circuit 20 can be read to the internal data bus 10 even when the input / output port section is functioning as an input port.

[Embodiment] First, an embodiment of the present invention will be described below with reference to FIG.

FIG. 2 is a circuit diagram showing an input / output port section which is a main part of one embodiment of the present invention.

In the present embodiment, the internal data bus 10, the output data latch circuit 20, the output gate circuit 30, the input / output port terminal 4
0, the output gate control signal latch circuit 50, and the read gate circuit 70 are configured in the same manner as in the conventional example of FIG.
The read data selection circuit 80 has a different configuration.

Here, the read data selection circuit 80 of the present embodiment is the first
And second input terminals 80A and 80B, an output terminal 80C, three-state buffers 81 and 82, an inverter 83, and a read data selection signal input terminal 84 to which the read data selection signal S _S is supplied. Has been done.

The three-state buffer 81 has its input terminal connected to the output terminal of the register 22 constituting the output data latch circuit 20 via the first input terminal 80A, and its control terminal connected to the read data selection signal input terminal 84. ing.

Further, the three-state buffer 82 has its input terminal connected to the input / output port terminal 40 via the second input terminal 80B, and its control terminal connected to the output terminal of the inverter 83. The input terminal of the inverter 83 is connected to the read data selection signal input terminal 84.

In the present embodiment configured as described above, when the write command signal WR is set to the high level voltage “H”, the nMOS FETs 21 and 51 are both turned on, and the output data D _O and the output gate are input to the registers 22 and 52, respectively. The control signal S _C is latched.

Therefore, in this case, the output gate control signal
If S _C is the high level voltage “H”, the three-state buffer 31 is turned on, and the output data D _O latched in the register 22 is output to the input / output port terminal 40. That is, at this time, this input / output port section functions as an output port.

In this state, for example, the read data selection signal S _S
By setting the read command signal RD and the read command signal RD to the high level voltage “H” and turning on the three-state buffer 81 and the nMOS FET 71, respectively, the output data D _O latched by the register 22 is transferred to the three-state buffer 81 and the nMOS F.
It can be read to the internal data bus 10 via the ET71.

On the other hand, the output gate control signal S _C latched by the register 52
Is a low level voltage "L", the three-state buffer 31 is turned off, and this input / output port section functions as an input port. That is, the input data D _I is supplied to the input / output port terminal 40.

In this case, when the read data selection signal S _{S is set} to the low level voltage “L”, the three-state buffer 81 is turned off and the three-state buffer 82 is turned on. Therefore, in this state, by setting the read gate command signal RD to the high level voltage “H” and turning on the nMOS FET 71, the input data input to the I / O port terminal 40 is input.
D _I can be read to the internal data bus 10 via the three-state buffer 82 and the nMOS FET 71.

Conversely, the read data selection signal S _{S is set} to the high level voltage “H”.
When set to 3, the three-state buffer 81 is turned on and the three-state buffer 82 is turned off. Therefore, in this state, by setting the read gate command signal RD to the high level voltage “H” and turning on the nMOS FET71, the output data D _O latched by the register 22 is passed through the three-state buffer 81 and the nMOS FET71. Can be read out to the internal data bus 10.

As described above, in this embodiment, the output data D latched in the register 22 is used even when the input / output port section is made to function as an input port or an output port. _O can be read to the internal data bus 10.

Therefore, according to the present embodiment, the efficiency of data processing can be improved when the register 22 is used as a memory for storing data.

Next, another embodiment of the present invention will be described with reference to FIG.

FIG. 3 is a circuit diagram showing an input / output port portion which is a main portion of another embodiment of the present invention.

In the example of FIG. 3, an open-drain type nMOS FET 90 is connected in the subsequent stage of the output gate circuit 30, and the other parts are configured similarly to the example of FIG. That is, the output terminal of the three-state buffer 31 is connected to the gate of the nMOS FET90, the drain of this nMOS FET90 is connected to the input / output port terminal 40, and the source of this nMOS FET90 is grounded. It is configured in the same manner as.

In the example of FIG. 3, when the input / output port section functions as an output port, only the low level voltage “L” is output to the input / output port terminal 40, but the input / output port section functions as an input port. Even if
Registers even when functioning as output ports
The point that the data D _O latched in 22 can be read out to the internal data bus 10 is the same as in the example of FIG.

Therefore, also in the example of FIG. 3, as in the example of FIG. 2, the efficiency of data processing can be improved when the register 22 is used as a memory for storing data.

As described above, according to the present invention, the read data selection circuit controls whether the input / output port section functions as an input port or an output port as in the conventional example of FIG. Even when the input / output port section is made to function as an input port by adopting a configuration in which it is controlled by a separate and independent read data selection signal instead of being controlled by an output gate control signal
Even when functioning as an output port, the output data latched by the output data latch circuit can be read to the internal data bus, so data processing is possible when the output data latch circuit is used as a memory for storing data. There is an effect that the efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a principle block diagram showing a main part (input / output port part) of the present invention, FIG. 2 is a circuit diagram showing a main part (input / output port part) of an embodiment of the present invention, and FIG. Main part of another embodiment of the invention (input / output port part)
FIG. 4 is a circuit diagram showing a main part (input / output port part) of a conventional example. 10 …… Internal data bus 20 …… Output data latch circuit 30 …… Output gate circuit 40 …… I / O port terminal 50 …… Output gate control signal latch circuit 60, 80 …… Read data selection circuit 70 …… Read gate circuit

Claims (1)

(57) [Claims] 1. An output data latch circuit (20) for latching output data (D _O ), an output gate circuit (30) having an input terminal connected to an output terminal of the output data latch circuit (20), An input / output port terminal (40) connected to the output terminal of the output gate circuit (30) and an output gate control signal (S _C ) for controlling conduction / non-conduction of the output gate circuit (30) are latched, An output gate control signal latch circuit (50) for controlling conduction / non-conduction of the output gate circuit (30), and first and second input terminals (80A, 80B) are provided.
And second input terminals (80A, 80B) are connected to the output terminal of the output data latch circuit (20) and the input / output port terminal (40), respectively, and are controlled by the read data selection signal (S _S ), A read data selection circuit (80) configured to output the level value of the output terminal of the output data latch circuit (20) or the level value of the input / output port terminal (40) to its output terminal (80C); The input terminal and the output terminal are connected to the output terminal (80C) of the read data selection circuit (80) and the internal data bus (10), respectively, and their conduction and non-conduction are controlled by the read command signal (RD). A semiconductor integrated circuit device comprising an input / output port section including a read gate circuit (70).