JPH04273359A - Bus circuit - Google Patents

Abstract

PURPOSE:To reduce the load of a logic circuit which transmits the data and to improve the performance of the circuit by providing plural analog switches to secure the connection between a bus line and plural logic circuits and separating the logic circuits requiring no logical operation from the bus line. CONSTITUTION:The logic circuits 3, 5, 7 and 9 are connected to a bus line 1 via the analog switches 2, 4, 6 and 8 respectively. The open/close of these analog switches are controlled by a decoder circuit 10. When both circuits 3 and 7 carry out the logical operations for exchange of data, the instruction result is decoded by the circuit 10 and the switches 2 and 6 are closed. That is, only the circuits 5 and 7 are connected to the line 1. When the data are exchanged between both circuits 5 and 9, only these circuits are connected to the line 1. Thus the load is reduced for the logic circuit that transfers the data.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to bus circuits.

0002

2. Description of the Related Art Conventional bus circuits connect a plurality of logic circuits to a common circuit, which is driven by a bus driver with high driving power.

0003

In the conventional bus circuit, in addition to the capacity of the bus line, a plurality of logic circuits connected to the bus line impose a large load. The larger the logic circuit, the larger the capacitive load. For this reason, even if it is driven by a bus driver with high bus circuit capability, its performance will be limited. Particularly in buses within semiconductor integrated circuits, this limitation in performance is a major drawback.

0004

SUMMARY OF THE INVENTION A bus circuit according to the present invention includes a plurality of analog switches that connect a bus line and a plurality of logic circuits, and a decoder circuit that controls the plurality of analog switches.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the present invention. logic circuit 3
, 5, 7, 9 are analog switches 2, 4, 6, respectively.
8 to the bus line 1. The opening and closing of the analog switches 2, 4, 6, and 8 are controlled by a decoder circuit 10.

When logic circuit 3 and logic circuit 7 execute a logic operation for exchanging data, the instruction result is decoded by decoder circuit 10 and analog switch 2 and analog switch 6 are closed. That is, only the logic circuit 3 and the logic circuit 7 are connected to the bus line 1. Similarly, when logic circuit 5 and logic circuit 9 exchange data, only both logic circuits are connected to bus line 1.

[0007]

As described above, the present invention connects only the logic circuits for data exchange to the bus run-in. Therefore, by separating logic circuits that do not require logic operations from the bus line, the load on the logic circuits that send data can be reduced, and performance can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

[Explanation of symbols] 1 Bus lines 2, 4, 6, 8 Analog switches 3, 5, 7,
9 Logic circuit 10 Decoder

Claims (1)

[Claims] 1. A bus circuit comprising a plurality of analog switches connecting a bus line and a plurality of logic circuits, and a decoder circuit controlling the plurality of analog switches.