JPS62179219A - Two-way bus buffer - Google Patents

Abstract

PURPOSE:To prevent useless power consumption attended with a change in the level of an input terminal by connecting the input terminal of an input buffer to a fixed level when an I/O bus buffer is in the output operation so as not to operate the input buffer even when the level of a bus line is changed through an output buffer. CONSTITUTION:The output terminal of a tri-state output buffer 11 is connected to the bus line 10, further the input terminal of an input buffer 12 is connected to the bus line 10 via the 1st electronic switch 14 and the input terminal of the input buffer 12 is connected to a prescribed voltage level via the 2nd electronic switch 13. In operating the output state of the I/O bus buffer, the level of a control signal OE is brought into '1' to activate the output buffer 11 and produce a data at the output terminal in response to the value at the input terminal. In this case, a FET 14 being the 1st electronic switch is turned off at the same time, the input terminal of the input buffer 12 is cut off from the bus line 10 by the FET 14, connected to '0' level being the fixed level by the turning-on of the FET 13 to prevent useless power consumption is advance.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to an improvement of a bidirectional bus buffer (hereinafter referred to as an I10 pass buffer) that is capable of transferring signals in both directions.

Conventionally, as shown in FIG. 3, an I10 has a structure in which a three-state output buffer (hereinafter referred to as a cover sofa) 31 and an input buffer (hereinafter referred to as a cover sofa) 32 are connected to a bus line 30. Seven bus buffer circuits are used.

The output buffer 731 is controlled by an external signal OE,
When the signal OE is TI, H, a value corresponding to the input is output, and when the signal OE is "0", the output section is grooved so as to have a high impedance.

Therefore, when outputting the I10 bus buffer, the signal OH is set to II, II, and a value corresponding to the input of the output buffer 731 is output to the bus line 30.

On the other hand, when inputting the I10 pass buffer 7, the signal OE is set to "o" in order to prevent data collision, the output terminal of the output buffer 731 is set to high impedance, and data is input onto the bus 30 from the outside. A value is output to the output section of the input buffer 732 in accordance with this data.

<Problems to be solved by the invention> In the conventional +10 no.
When data is set at the input terminal of 1 and outputted on the bus 30, there may be no particular meaning in changing the value of the set data to generate data at the output terminal through the input cover sofa 32. That is, in this case, there is no need to prepare the input buffer 732 in advance.

Generally, in a circuit configured with a CMO5, when the voltage level at the input terminal changes, a current called a through current flows and consumes power. Gap buffer 32
When configured with 5 CMO circuits, the input buffer 13 described above
2 when there is no need to operate and causing the voltage level at the input terminal of the input buffer 732 to vary in accordance with the data results in unnecessary consumption of all power. In particular, if the output/input of the I10 path buffer is not frequently switched and data is frequently output to the bus 30, this wasteful power consumption becomes significant and cannot be ignored.

8JJ (/i) was devised in view of the above points, and the purpose is to provide a bidirectional bus buffer with a novel structure that prevents the above-mentioned wasteful power consumption.

<Means for Solving the Problems> In order to achieve the above object, the bidirectional bus buffer of the present invention includes a three-state output buffer whose output end is connected to the bus line, and a three-state output buffer that can be opened and closed depending on an external voltage level. a first electronic switch to be controlled; an input buffer having an input end connected to the bus line via the first electronic switch; one end connected to the input end of the input buffer; a second electronic switch whose opening/closing is controlled by an external voltage level whose other end is fixed at a predetermined voltage level;
and controlling the opening and closing phases of the second electronic switch to be opposite to each other, and controlling the opening and closing phases of the first electronic switch and the three-state output buffer to be opposite to each other. It consists of

With the above configuration, when the I10 bus buffer is operated as an output, the input terminal of the input buffer is connected to a fixed level by the closing and opening operations of the first and second electronic switches, and the output buffer is connected to a fixed level. Even when the value of the bus line changes through the input terminal, the input cover sofa does not operate in the previous state, thereby preventing wasteful power consumption due to changes in the level of the input terminal.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In FIG. 1, IO is a bus line, to which the output end of a three-state output buffer (output buffer 7) 11 is connected, and to the bus line 10 is connected a first electronic switch 14. The input end of the input buffer (input buffer 7y) +2 is connected, and the input terminal of the input buffer (input buffer 7y) +2 is connected.
20 input end is connected to a predetermined voltage level (earth level) via a second electronic switch 3.

Above output buffer IN and input buffer%cMosFET
The first electronic switch +4 is composed of a P-channel MOSFET, and the second electronic switch 13 is composed of an N-channel MOSFET.
l3 can be controlled by the control signal OE, and turns on when the signal OE is l'', and turns off when the signal OE is ``o''. FET14 can also be controlled by the control signal OEK, and turns off when the signal OE is ``]'' Then, the signal OE becomes "'0"
It turns on when .

In the above configuration, when the 10 bus buffers perform input pre-processing, the signal OE is set to II as in the conventional case.
OI+, and the output section of the output buffer 711 is set to high impedance. At the same time, the second electronic switch FETl3 is turned off, and the input end of the input buffer 12 is disconnected from the fixed level ItOI+II.
When the FET 14, which is the first electronic switch, is turned on, the input end of the input buffer 712 is connected to the bus line IOK, and operates as an input buffer.

Further, when the I10 bus buffer shown in FIG. 1 is to be put into output operation, the control signal OE is set to II, 71, and the output buffer sofa 11 is brought into operation to generate data at the output end according to the value at the input end. At this time, the first electronic switch FETI4 is turned off, the input end of the input buffer 712 is disconnected from the bus line 10 by the FETI4, and the fixed level "O" is set by turning on the FET13.
By connecting to the level, unnecessary power consumption can be prevented.

FIG. 2 is a circuit diagram showing the configuration of another embodiment of the present invention, in which the same parts as in FIG. This shows an example of a buffer configuration.

In FIG. 2, 21 is a pad for external connection, 22
is an input end protection circuit, and this input end protection circuit 22 is provided between the bus line 10 and the first electronic switch 14,
This protects the CMOS circuit from external noise.

In the circuit configuration shown in FIG. 2, normal data input/output 0J operations are the same as in the case of the circuit configuration shown in FIG.

<Effects of the Invention> As described above, according to the FIA, when the I10 pass buffer is operated as an output, the input end of the input cover sofa is connected to a fixed level, and the value of the bus line changes through the output buffer 7. In some cases, the input buffer does not operate, so that wasteful power consumption due to changes in the level of the input terminal can be prevented.

[Brief explanation of drawings]

Figure WJ1 is a circuit diagram showing the configuration of one embodiment of the present invention.
The figure is a circuit diagram showing the configuration of another embodiment of the present invention, and FIG. 3 is a circuit diagram showing a conventional example. 11... 3-state output buffer, 12... input buffer,
13...Second electronic switch (N channel MO5FE
T), I4...first electronic switch (P channel MO
5FET). Agent Patent Attorney Takeshi Sugiyama (and 1 other person) Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. A three-state output buffer whose output end is connected to a bus line; a first electronic switch whose opening/closing is controlled by an external voltage level; an input buffer whose input end is connected to the bus line; and a second input buffer whose opening/closing is controlled by an external voltage level whose one end is connected to the input end of the input buffer and whose other end is fixed at a predetermined voltage level. an electronic switch, controlling the opening and closing phases of the first and second electronic switches to be opposite to each other, and controlling the opening and closing phases of the first electronic switch and the three-state output buffer to be opposite to each other. A bidirectional bus buffer that is controlled so that it becomes . 2. The bidirectional bus buffer according to claim 1, further comprising an input terminal protection circuit provided between the bus line and the first electronic switch.