JPH0738776A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To sharply reduce power consumption by a small-scaled circuit by providing a circuit constitution in which data of a period which is not necessary at a signal processing circuit are not processed. CONSTITUTION:This circuit is equipped with a data invarying circuit 3 which outputs data of the period which is necessary for a signal processing among inputted data without operating a data processing, and outputs the data of the period which is not necessary for the signal processing by fixing the data to an arbitrary value. Then, when the data inputted from an input terminal 1 are the data of the period which is necessary at a signal processing circuit 4, the data invarying circuit 3 outputs the data without processing the data, and when the data are the data of the period which is not necessary at the signal processing circuit 4, the data invarying circuit 3 outputs the data by fixing the data to an arbitrary value (High or Low), or outputs data by holding the final data of the necessary data. The signal processing circuit 4 performs an arithmetic processing necessary for recording by using the data outputted from the data invarying circuit 3, and outputs the data from an output terminal 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit capable of reducing power consumption by stopping the circuit operation during a period when a signal processing circuit does not process a signal.

[0002]

2. Description of the Related Art Conventional video signal processing circuits perform signal processing during the entire period of input data.

FIG. 4 shows a block diagram of a conventional video signal processing circuit. In FIG. 4, 31 is a data input terminal, 32 is a signal processing circuit that performs arithmetic processing required for recording using the data input from the input terminal 31, and 33 is output from the signal processing circuit 32. This is a data output terminal.

The operation of the video signal processing circuit configured as described above will be described below with reference to FIG. By using all the data input from the input terminal 31, the signal processing circuit 32 performs the arithmetic processing required for recording,
Data is output from the output terminal 33.

[0005]

However, in the above video signal processing circuit, the power consumption is increased because only the data necessary for processing the data in the period unnecessary for the signal processing is processed.

In view of the above points, the present invention aims to reduce power consumption.

[0007]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention outputs data during a period unnecessary for signal processing without performing data processing during a period necessary for signal processing in input data. It is equipped with a data invariant circuit that outputs a fixed value to an arbitrary value by a control signal and outputs it to a subsequent circuit, and outputs the input clock without processing for the period required for signal processing, The signal processing circuit is composed of a clock stop circuit that performs switching to stop the clock in a period unnecessary for processing by a control signal and outputs it to the subsequent circuit. It is composed of a power supply stop circuit that controls the operation of the signal processing circuit by stopping the power supply when the data is in a period unnecessary for signal processing.

[0008]

With the above configuration, the data of the unnecessary period among the input data is fixed to an arbitrary value. Further, the circuit operation is stopped by stopping the clock used in the signal processing circuit when data of an unnecessary period is input. Further, the circuit operation is stopped by stopping the power supply used in the signal processing circuit when data of an unnecessary period is input. The purpose of these processes is to reduce power consumption significantly in a small-scale circuit.

[0009]

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a video signal processing circuit of this embodiment. In FIG. 1, 1 is an input terminal for data, 2 is an input terminal for a control signal for controlling whether or not data has a fixed value, and 3 is data input from the input terminal 1 from the input terminal 2. In the case of the data of the period required by the signal processing circuit 4 according to the input control signal, the data is output without being processed, and in the case of the data of the period unnecessary by the signal processing circuit 4, the input data is set to an arbitrary value. Is a data invariant circuit fixed to (or holding the final data of necessary data in the case of data of an unnecessary period in the signal processing circuit 4), and 4 is data output from the data invariant circuit 3. Is a signal processing circuit for performing arithmetic processing necessary for recording, and 5 is an output terminal for data output from the signal processing circuit 4.

The operation of the video signal processing circuit configured as described above will be described below with reference to FIG. First, when the data input from the input terminal 1 is the data of the period required by the signal processing circuit 4, it is output without being processed by the data invariant circuit 3 and is the data of the unnecessary period in the signal processing circuit 4. Is an arbitrary value (H
It is fixed to (high or Low) and output, or in the case of data of a period unnecessary for the signal processing circuit 4, the final data of necessary data is held and output to the signal processing circuit 4. The signal processing circuit 4 uses the data output from the data invariant circuit 3 to perform arithmetic processing necessary for recording and outputs the data from the output terminal 5.

(Second Embodiment) FIG. 2 is a block diagram of a video signal processing circuit of the present embodiment. In FIG. 2, 11 is a clock input terminal, 12 is a control signal input terminal for controlling whether or not to stop the clock, 13 is a data input terminal, and 14 is an input from the input terminal 13. Is a signal processing circuit for performing arithmetic processing necessary for recording by using the recorded data. Reference numeral 15 is a signal processing circuit for stopping the clock by using a control signal input from the input terminal 12 when the data has an unnecessary period. A clock stop circuit for causing the data to be output, and 16 is an output terminal for the data output from the signal processing circuit 14.

The operation of the video signal processing apparatus configured as described above will be described below with reference to FIG. First, of the data input from the input terminal 13, for data of an unnecessary period in the signal processing circuit 14, the clock input from the input terminal 21 is stopped by the control signal input from the input terminal 22, and the clock is stopped. Output from the circuit 15. By inputting the clock output from the clock stop circuit 15 to the signal processing circuit 14, the circuit operation is stopped and data is output from the output terminal 16.

(Embodiment 3) FIG. 3 is a block diagram of a video signal processing circuit of this embodiment. In FIG. 3, reference numeral 21 is a data input terminal, 22 is a clock input terminal, and 23 is a data input from the input terminal 21 and a clock input from the input terminal 22 for performing arithmetic processing necessary for recording. A signal processing circuit, 24 is an input terminal of a signal for controlling whether or not the power supply of the signal processing circuit 23 is stopped, and 25 is data in a period unnecessary for signal processing in the signal processing circuit 23, A power supply stop circuit that stops the power supply of the signal processing circuit 23 by the control signal input from the input terminal 24 to stop the circuit operation, and 26 is an output terminal for the data output from the signal processing circuit 23.

The operation of the video signal processing apparatus configured as described above will be described below with reference to FIG. First, using the data input from the input terminal 21 and the clock input from the input terminal 22, the signal processing circuit 23 performs arithmetic processing necessary for recording, and the signal processing circuit 23
In the case of data of a period unnecessary for signal processing, the control signal input from the input signal 24 is input to the power supply stop circuit 25, the power of the signal processing circuit 23 is stopped to stop the circuit operation, and the output terminal 26 To output data.

[0016]

As described above, according to the present invention, by adopting a circuit configuration in which a signal processing circuit does not process data for an unnecessary period, a large reduction in power consumption is realized with a small-scale circuit. I can do things.

[Brief description of drawings]

FIG. 1 is a block diagram of a video signal processing circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a video signal processing circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a video signal processing circuit according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a conventional video signal processing circuit.

[Explanation of symbols]

 3 data invariant circuit 4 signal processing circuit 14 signal processing circuit 15 clock stop circuit 23 signal processing circuit 25 power supply stop circuit 32 signal processing circuit

Claims (4)

[Claims] 1. A control signal is used to switch the input data for a period required for signal processing without performing data processing and to output the data during a period unnecessary for signal processing while fixing the data to an arbitrary value. A video signal processing circuit comprising a data invariant circuit for performing and outputting to a subsequent circuit. 2. The video signal processing circuit according to claim 1, wherein the data invariant circuit is composed of a circuit for holding and outputting final data of data of a period required for signal processing. 3. A clock which outputs an input clock without processing during a period required for signal processing, and stops the clock during a period not required for signal processing by a control signal and outputs the clock to a subsequent circuit. A video signal processing circuit comprising a stop circuit. 4. A signal processing circuit for performing signal processing according to input data and a clock, and operation of the signal processing circuit by stopping power supply when data is in a period unnecessary for signal processing in the signal processing circuit. A video signal processing circuit comprising a power supply stop circuit for controlling the video signal.