JPH07141288A - Dma transfer system - Google Patents

Abstract

PURPOSE:To obtain a control part which performs a pipeline process for data at a high speed without requiring a large-scale constitution. CONSTITUTION:This system is equipped with a DMA control part 1a which operates in order of every transfer cycle with >=2 channels, a dedicated integrated circuit 2a which performs a process through a multi-stage pipeline, a memory part 3 which stores the process result, an interface part 4 for external equipment, and a CPU 5 which controls the whole device, and, the DMA control part 1a is so constituted that the number of delay transfer cycle until the start of transfer operation of each channel is >=2. Consequently, unnecessary operation can be eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a dedicated integrated circuit (LS).
According to I), the present invention relates to a data processing device for performing high-speed processing in a multi-stage pipeline, which is executed by the DMA transfer method.

[0002]

2. Description of the Related Art In a conventional data processing device, a CPU directly processes data or has a processing-dedicated LSI and a processing-dedicated LSI on a CPU bus.
LS for processing by connecting the CPU and transferring data by the CPU
A method is used such as whether I processes the data, or whether the data is processed by using a dedicated bus and a dedicated LSI.

In addition, a DMA (Dire) for high-speed data transfer between a memory and a processing-dedicated LSI without intervention of a CPU.
ct Memory Access) As a data processing method using transfer, the alternate operation of 2-channel DMA as described in the data transfer control method of JP-A-4-195448 and the data processor using the method is applied to data processing. It is also possible. In the case of this data processing method, for example, the data received from the external device by the interface unit is input to the processing-dedicated LSI through one channel of the DMA control unit by the alternate operation of the two-channel DMA, and the result of pipeline processing is displayed. The data is stored in the memory unit on the other channel of the DMA control unit.

[0004]

However, in order to perform enormous processing of image data and the like, in the above-mentioned conventional method, the CPU requires processing time to process and transfer data, and in the method of the above method There is a problem in that it does not need to be large-scaled and it lacks flexibility because it is composed of hardware.

Further, in the above-mentioned conventional method, if it is applied to a processing-dedicated LSI having two or more pipeline stages, it is necessary to perform a wasteful transfer operation for adjusting the number of pipeline stages, resulting in inefficient data processing. There is. For example, when performing color conversion from an RGB signal to a YMC signal with a 4-stage pipeline configuration in image processing,
The conversion output cannot be obtained unless four pieces of data are continuously input to the processing-dedicated LSI, so that in the alternate operation, useless transfer operation is performed in the meantime.

[0006] Therefore, the present invention is to solve the above problems, and an object of the present invention is to realize a control unit which does not require a large scale configuration and which pipelines data at high speed.

[0007]

To this end, the present invention provides two
D that operates in order for each transfer cycle on channels or more
The MA control unit, a dedicated integrated circuit that performs processing in a multi-stage pipeline, a memory unit that stores the processing result, an interface unit with external devices, and a CPU that controls the entire apparatus are provided. It is characterized in that the number of delayed transfer cycles until each channel starts the transfer operation is set to 2 or more.

[0008]

According to the DMA transfer method of the present invention, a DMA control unit that operates in two or more channels in sequence for each transfer cycle, and a dedicated integrated circuit that performs processing in a multistage pipeline,
A DM including a memory unit for storing processing results, an interface unit for external devices, and a CPU for controlling the entire apparatus,
Since the A control unit is configured so that the number of delayed transfer cycles until each channel starts the transfer operation is 2 or more, C
Under the control of the PU, the interface unit inputs the data received from the external device to the processing-dedicated LSI in one channel of the DMA control unit, and the result of the multistage pipeline processing is performed in the memory unit in the other channel of the DMA control unit. Even when storing in, it is possible to eliminate unnecessary operations.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a DMA transfer system according to the present invention. In FIG. 1, the DMA controller 1a
It is composed of two channels, A channel and B channel, and a delayed transfer cycle is set in each channel, and after delayed activation based on the setting, it operates in sequence for every one transfer cycle. The dedicated LSI 2a performs processing in a multi-stage pipeline, and the memory unit 3 stores the processing result. The interface unit 4 is an interface with an external device, and the CPU 5 controls the entire apparatus.

In the DMA control section 1a, the A channel performs DMA transfer from the interface section 4 to the dedicated LSI 2a, and the B channel performs DMA transfer from the dedicated LSI 2a to the memory section 3. The operation sequence is such that the A channel starts the operation and executes the set delayed transfer cycle, and then the B channel starts the operation and operates alternately every one transfer cycle. The dedicated LSI 2a has a multi-stage pipeline configuration in which necessary data processing is executed by supplying data and a write signal input and the result can be read by a read signal.

In the above configuration, the interface unit 4 inputs the data received from the external device to the processing-dedicated LSI 2a through one A channel of the DMA control unit 1a in a predetermined cycle, and thereafter is subjected to the multi-stage pipeline processing by the alternate operation. Since the obtained result is stored in the memory unit 3 through the other B channel of the DMA control unit 1a, the DMA operation with the memory unit 3 also follows the processing of the dedicated LSI 2a, so that a correct result can be obtained even in the multistage pipeline. . If the number of pipeline stages is, for example, 5, the A channel starts to operate and after 5 transfer cycles have been executed, the B channel starts to operate, and thereafter, the B channel operates alternately every 1 transfer cycle. With this configuration, the CPU 5 sets the delay activation of the DMA channel to the DMA control unit 1a, so that the dedicated LS having different pipeline stages can be used.
I can also be used flexibly. In this embodiment, the two channels are alternately operated for each transfer cycle. However, when the number of input data and the number of output data of the processing-dedicated LSI 12 are different, one or both channels are transferred a plurality of times. The number of data may be balanced by alternately operating as a cycle.

FIG. 2 is a diagram showing a second embodiment of the DMA transfer system of the present invention. In this embodiment, there are three channels of A channel, B channel, and C channel, and a DMA control unit 1 of three channels that operates in sequence for each transfer cycle.
c and dedicated LSIs 2a, 2c for performing pipeline processing
It adopts a configuration with and. Then, the A channel is DMed from the interface unit 4 to the dedicated LSI 2a.
A transfer is performed, B channel is DMA transferred from the dedicated LSI 2a to the dedicated LSI 2c, and C channel is dedicated L
The DMA transfer is performed from the SI 2c to the memory unit 3. Further, the operation sequence is such that after the A channel starts to operate and a predetermined delay transfer cycle is set, one transfer cycle is sequentially performed for the B channel and the C channel, and thereafter, the operation is repeated. The dedicated LSI2
a, the dedicated LSI 2c has a pipeline configuration in which necessary data processing is performed by supplying data and a write signal input, and the result can be read by a read signal. The number of pipeline stages is such that the dedicated LSI 2a has multiple stages and is dedicated. LSI
2c is the first stage.

According to this embodiment, by changing the role setting of the DMA channel, it is possible to flexibly configure the processing order by the cascade connection of the dedicated LSIs. Further, when the amount of completed data changes, the processing amount can be reduced by changing the combination of the processing order. For example, when performing the enlargement / reduction processing and the color conversion processing, the reduction and the color conversion are performed. In the combination, the reduction processing is performed first, and then the color conversion processing is performed. In the combination of enlargement and color conversion, the color conversion processing is performed and the enlargement processing is performed, thereby reducing the amount of color conversion processing. be able to.

FIG. 3 is a diagram showing a third embodiment of the DMA transfer system of the present invention. This embodiment employs a configuration including a two-channel DMA control unit 1d capable of setting functions for independent operation and sequential operation for each transfer cycle, and a dedicated LSI 2a for performing processing in a one-stage pipeline. is there.
In the DMA control unit 1d, when the two channels, A channel and B channel, are set to be able to operate independently, DM is transferred from the interface unit 4 to the memory unit 3.
A transfer is performed, or DMA is performed between two areas of the memory unit 3.
Transfer it. When the function is set to the sequential operation for each transfer cycle, the A channel performs DMA transfer from the interface unit 4 to the dedicated LSI 2a, and
The channel performs DMA transfer from the dedicated LSI 2a to the memory unit 3. It should be noted that the dedicated LSI 2a has a one-stage pipeline configuration in which data and a write signal are input to perform necessary data processing and the result can be read by a read signal.

According to this embodiment, it is possible to flexibly select and use a normal DMA operation or pipeline processing by setting the function of the DMA channel.

The present invention is not limited to the above embodiment, but various modifications can be made. For example, in the above-described embodiment, an example in which the image data is DMA-transferred has been described, but it goes without saying that the same can be applied to the case of DMA-transferring another data.

[0017]

As described above, according to the present invention, the processing of an arbitrary number of pipeline stages can be executed by setting the delay operation of each channel of the DMA control unit, so that the processing can be performed at a relatively high speed. A highly flexible processing device can be easily provided. Moreover, since various data processing is left to the dedicated LSI and the DMA control unit, the data processing speed can be improved, and the CPU can concentrate on input / output control and the like, so that the processing capacity of the entire system can be improved. it can.

[Brief description of drawings]

FIG. 1 is a diagram for explaining one embodiment of a DMA transfer system according to the present invention.

FIG. 2 is a diagram for explaining a second embodiment of the DMA transfer system according to the present invention.

FIG. 3 is a diagram for explaining a third embodiment of the DMA transfer system according to the present invention.

[Explanation of symbols]

1a ... DMA control section, 2a ... dedicated LSI, 3 ... memory section, 4 ... interface section, 5 ... CPU

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G06T 1/20

Claims (1)

[Claims] 1. A DMA controller that operates in two or more channels in sequence for each transfer cycle, a dedicated integrated circuit that performs processing in a multi-stage pipeline, a memory unit that stores a processing result, and an interface with an external device. And a CPU that controls the entire apparatus, and the DMA control unit is configured so that the number of delayed transfer cycles until each channel starts a transfer operation is 2 or more.