JPS6217776B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device, and more particularly to a data processing device with an improved input/output control device for controlling data transfer between an input/output device and a main storage device.

In conventional data processing devices, execution of a data transfer type input/output command is performed using data of the data transfer length indicated in the data transfer type input/output command in order to synchronize the central processing unit and the input/output control unit. When the transfer is completed, the input/output control device issues a termination signal to the central processing unit, and the central processing unit processes the transferred data when it becomes possible. That is, the central processing unit could not start processing the data until it received a data transfer end signal from the input/output control unit. Therefore, in order for the central processing unit to process data, the input/output control unit must transfer all the data of the data transfer length indicated by the data transfer type input/output command word to the main memory at once, and therefore the main memory It was necessary for the storage device to have a buffer that was at least equal to the data transfer length. Therefore, in consideration of efficient use of the main memory and efficient processing of data, multiple buffers smaller than the data transfer length are prepared in the main memory, and the contents of these buffers can be tested or put into a certain state. By controlling this test setting input/output command word, check whether the buffer can be used, and if it is usable, jump to the data transfer type input/output command word, or if it is unusable. All data transfer processing was performed by alternating small buffers by changing the execution order of a series of input/output command words, such as jumping to a processing routine that waited until a usable state was reached. .

However, the above method adds a new test setting input/output command word, which complicates the configuration of a series of input/output command words, and also makes it difficult to execute the input/output command word using the test setting input/output word. It was not always possible to say that efficient processing was performed, such as the need to add hardware to change the order.

Therefore, it is an object of the present invention to improve the data transfer control method using the test setting input/output command words to enable more efficient data processing.

According to the present invention, a central processing unit, a main storage device in which a series of input/output command words are stored, an input/output control device that controls execution of the input/output command words, and a comprising an input/output device that executes an operation based on the input/output command word independently of the operation of the central processing unit, and means for notifying the central processing unit of completion of execution of the series of input/output command words, In order to synchronize between the central processing unit and the input/output control device during a data transfer type input/output command word for executing data transfer data between the input/output device and the main storage device, It has a field that specifies testing of a specific area existing in the storage device, and further instructs the start of data transfer or changes the execution order of subsequent input/output command words based on the result of the test. A data processing device characterized in that the means is provided is obtained.

First, to give an overview of the functions of this device, a field in the data transfer type input/output command word is given an instruction to check the status of the buffer in the main memory used for data transfer control, and a test instruction is given. If the data transfer buffer address indicated in the data transfer type input/output command word indicates the buffer status, the field indicating the buffer status at the beginning of the field indicated by the data transfer buffer address is tested, and the data transfer of the subsequent field is performed based on the test result. If it is possible, execute a data transfer operation using a data transfer type input/output command word, and if it is impossible to execute a data transfer operation, perform a data transfer operation using a data transfer type input/output command word without performing a data transfer operation using a data transfer type input/output command word. The execution order of the input/output command words is controlled by moving to the next input/output command word after the data transfer is executed, and the input/output control unit operates in parallel with the operation of the central processing unit. out of all the data transferred by the input/output control unit, when the data necessary for processing by the central processing unit is transferred to the buffer, the central processing unit is notified that it can be processed, and the central processing unit starts processing the data if it can process it. During this period, the input/output control device transfers data to other buffers. That is, a plurality of buffers having the minimum required size are alternately used, thereby making it possible to process a large amount of data without interrupting the processing of the central processing unit.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, 11 is a main storage device;
12 is a central processing unit, 13 is an input/output control unit, 1
4 is an input/output control section in this input/output control device 13;
Reference numeral 15 denotes a branch control unit, which is a feature of the device of the present invention, 16 an input/output device, and portions indicated by 1, 2, 3, and 4 in the input/output control unit 14 are channels with the input/output device 16. The input and output ports are shown respectively. A series of input/output command words are stored in the main storage device 11 in correspondence with the input/output device 16, and when the input/output control device 13 receives a command from the central processing unit 12 via the bus a,
From the main storage device 11 through bus b to the input/output device 1
The input/output command word corresponding to any one of input/output command words ₆₁ to ₁₆₄ is taken in, and the control operation corresponding to the input/output command word taken in is instructed to the logic of the input/output ports 14-1 to 14-4. The logic of input/output ports 14-1 to 14-4 sends control information to input/output devices ₁₆₁ to ₁₆₄ , respectively, through buses _c1 to _c4 . Furthermore, events occurring in these input/output devices are transmitted to input/output ports 14-1 to 14-1 through buses _c1 to _c4 .
4-4 respectively, and the input/output control device 13
will process the information conveyed to them.

FIG. 2 is a diagram showing the format of input/output command words used in the above embodiment. There are 8 input/output command words.
The first byte (bits 0 to 7) is a command code section indicating the type and operation of the input/output command word. The second byte (bits 8 to 15) is a flag byte that instructs auxiliary control of the command in the operation according to the command code, and is a flag byte that instructs auxiliary control of the command in the operation according to the command code.
A setting ( _TEST & _SET, abbreviated as T&S) designation flag also occupies one bit in this flag byte.
The third and fourth bytes (bits 16 to 31) are count fields indicating the data transfer length in the data transfer type input/output command word. The 5th, 6th, 7th, and 8th bytes (bits 32 to 63) are the data buffer address or T&
When the S flag is “ON”, it indicates the address of the lock byte that exists before the data buffer.
In unconditional branch input/output command words, it indicates the address of the branch destination.

FIG. 3 is a diagram showing two data buffers A and B set in the main memory 11 in this embodiment, and the buffer sizes are LA and LB, respectively. At the start address AAAA or BBBB of data buffers A and B, 1 byte of lock byte A and lock byte B exist.

FIG. 4 is a diagram showing a group of input/output command words in this embodiment. This is also called a channel program. In Figure 4, a channel program consists of three input/output command words, each connected by a command chain flag (CC) indicated by a flag field, and one input/output command from the software. The program is designed to allow data transfer using buffers A and B without causing a termination interrupt to the software until the data transfer of the required data length is completed in response to a start request.

FIG. 5 is a diagram showing in detail the configuration of the input/output control device 13 in the apparatus of the present invention shown in FIG. Next, the execution of the channel program shown in FIG. 4 will be explained with reference to FIG. 5 as well as FIGS. 1 to 3. In this embodiment, a large amount of information generated by the input/output device ₁₆₁ connected to the port 14-1 is alternately transferred to buffers A and B (Fig. 3) existing in the main storage device 11, and data transfer is performed. A case will be described in which the software continues to process transferred data. Usually software instructions are stored in main memory 1
1, and the central processing unit 12 takes in software instructions from the main memory 11 through the bus d, and analyzes and executes them. Assuming that the software instruction just taken out is an input/output instruction, the central processing unit 12 sends the channel program address to the channel program address register 21 in the branch control unit 14 in the input/output control unit 13 through bus a, and executes the input/output instruction. Instructing the start of the output command word, central processing unit 12 continues executing other software instructions.

The input/output control device 3, which has been instructed to start the input/output command word, registers the channel program address register 2.
1 (in this case, address 1000 in FIG. 4), the first input/output command word is retrieved from the central storage device 11 through the bus b, and the command register 22 in the input/output control section 14, Information is set in the flag register 23, count register 24, and address register 25. When the input/output control device 13 determines that the R _EAD command has been issued and that the T&S flag is set to 1, the input/output control device 13 starts the decoder 2 from the contents of the address register 25.
The command e from 6 reads lock byte A (address is AAAA) through bus b, and reads 1 byte of lock byte data into data register 27.

When the determination circuit 27 determines that this lock byte data is all 0, it means that the buffer A is in a free state, and the input/output control device 13 determines the data length for the lock of the port 14-1.
An instruction to read LA is issued by command f, and an instruction is issued to all 1 generation circuit 29 to set the lock byte to all 1 by command g. All 1
When the generation circuit 29 receives the command g, it writes all1 to the software (AAAA) indicated by the address register 25 through the bus b, and instructs that the buffer A is busy. When the input/output control device 13 sets the buffer A to a busy state, the contents of the channel program address register 21 are incremented by 8 in the plus 8 circuit 30 of the branch control unit 15 according to the command h, and the data transfer performed using the command f is terminated. After that, preparations are made to start execution of the next input/output command word.

If the determination circuit 27 determines that the data of lock byte A present at the head of buffer A is other than all0, the input/output control unit 13 uses command i to notify the central processing unit 12 of abnormal termination after input/output command. The channel program run through bus a and shown in FIG. 4 will abort execution.

Input data from the input/output device ₁₆₁ is transferred to the buffer A of the main storage device 11 via the input/output control 14 and the bus b, but when the data with the data transfer length LA is transferred, the logic ₁₆₁ of the port is It issues a command j to the input/output control device 13 to notify the central processing unit 12 that the transfer to buffer A has been completed, and since the command chain flag (CC) = 1, it issues the next input/output. A command k is used to instruct the start of a command word.

When the central processing unit 12 is notified of the completion of the transfer to the buffer A from the input/output control device 13, it processes the data transferred to the buffer A in the main storage device 11 independently of the input/output control device 13. , the program is configured to set lock byte A to all 0 when data processing is completed. When command k instructs execution of the next input/output command, the input/output control unit 13 uses the contents of the channel program address register 21 to read the input from address 1008 of the main memory 11 in the same way as when reading the previous input/output command. The output command word is read and information is set in the command register 22, flag register 23, count register 24, and address register 25 of the input/output control device 13. The input/output command word at address 1008 is the 4th
As can be easily seen from the figure, the state of buffer B is judged by lock byte B, and if buffer B is free, data is transferred to address BBBB of main storage device 11 via port 14-1 for the length of data transfer length LB. It is something to do. Since buffer B is now free, the input/output control device 13 performs the same processing as the execution of the first input/output command word, and adds 8 to the channel program address using the plus 8 circuit 30 to end the transfer to buffer B. wait.

When the data with the data transfer length LB is transferred, the port logic 14-1 sends a command j to the input/output control device 13 requesting that the data in the buffer B become valid, and also sets the command chain flag CC. Since the value has become "1", command k is used to move to execution of the next input/output command word.

The input/output command word stored at address 1010 of the main storage device 11 is an unconditional branch input/output command word (UCB) that also constitutes the present invention, and is located at address section 1000.
Channel program address register 21
It has a function to set the This input/output command word also has the command chain flag CC set to 1, so the input/output control device 13
After the input/output command word is executed, the R _EAD input/output command word at address 1000 continues to be executed. In this way, the input/output device 13 successively executes the input/output command words in the main memory 11 in the order of → address 1000 → address 1008 → address 1010, and transmits the information generated in the input/output device 16 _1. The data is transferred alternately to buffer A and buffer B of the main storage device 11.

The input/output device ₁₆₁ notifies the port logic 14-1 that the transfer of all information generated by the input/output device ₁₆₁ has been completed, and the port logic 14-1 issues a series of input/output commands using the command l. Requests the central processing unit 12 to report the end of the word.

When the central processing unit 12 receives a report from the input/output control unit 13 that the data transfer from the input/output device 16 ₁ is completed, it becomes possible to send an input/output command to the input/output device 16 ₁ again.

Although the above explanation has been given for the input/output device ₁₆₁ , the same can be said for any of the other devices ₁₆₂ to ₁₆₄ , and the number of input/output devices is not limited to four. .

Furthermore, it goes without saying that the configuration of the branch control section 15, which is a characteristic component of the apparatus of the present invention, is not limited to that shown in FIG.

As explained above, the present invention provides an input/output device 1
By alternately using multiple smaller buffers without having the main memory have a buffer equal to the amount of information generated in step 6, efficient data transfer processing becomes possible. By providing a bit in the flag field that specifies that the buffer status is tested or set to a certain state, the configuration of the input/output command group becomes extremely simple, and it also simplifies the configuration of input/output command words that were previously defined as test and setting input/output command words. This greatly reduces the amount of hardware required for the input/output control device 13, which had previously increased due to

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a data processing device according to the present invention, FIG. 2 is a diagram showing the format of input/output command words used in the embodiment of FIG. 1, and FIG. A diagram explaining two data buffers set in the main memory, FIG. 4 is a diagram also showing a group of input/output command words, and FIG. 5 is a configuration of the input/output control device in the embodiment of the present invention shown in FIG. 1. FIG. Explanation of symbols: 11 is the main storage device, 12 is the central processing unit, 13 is the input/output controller, 14 is the input/output controller, 15 is the branch controller, 16 is the input/output device, 21 is the channel program address register, 22 23 is a command register, 23 is a flag register, 24 is a count register, 25 is an address register, 27 is a data register, 28 is an all 0 judgment circuit, 29 is an all 1 generation circuit, and 30 is a plus 8 circuit.

Claims (1)

[Claims] 1 A main storage device in which a series of input/output command words are stored, an input/output control device that controls execution of the input/output command words, and an input/output control device that controls the execution of the input/output command words based on the input/output command words. It has an input/output device that executes operations independently of the operation of the central processing unit, and means for notifying the central processing unit of the completion of execution of the series of input/output command words, and the input/output device and the main Testing a specific area that exists in the main storage device for synchronizing the central processing unit and the input/output control device during a data transfer type input/output command word that executes data transfer data between storage devices. The data is characterized in that it has a field specifying that the test is to be performed, and further includes means for instructing the start of data transfer or changing the execution order of subsequent input/output command words based on the result of the test. Processing equipment.