JPS62233842A - Memory interface circuit - Google Patents

Abstract

PURPOSE:To reduce the processing delay caused by the change of a higher order side address in a processing execution mode by making use of the ON/ OFF states of the flag produced from calculation of a lower order side address in an overflow mode to change the higher order side address. CONSTITUTION:When a muPD 7281 is used for data flow processors 21 and 22, a lower order side address is calculated by means of an addition or increment instruction. Then a flag bit can be turned on in an overflow mode. That is, a token is outputted as long as a flag showing the occurrence of an overflow of the lower order side address data in case a carry is sent to a higher order side address from the lower order side address. Then the increment of the higher order side address is possible by means of said flag.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory interface circuit that performs a write operation from a data flow processor to a memory.

[Conventional technology]

Conventionally, there is μPD7281 manufactured by NEC Corporation as a data flow processor. The μPD930 manufactured by NEC Corporation was used as a memory interface circuit in the arithmetic processing system using the previous i-video data flow processor.
There are 5. First, the memory access operation of the μPD9305 will be explained.

The μPD9305 performs data delivery and arithmetic processing using a data flow method, and the data output by humans is called a token.

A token is set data consisting of a data section, an identifier indicating the meaning of the data section, and a destination tag indicating the destination of the token.

For example, in the case of memory writing, there is a data part that is 11 write data, a write data token that has an identifier indicating that it is write data and a destination tag that indicates the destination is the memory interface circuit, and data that is the write lower side address. , a write lower fllJ address token having an identifier indicating that it is a write lower address, and a destination tag with the memory interface circuit as the destination, are input to the memory interface circuit in this order. The memory interface circuit has a plurality of data registers inside, and when a *write data token is input, the write data of the data section is set and held in the data register.

When the write lower address token is input, the memory interface circuit inputs the write data read from the data register to the memory, and the lower 9111 write address of the data portion of the lower write address token. A memory write command signal is output to instruct a write operation.

The memory executes the write operation according to the above instruction, and when the write operation is completed, returns an access completion signal to the memory interface circuit. The memory interface circuit receives this access end signal and ends the memory write operation.

In the case of memory read, a read lower address token having a data part which is a read lower address, an identifier indicating that it is a read lower address, and a destination address tag with the memory interface as the destination is sent to the memory interface circuit. input. The memory interface circuit outputs a memory read command signal using the data portion of the read lower address token as the lower address.

Instructs read operation.

The memory input performs a read operation according to the above instructions;
Ends the memory read operation.

The μPD9305 is further equipped with a read high address register and a write high address register for read operations and write operations as registers on the upper side of addresses, respectively, and the values to be set in these registers are used as the data part. , input of a read or write by address token containing an identifier indicating that it is an upper address or write address and a register number for selecting one of a plurality of read high address registers or write high address registers. and can be set in each of the corresponding high address registers.

When the read lower address token or write lower address token is input to the μPD9305,
The upper address is read together with the lower address from the read/write address register or write high address register selected by the destination tag or identifier, and is used as the address for accessing the memory. (
μPD9305This device allows μPD93o5tr
This represents the expansion of the memory address space using the s upper address.

[An intermediate point to solve the problem] For the conventional memory interface circuit, the upper address and the lower address are completely independent inputs. For example, if a token with a 16-bit data field is used, in a memory space where the upper address is in the range of 216 words, only the token with the lower address can read and write. When handling a memory space that is quite large, or when handling an area that spans different upper address spaces even if the space is smaller than 218 words, input the correct upper address to the memory interface circuit. The value of the read or write high address register had to be changed. For example, in a hexadecimal address, the upper 8 bits and the lower 16 bits are 2.
The next address after roOFFFFJ in the 4-bit address space is [010000J, and the upper address changes from "OO" to "01".

Conventionally, there are the following two methods for handling memory addresses that exceed areas with different upper addresses.

The first method is to change the upper address between the Nth and +1st memory accesses if the algorithm knows in advance that the upper address will be changed at the Nth memory access. This is to add a program.

The second method is, for example, when the number of memory addresses to be accessed increases monotonically, it is monitored whether the maximum value that can be expressed by the lower address has been reached, and if it has been reached, the next This is a method of changing the upper address before performing memory access. In the example of the data section of 16 and 7 above, when the address increases by 1, when the lower address is FFFFJ, the next access Before accessing the memory using the lower address ro OOOJ,
, the upper address is set to a value incremented by "1".

However, the first method described above has the drawback that the timing for changing the upper address varies depending on where in the memory space the starting address is set, and it is difficult to implement a general-purpose program. Even with the second method, programs must be programmed to constantly monitor the value of the lower address and to interrupt a series of processes to change the upper address, which increases the burden on software and This method had the disadvantage of causing processing delays.

The object of the present invention is to be able to create a program without being aware of changes in the upper address in memory access and write operations by the Cheetah Flow Processor, thereby reducing processing delays caused by changes in the upper address during processing execution. It's about doing.

[Means to solve the problem]

The configuration of the present invention is connected between a host processor, a plurality of Cheetah Flow processors connected in a ring shape, and a memory, and performs read/write operations on the memory in accordance with a token instruction input from the Cheetah Flow processor. In the memory interface circuit that executes, a data register that outputs write data to the memory, a write upper address counter register, a bladder output upper counter address register, and a lower address that outputs a lower address to the memory. a register, a memory access controller that controls access to the memory, write data obtained by the token according to instructions of the token input from the data flow processor, *input upper side address, output upper side address, and lower side. The address is set in each of the corresponding registers, and in the case of setting the lower address, the write upper (Il) address is further set according to the instruction of the input token.
It is determined whether or not to increment the 1 address register or the read upper address register, performs an increment operation, and sends 1 to the memory access controller.
7 A token input unit for instructing the start of the operation of writing in or issuing riS, and the writing device connected to the write upper address register and the bladder output upper side address register, and is set according to the write or read operation. It is characterized by comprising a multiplex length for selecting one of the upper address, Mf, and the output upper address and outputting it to the memory as the upper address.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In this figure, one embodiment of the present invention has an internal multi-breafter 24. Row address register 11° data register 13. Read high address counter register 12. Write high address counter register 14. Memory access controller 15. A memory interface circuit 10 consisting of a token input section 16, a token main formation section 171, a token output section 18. It consists of a host interface 19.

The memory interface circuit 10 has signal lines 100 and 1
11 to Cheetah flow processors 21 and 22, which are connected to each other by a signal 1112, respectively;
Signal lines 105, 106, 107 and 108 are connected to memory 20.

Various commands, data, etc. are exchanged from the host interface 19U and the host 10 set length 23 via the signal 1115, and data is sent from the token input section 16 via the signal line 103 to the host 10 via the signal line 115. Send to Setsa, and conversely signal fi from host 10 set length 23! The data input via signal line 115 is transferred to signal line 109.
is connected to the token output section via the .

The token input section 16ri outputs a signal via the signal line 100. If the destination tag of the input card does not indicate this memory interface circuit according to the signal 1113, the input token is sent as is to the token output section 18. When the identifier specifies a memory read operation on the signal line 104, a destination tag and an identifier for the read data are sent to the token generation unit 17.

The token generation section 17 generates a token by combining the memory read data input from the signal 1108 and the signal input from the signal 1104, and sends it to the token output section 18 via the signal line 11O.

The token output section 18 has signal lines 109, 110 and 11
If there is a token input from 3 and output via signal +9111, signal line 1 is sent to data flow-1079-21.
11. Token input section 16? When a token related to memory access is input, the information is sent to the memory access controller 15 via the signal line 101, and if the input token has an address value in the data section, the write high address is sent via the signal line 102. Register l 4 and IJ address register μ are set in a certain vhu row address register 11, and if it has a data value, it is set in the data register 13.

Memory access controller 15 is connected to memory 20 via signal line 105. Output of write high address register 14 and read no 1 address register 12
The outputs of are input to the multiplexer 24 through signal lines 114 and 116, respectively, and one is selected and output to the memo'J 20 through a signal line 107. Row address register 11
is connected to the memory by a signal line 106. The output of the data register 13 sends write data to the memory 20 via the signal line 108, but in a read operation, no data is output from the data register 13 to the signal line 10B. signal#
i! 108 is connected to the token generation unit 17, and read data from the memory 20 is transferred thereto.

The upper address value and register number are input from the token input section 16 via the read high address counter register 12, write high address counter register 14ri, and signal 8102. The consecutive high-order 1 address and the write high-order address outputted via the signal lines 116 and 114 are selected by the multiplexer 24 according to the read operation and the write operation, and are outputted to the memory 20 via the signal line 107.
is output to. Here, of course, a selection circuit using a high impedance circuit may be used instead of the multiplexer 24.

The emptying operation and writing operation of the memory 20 will be explained below.

A token is a set of data consisting of a data section, an identifier indicating the meaning of the data section, and a destination tag indicating the destination of the token.

For both memory write and memory read operations, a data portion that is a write upper address or a read upper gJ0 address, an identifier indicating whether it is a write upper address or a continuation upper address,
A write upper address token or an indulgence upper address token having a destination tag and register number destined for the memory interface circuit decodes the memory destination tag, identifier, and register number, and connects the signal line. 102, the value of the data portion is set in the counter register corresponding to the register number among the write high address counter registers 14. Here,
A counter register is a register that can be set with any value, operates as a counter, and has the function of incrementing the set value.

When a read upper address token is input, a value is set in the read high address counter register 12 via the signal line 102, as in the case of a write upper address token.

Specifically, the register number may be the value of the destination tag as it is, a part of the identifier, or a combination of the destination tag and the identifier. In the case of memory writing, the data section is write data, an identifier indicating that it is write data, a write data token that has a destination tag and register number with the memory interface circuit as the destination, and a write lower address. A write lower address token having a data portion, an identifier indicating that it is a write lower address, a destination tag with the memory interface circuit as the destination, a register number, and a flag is sent as a signal to the memory interface circuit 10 in this order. Input from fM100. When the write data token is input, the token input section 16
decodes the destination tag and identifier of the input data, and the data including ■ in the data part is sent to the token input part 1.
6 to the register specified by the register number of the data register 13 via the signal line 102.

Next, when the write lower address token is input,
The token input section 16 receives the signal i! The write lower address of the data portion of the save address token is set in the row address register 11 via signal m102, and a memo IJ fF write command signal is sent to the memory access controller 15 via signal m101.

The memory access controller 15 outputs the data corresponding to the data register 13 from the register number in the write lower address token to the signal line 108, and uses it as write data to the memory 20.

The write high address counter register 14 increments the write high address counter register 14 corresponding to the register number if the flag of the write lower address token is ON, and does not increment if the flag is OFF.

Thereafter, the write upper address is output from the signal line 114 to the signal line 107 via the multiplexer 24, and the signal line 106 outputs the write upper address to the row address register 11.
The memory 20 is addressed along with the write lower address from.

Next, the memory access controller 15d sends a memory write control signal to the memory 20 via the signal line 105.
After executing the write operation and receiving an access end signal from the memory 20 via the signal line 105, the memory interface circuit IO ends the write operation.

μPD72 as data flow processor 21.22
When 81 is used, the lower it'11 address can be calculated using an addition instruction or an increment instruction, and the flag bit can be set to -1 ON upon overflow. (μPD7281 User's Manual) ~l
-877B Japan 1. In other words, if there is a carry from the lower address to the upper address, a token whose flag indicating that an overflow has occurred in the lower address data is ON is output.
The upper address can be incremented using the flag.

Similarly, in the case of memory reading, the memory has a data section which is a lower read address, an identifier indicating that it is a lower read address, a destination tag, a register number, and a flag indicating that the memory interface circuit is the destination. When the read lower address token is input to the memory interface circuit 10, the read lower address of the data section of the bladder output lower address token is input to the token input section 16 of the memory interface circuit 10 via the signal line 102. It is set in the row address register 11 and a memory read command signal is sent to the memory access controller 15 via the signal line 101.

Read high address counter register 1.2fl If the flag is ON, the read high address counter register 12 for the register number is incremented, but if it is OFF', it is not incremented.

The output of the read high address register counter 12 is g
Branch line 116. Multiplexer 24. M is inputted to the memory 20 as a read address via the signal line 107 together with the output via the signal line 106 of the row address register 11, and is outputted from the memory access controller 15 to the signal line lO5 at a = memory read control signal. An ejecting operation is performed. When this is completed, the read data from the memory 20 is input to the memory interface circuit 10 via the signal 1102 and sent to the token generation section 17. Further, an access end signal is sent back from the memory 20 to the memory access controller 15 via the signal line 105, and the memory read operation is ended.

The token generation unit 17 uses the successive data sent through the signal line 108 as a data part, and combines a destination tag indicating the destination of the read data inputted from the signal line 104 with an identifier indicating that the data is read data, etc. A token is formed and sent to token output 18 via signal line 110.

〔Effect of the invention〕

As explained above, in the present invention, the upper address can be changed by calculating the lower address and using the ON and OFF of the flag that occurs when an overflow occurs, so the program can be programmed without being aware of the change in the upper address. can be created,
This has the effect of reducing processing delays caused by changes in higher-order addresses during actual execution.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 10... Memory interface circuit, 11. . 10. . Low address register, 12... Read high address counter register, 13... Mark/data register, 14... Write high address counter register, 15... Memory access controller, 1
6. Mountain... Token input section, 17... Token generation section, 18... Token output section, 19...
...Host interface, 20...Memory, 21.22...Data flow-10 length,
23...Host processor, 24...
Multiplexer % 100-116...Signal line. ,'--\ Agent: Patent attorney Hi-ichi Uchihara.

Claims (1)

[Claims] a memory interface circuit that is connected between a host processor, a plurality of data flow processors connected in a ring, and the memory, and executes a read/write operation to the memory according to a token instruction input from the data flow processor; , a data register that outputs write data to the memory, a write upper address counter register, a read upper counter address register, a lower address register that outputs a lower address to the memory, and an access register for the memory. and a memory access controller that controls the memory access controller, and sets the write data obtained by the token, the write upper address, the read upper address, and the lower address to the corresponding registers according to instructions of the token input from the data flow processor. However, in the case of setting the lower address, it is further determined whether or not the write upper address register or the read upper address register is to be incremented according to the instruction of the input token, and the increment operation is performed. A token input section that instructs the memory access controller to start a write or read operation, and a token input section that is connected to the write upper address register and the read upper address register, and that is set according to the write or read operation. 1. A memory interface circuit comprising: a multiplexer that selects either a read upper address or a read upper address and outputs the selected upper address to the memory as the upper address.