JPH01234957A - Method and device for controlling dma - Google Patents

Abstract

PURPOSE:To make DMA control efficient and to reduce the overhead of a control device by executing memory access based on an FiFo format, and at the time of arriving at the previously determined number of accesses, executing interruption processing for DMA end. CONSTITUTION:At the time of direct memory access (DMA) operation, a DMA operation means 3 outputs a source address, a destination address and length data to a main memory 2 based on a first in first out (FiFo) format. The operation means 3 stores the number of times of DMA, and when the number of times of DMA reaches the previously determined number of accesses, outputs a DMA end interruption. Consequently, DMA control can be efficiently executed and the overhead of the control device can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Summary) The present invention relates to a DMA control method and device, and aims to efficiently perform DMA control and reduce overhead of the control device. and a means for storing the number of DMA executions and controlling input/output operations to the register based on the stored contents, the memory is accessed in FiFo format, and when a predetermined number of accesses is reached, the DMA is executed. End interrupt processing is now performed.

[Industrial application field]

The present invention provides a DM for performing direct memory access (DMA) to a main memory in an information processing device.
A. This relates to a control method and device.

(Prior art) For example, a control adapter for establishing data transfer between a host CPU and a disk device that is an Ilo.
2. Description of the Related Art In recent years, devices that perform a series of processes in response to commands from a CPU have often adopted a method of performing DMA on a main memory in order to obtain various data for program execution. An example of a DMA control device using such a method is shown in FIG. 4, for example. This consists of a CPU 1 that performs various arithmetic processing according to predetermined programs, a main memory 2 that stores various data including CPU operation programs, and a DMA operating device that performs direct memory access (hereinafter referred to as DMA) to the main memory 2. 3, and a bus 8 serving as a data transfer path between the CPU 1, main memory 2, and DMA operating device 3. DMA operating device 3 is DM
An I10 boat 5 serves as a data entry/exit between the DMA control unit 4 that controls the A operation and an external device, and a local memory 6 that stores DMA operation programs and data.
A microprocessor 7 that operates and controls each of the operating sections.
(hereinafter referred to as MPU) and a bus 9 serving as a data transfer path between these operating units.

Conventionally, the DMA control unit 4 performs a direct memory access operation using an address register 10 in which a source address and a destination address are temporarily stored, and a length register 11 in which a processing data length is stored, as shown in FIG. It is composed of a DMA operating section 12. Then, a source address and a destination address are set in the address register 10 by the program operation of the MPU 7. Further, the MPU 7 issues a DMA activation instruction to the DMA operation unit 12. Accordingly, from the DMA operation unit 12 to the address register 10
A carry instruction is issued to the length register 11, and the address register 10 is sent to the main memory 2 through the bus 8.
Hair address information is output. Further, a bus control signal is outputted from the DMA operating section 12 onto the bus 8. As a result, a direct memory access operation for a specific address is performed, and when this is completed, an access operation completion notification is output from the length register 11 to the DMA operation unit 12. In this way, in MA control, data regarding the source address, destination address, and length are stored in the main memory 2 by a program executed by the CPU 1 as shown in FIG. If the main memory 2 is stored for operation and for the second direct memory access operation, when an operation instruction is given to Ilo from the CPU, Ilo imports the contents of main memory 2 into local memory 6 and imports them. MP data
U7 is set in each register 10.11.

Then, when the DMA is performed sequentially and the final direct memory access operation is performed, the MPU 7 determines the end when it sets the end flag (for example, the counter value is defined as °O゛) in the DMA length counter, and the CPU
1 is notified of the termination.

The operation of the MPU 7 during such processing is shown in FIGS. 7 and 8. FIG. 7 shows the DMA control operation of the MPU 7. When the DMA control operation is started, the MPU 7 sets an address (for example, the address corresponding to the first time in FIG. 6) and a length in the address and length register 10 in a processing step (hereinafter simply referred to as step) STI, and then In step ST2, a DMA activation instruction is given to the DMA operating section 12. Then, the main memory 2 is accessed by the operation of the DMA operating section 12, and data at the accessed address is read or data is written. During this memory access operation, the MPU 7 performs step S
The process moves to T3, and it is checked whether the first memory access operation due to the previous startup has been completed, and when the completion of the operation due to the interrupt routine due to the end of DMA is detected, the process goes to step S.
All DMs that have moved to T5 and are chained as shown in Figure 6
Check whether A is finished. If it is determined that the DMA is not completed, the process returns to step STI and the second DM is performed.
A operation is started. Then, the address corresponding to the second time in FIG. 6 is set in the address register 10, and then the processing from step S72 onwards is performed. In this way,
The processing operations of steps STI to ST5 are repeated, and when the final DMA operation is performed, the end flag 13 is read from the local memory 6. In step ST5, the MPU 7 uses the end flag 13 to
It recognizes the end of MA and ends the DMA operation. In the interrupt routine, in step ST6, it is checked whether each DMA operation has been completed normally, and the status of each functional section of the DMA operating device is also checked. If it is determined that the process has ended normally, step ST7
The interrupt cause is reset, the DMA end flag is set, and the interrupt routine ends.

(Problem to be Solved by the Invention) However, in such conventional DMA control, an end interrupt is raised every time one DMA operation is completed during DMA operation, and the next DMA address is determined. Since the registers 10 and 11 are reset, there is a problem in that the overhead is large.

The present invention has been made in view of such problems, and its purpose is to efficiently perform DMA control and reduce the overhead of the control device.

[Means to solve the problem]

FIG. 1 is a diagram showing the basic configuration of the present invention. In this figure, 20 indicates a DMA control section incorporated in the DMA control device shown in FIG.

Reference numeral 21 indicates an address register group, and this address register group is composed of a plurality of registers such as R1, R2, . 22 indicates a length register group. Further, 23 indicates a DMA operation unit that performs DMA processing, and 24 indicates a bus serving as a transport path for address information.

The DMA operating unit 23 receives a DMA activation instruction from the MPU 7, and also issues a DMA termination notification to the MPU 7. Further, this DMA operation section 23 includes registers R2, . . .
While outputting an instruction to write address information to Rn and length register 22, a carry instruction is issued to register Rn and length register 22 at the final stage, and a notification of completion of the access operation is received from length register 22. First stage register R1 in address register group 21
Address information is set by the MPU 7 through an address bus.

[Effect]

The MPU 7 sequentially outputs a plurality of address data of the main memory 2 to be DMA'd to the address register group 21. In the address register group 21, a plurality of pieces of address information are sequentially shifted and stored from the first stage register R1 to the last stage register Rn according to a first-in, first-out format. Then, DM from the MPU 7 to the DMA operating section 23
When the A start instruction is issued, the DMA operating unit 23 issues a carry instruction to the final stage register Rn and length register 22, outputs the address information stored in the final stage register Rn onto the bus, and Access the corresponding address on memory 2. When this access operation is completed, the length register 22 outputs an access operation completion notification to the DMA operation unit 23. Then, the DMA operating section 23 issues a write instruction to the registers R2, . . . Rn. As a result, the address information stored in each register is R1-+R2, R2-+R3,...Rn-1-+Rn
In the end, the address information is shifted by one stage. In this way, access operations by DMA are performed sequentially until the last address is output. Then, when the last address is output and the access operation to the corresponding address on the main memory 2 is completed, the DMA
A DMA end notification is output from the operation unit 23, and the interrupt routine processing operation is performed based on this. After the interrupt routine ends, the series of DMA operations ends.

〔Example〕

FIGS. 2 and 3 are diagrams showing an embodiment of a DMA control device according to the present invention and an example of its operation.

In this embodiment, the source address register, destination address register, and length register are all set in the FiFo format as register groups 25 and 26.
．． It is composed of 27. Then, a plurality of pieces of data of each address and length are outputted from the MPU 7 to these register groups 25, 26.27, and these data are sent to each register of each register group 25, 26.27 via FiF.
Written and read in o format. Also, each register group 25
, 26, 27 have respective register groups 25 on their output sides.
, 26, 27 are set to set registers 28, 29, and 30. The outputs of the set register 28 for setting the source address and the set register 29 for setting the destination address are output to the multiplexer 31, while the output of the set register 30 for setting the length is sent to the DMA as an end notification.
It is output to the operating section 23. Count-up signals a and b are output from the DMA operating section 23 to the set registers 28 and 29, respectively, while a count-down signal C is output from the DMA operating section 23 to the set register 30. Further, a select signal d is outputted from the DMA operation section 23 to the multiplexer 31, and a source address or a destination address is selectively outputted to the main memory 23.
is accessed. Furthermore, a path sequencer 32 is connected to the DMA operating section 23 and controls the bus 9. In addition, as described in relation to FIG.
, ---RSn, RDI, ---RDn, RL
I.

. . . In order to instruct RLn to write in the FiFo procedure, the DMA operation unit 23 sends each register group 25, 26 .
Write instruction signal lines 33, 34, and 35 are connected to 27.

The operation of the DMA control device having such a configuration will be explained based on the flowchart of FIG. 3.

In this case, the array chained D shown in FIG.
Assume that the number of MAs is greater than n registers. When the DMA control operation is started, the MPU 7 sequentially sets a plurality of addresses or lengths in each register group 25, 26, and 27 in the FiFo format in step 5TII, and sets all addresses,
After setting the length, in step 5T12
A DMA activation instruction is given to the MA operating section 23. Then, the first DMA operation is performed by the operation of the DMA operation unit 23, and in each register group 25, 26, and 27, information on each address or length is first output from the first register RSn, RDn, and RLn, and then sent to the set register 2.
They are stored at 8°29.30, respectively. Thereafter, the main memory 2 is accessed by the control operation of the MPX 31 by the DMA operating section 23, and data at the accessed address is read or data is written. D.M.A.
When the operation unit detects that the transfer for the set length has been completed and the operation has ended, it continues executing the DMA. In this processing step, the DMA operating unit 23 rewrites and shifts the data stored in each register group 25, 26, 27 based on the completion notification from the length register group 27 side (that is, the set register 30). let As a result, for example, in the source address register group 25, the data stored in register R5n-1 is newly written to register R3n, and the data in register R31 is subsequently written to R32 through sequential shifting. . The same applies to the other register groups 26 and 27. Then, a second DMA operation is performed and the main memory 2 is accessed. When the DMA operation is repeated in this manner and all data has been output from each register group 25, 26, 27, a completion notification is output from these registers. When the MPU 7 determines in step 5T14 that the DMA has ended as a result of processing the interrupt routine of FIG.
If A is not completed, return to step 5TII, set the address and length, and start DMA. In the processing of this interrupt routine, processing similar to that shown in FIG. 8 is performed.

〔Effect of the invention〕

As explained above, according to the present invention, when performing a DMA operation, Fi is stored in the register by processing all the address information necessary for the DMA operation 1/n times.
Since data is stored in the Fo format and multiple stages of DMA processing are performed continuously, it is possible to reduce the overhead caused by interrupts from the MPU, etc. that control DMA operations, and this has the effect of improving DMA work efficiency. can get.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is an embodiment of the invention, FIG. 3 is a flowchart showing the operation of the embodiment, and FIG. 4 is a DMA control device to which the present invention is applied. The block diagram shown in FIG. 5 shows the DMA in the DMA control device.
A block diagram showing a conventional example of a control unit, FIG. 6 is a diagram showing a conventional storage state of addresses and lengths in memory,
FIG. 7 is a flowchart showing the operation of a conventional DMA control device, and FIG. 8 is a flowchart showing the contents of the interrupt routine in FIG. 1...CPU 2...Main memory 3...DMA operation means 7...MPU (control means) 20...DM
A control unit 23...DMA operation unit 25...Source address register group 26...Destination address register group 2
7...Length register group 28.29.30...Set register 20 (DMA SE) The principle of starting θ, I also go to one Figure 1 τ・IA or Luciha xJa (ll) - Misfire +] Flowchart showing the movement of example 8 ↑-T3
FA DMA% Vm %, i = bridge relation block, Figure 2, Figure 4
Ku I Shiba + - A 11 - Oriri DMA γ Figure 8 Figure 6 Figure 7 Figure 8

Claims (2)

[Claims] (1) An information processing device comprising an arithmetic processing unit, a main memory, and an operating means for performing direct memory access to the main memory, wherein the DMA operating means includes:
During DMA operation, the source address, destination address, and length data are output to the main memory in a first-in, first-out format, and the operating means stores the number of DMA operations and performs predetermined access. A DMA control method characterized by raising an interrupt for completion of direct memory access when a specified number of times is reached. (2) Arithmetic processing unit (1), main memory (2), and D
An information processing device comprising an MA operating means (3),
The DMA operating means includes a DMA control unit (20) that controls access to the main memory, and a plurality of registers (25, 26,
27), and means (7) for storing the number of DMA executions and controlling the DMA control unit and register based on the stored contents.
), A DMA control device characterized in that it is provided with: