JPS62221059A - Central processing unit - Google Patents

Abstract

PURPOSE:To eliminate the calculation of the data number before the transfer of these data by allocating the terminate data to an internal register in a repeating data transfer instruction and executing the next instruction when the transfer data is coincident with the terminate data. CONSTITUTION:The transfer data is compared with the terminate data on a terminate data register 35 by a comparator 4. Then the comparator 4 outputs no coincidence signal when no coincidence is obtained between both data. At the same time, the data on a temporary register 34 is written to the destination address of an external memory under the control of an address bus control part 6 and a data bus control part 7. Such the transfer of data is repeated by the operation performed by an arithmetic part 2 under the control of a central control part 8. Then the comparator 4 outputs the coincidence signal when the coincidence is obtained between the transfer data and the terminate data. When this coincidence signal is outputted, the part 8 executes the next instruction as soon as the execution is through with a data transfer instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a central processing unit, and more particularly to a central processing unit that reduces the effort of a data transfer program.

[Conventional technology]

As a conventional central processing unit, there is one shown in FIG. 4, for example. This central processing unit 1 includes an arithmetic unit 2 that performs predetermined calculations to be described later, address registers 31 and 32 to which source addresses and destination addresses of transfer data are assigned, a transfer number setting register 33 to which the number of data transfers is set; and a register group 3 including a temporary register 4 for temporarily holding transfer data, etc.
(consisting of general-purpose registers), an address bus control unit 6 that controls the address of an external memory (not shown) based on the source address and destination address, and transfer of data held in the temporary register 34. , and a central control section 8 that controls the internal circuits described above.

The operation of the above configuration will be explained based on the time chart of FIG.

First, the number of repeated data transfers is set in the transfer number setting register 33. Next, the source address and destination address of the transfer data are assigned to the source address register 31 and the destination address register 32, and the data is transferred from the source address of the external memory under the control of the address bus control unit 6 and the data bus control unit 7. Data is read and held in the temporary register 34. The held transfer data is written to the destination address of the external memory under the control of the address bus control section 6 and the data bus control section 7. Based on this write operation, the calculation unit 2 subtracts 1 from the number of times set in the transfer circuit setting register 33. In this way, data is repeatedly transferred from the source address of the external memory to the destination address based on the arithmetic operation of the arithmetic unit 2 performed under the control of the central control unit 8. When the set value of the transfer count setting register 33 becomes 0 due to this repeated data transfer, the central control unit 8 instructs the end of the data transfer and the next command.

[Problem that the invention seeks to solve]

However, with conventional central processing units, when transferring data whose length is not constant, it is necessary to calculate the number of data and set the number of transfers before transfer, which reduces the effort of programming. There is an inconvenience that it takes.

For example, display data to be transferred to a display device (for example, AS
Since many messages (such as messages based on CII data) have an arbitrary length, the above-mentioned disadvantage occurs.

[Means for solving problems]

The present invention has been made in view of the above, and provides a central processing unit that allocates termination data in a repeated data transfer instruction to an internal register, and executes the next instruction when the transfer data matches the termination data. It is something.

The central processing unit according to the present invention will be explained in detail below.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and the same parts as in FIG. 4 are indicated by the same reference numerals, so redundant explanation will be omitted. Register group 3 sets termination data in a data transfer instruction. In addition, a comparator 4 is provided to compare the termination data in the termination data register 35 and the transfer data in the temporary register 34.

In the above configuration, the operation thereof will be explained based on the time chart of FIG. 2 and the flow chart of FIG. 3.

First, the termination data in the repeated data transfer command is set in the termination data register 35.

Next, when the source address of the external memory to which the transfer data is stored and the destination address of the external memory to which the transfer data is transferred are assigned to the source address register 31 and the destination address register 32, the address bus controller 6 and the data Transfer data is read from the external memory under the control of the bus control unit 7 and is held in the temporary register 34. This transfer data is compared with the termination data of the termination data register 35 in the comparator 4, and when the two do not match, the comparator 4 does not output a match signal, and the address bus control section 6 and data bus control section 7 Based on the control, the data in the temporary register 34 is written to the destination address in the external memory. Such data transfer is repeatedly performed by the calculation of the calculation unit 2 under the control of the central control unit 8,
When the transfer data matches the termination, the comparator 4 outputs a match signal. When the coincidence signal is output, the central control unit 8 executes the next command upon completion of the data transfer command.

〔Effect of the invention〕

As explained above, according to the central processing unit of the present invention, the next instruction is executed when the transfer data matches the terminate data. There is no need to calculate , and the time and effort required for programming is eliminated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a time chart diagram of the present invention. FIG. 3 is a control flowchart of the present invention. FIG. 4 is a block diagram of a conventional central processing unit. FIG. 5 is a time chart diagram of a conventional central processing unit. Explanation of symbols 1 -------- Central processing unit 2 -------
---Arithmetic unit 3----Register group
4-----Comparator 6--Address bus control section? −−−−−・−・Data bus control unit 8−−−−−・−・Central processing unit

Claims (1)

[Claims] An address register to which a source address and a destination address for repeated data transfer instructions are assigned, and a temporary register for temporarily holding transfer data, and the data at the source address is taken into the temporary register. in a central processing unit that transfers data from a data transfer command to a destination address, a termination data register to which termination data in a repeated data transfer instruction is set, and a termination data register to which termination data is temporarily held in the temporary register and which are set to the termination data register. a comparison circuit that outputs a data match signal when the data matches the terminated data; and a control means that commands the termination of data transfer based on the data match signal. Processing equipment.