JPH09146877A - Inter-memory data transfer controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the efficiency of transfer between memories even when the addresses of the memories are misaligned. SOLUTION: Two read buffers 41 and 42 are provided which store data of single-time access units of a source-side memory. If the address of the source- side memory is misaligned, a transfer control part 44 stores the misaligned part in one read buffer 41 and a next aligned part in the other read buffer 42. Further, the transfer control part 44 recomposes the data in the read buffers 41 and 42 so that the address is aligned with the address of a destination-side memory, and stores the data in a write buffer 43, thereby performing writing to the destination-side memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-memory data transfer control device for controlling data transfer between memories in a computer system.

[0002]

2. Description of the Related Art The conventional data transfer between memories in a computer system is constructed as follows. For example, in a computer system having a 32-bit data bus, a transfer is performed in units of 4 bytes, and a register (hereinafter, simply referred to as a register) that stores 4 bytes of data in a memory (hereinafter, referred to as a source side memory) that is a transfer source. Is used to read data from the source memory, store 4 bytes of data in the register, and then write the data to the transfer destination memory (hereinafter referred to as destination memory). It was

[0003]

However, in the above conventional memory transfer, since 4 bytes is a transfer unit,
When data is read from the source side memory or written to the destination side memory, if the memory address is aligned with 4 bytes, both read and write cycles are executed once, but in the case of misalignment There was a problem that it was necessary twice and transfer time was long.

From such a point, it has been desired to realize an inter-memory data transfer control device capable of improving the transfer efficiency between memories even when misaligned.

[0005]

The present invention employs the following structure to solve the above-mentioned problems. <Structure of Claim 1> In the inter-memory data transfer control device of the present invention, in the inter-memory data transfer control device for performing direct memory access control between the source side memory and the destination side memory, 2 read buffers for storing the data of each read access unit, a write buffer for storing the data of one write access unit to the destination memory, and a source for the two read buffers. While storing different data from the side memory in units that match the read address alignment,
It is characterized by including a transfer control unit that rearranges the data of the two read buffers and stores them in the write buffer so as to match the alignment of the write address to the destination side memory. .

<Explanation of Claim 1> When the read address of the memory on the source side is misaligned, the transfer control section first sets the misaligned portion to one of the two read buffers. Store and store the next aligned data in the other read buffer. Then, the transfer control unit rearranges the data of the two read buffers so as to match the write address alignment of the destination side memory,
The data is stored in the write buffer. Then, the data stored in the write buffer is written to the destination memory in one access unit.

As a result, when the transfer data is one access unit × n (n = 1, 2, ...), the number of read / write accesses to the memory is n + 1. . In addition, the data amount of one access unit is
For example, the value is 4 bytes, but the same effect can be obtained with a value larger than this.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. <Structure> FIG. 1 is a block diagram showing a concrete example of the inter-memory data transfer control device of the present invention. In the system shown in the figure, a DMAC (Direct Memory Access Controller) for performing data transfer between two independent buses is arranged between the buses, and a CPU (Central Processing Unit) provides address, data and control buses. 2 shows a configuration relating to data transfer between memories of a computer system that controls each device and performs data processing via the device.

The system shown in FIG.
(Central processing unit) 4 and inter-memory data transfer control unit 4. The memory 1 and the CPU 3 have an address bus 101,
The memory 2 is connected to the data bus 102 and the control bus 103, and includes the address bus 201 and the data bus 20.
2. Connected to the control bus 203. Also,
The inter-memory data transfer control device 4 is connected to these address buses 101 and 201, data buses 102 and 202, and control buses 103 and 203.

The memory-to-memory data transfer control device 4 is a CPU
3 is a direct memory access controller (DMAC) that performs data transfer between memories, and includes read buffers 41 and 42, a write buffer 43, and a transfer control unit 44. The read buffers 41 and 42 are
Each of the buffers is a buffer for storing data for one access unit of the source side memory.
It is in bytes. The write buffer 43 is a buffer for storing data for one access unit (4 bytes) of the destination memory. Further, the transfer control unit 44 takes out 4 bytes of data from the memory on the source side and stores the data in the read buffers 41 and 42, and based on the address of the memory on the destination side, the data in the read buffers 41 and 42 is read. It has a function of rearranging in byte units, storing 4-byte data in the write buffer 43 so as to match the write address alignment of the destination side memory, and transferring it to the destination side memory.

<Operation> Next, the operation of the inter-memory data transfer control device having the above configuration will be described. For example, when data is transferred from the memory 1 (source side memory) to the memory 2 (destination side memory), the transfer data is transferred to the read buffers 41 and 42 via the data bus 102 by the route shown by the broken line 11. Is stored. And
The transfer control unit 44 rearranges the data with respect to these data, and the write buffer 43 is routed along the route indicated by the solid line 12.
In the data bus 2 along the route indicated by the broken line 13.
Write to memory 2 via 02. On the other hand, memory 2
To transfer data from (source-side memory) to memory 1 (destination-side memory), the chain line 14
The data is stored in the read buffers 41 and 42 by the route indicated by, the data is rearranged, stored in the write buffer 43 by the route indicated by the solid line 12, and written in the memory 1 by the route indicated by the alternate long and short dash line 15.

2 and 3 are explanatory views showing the operation of this example in comparison with the conventional one. In the figure, a shaded block portion indicates a data transfer execution unit on the memory, and one block is 1 byte. The transfer data is 4 × n
Bytes (n = 1, 2, 3, ...).

The type a is a case where the addresses of the transfer data on the memory are aligned, and in this case, the operation is the same as that of the present example and the conventional one. That is, with one access, 4 bytes of access such as ABCD, EFGH, ..., WXYZ are performed.

On the other hand, as shown in types b to d,
If the transfer data on the memory is not aligned in units of 4 bytes (misalignment), the transfer control unit 44 first stores the first misaligned data in the read buffer 41. Next, the aligned 4-byte data is stored in the read buffer 42. For example, in the case of type b, the ABC part is first read and stored in the read buffer 41. Next, the DEFG section is read and stored in the read buffer 42. Therefore, if there are 4 × n bytes of transfer data, in this specific example, it is sufficient to read n + 1 times.

On the other hand, according to the conventional method, in the case of type b, the ABC part is first read, and then the D part is read in order to make it 4 bytes. And since such an operation is repeated, the access becomes 2 × n times.

Further, for example, when the source side address is a type c and the destination side address is a type b, which is a different type of alignment, the transfer control unit 44.
Stores the data in the write buffer 43 after rearranging the data in the read buffers 41 and 42. That is, since the source side address is of type c, A is stored in the read buffer 41.
The B section is stored, the CDEF section is stored in the read buffer 42, and the ABC section is first stored in the write buffer 43 so that the destination side address is aligned from these data, and this is written in the memory 2. next,
The GHIJ section is stored in the read buffer 41, and the data in the read buffers 41 and 42 is stored in the write buffer 43.
The EFG section is stored and written in the destination side memory. In this way, even if the address alignment of the source memory and destination memory is different,
Each of the memories 1 and 2 can be accessed only n + 1 times.

<Effect> As described above, in the present specific example, even when the transfer data on the memory is not aligned in units of 4 bytes, two read buffers 41 and 42 are set, so that separate data of 4 bytes is obtained. Can be read and stored, and data can be transferred only to the misaligned portion, and the read buffers 41, 42 can be read in byte units.
It is possible to store the write data of the destination memory in the write buffer 43 so as to be aligned in units of 4 bytes.
When the transfer data is 4 × n bytes (n = 1, 2, 3, ...), the number of read and write accesses to the memory is reduced by {2n− (n + 1)} × 2 = 2 (n−1). It is possible to improve the data transfer efficiency.

For example, when data transfer is performed in the case where the data arrangement of the source side memory is type b and the data arrangement of the destination side memory is type c with 32 bytes of transfer data, first, transfer data read access of the source side memory is performed. The number of times required was 64 in the conventional method, but in the present specific example, the number of times can be 33. As a result, in the present specific example, the number of read and write accesses required for data transfer can be performed 66 times, and the data transfer can be further improved as compared with 128 times in the case of the conventional technique.

In the above specific example, the case of data transfer in units of 4 bytes has been described, but the present invention is not limited to this, and for example, data transfer in units of 16 bytes in the case of a 64-bit bus, etc. The same effect can be achieved.

[0020]

As described above, according to the inter-memory data transfer control device of the present invention, even if the read or write address is misaligned, the inter-memory data transfer efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an inter-memory data transfer control device of the present invention.

FIG. 2 is an explanatory view (No. 1) showing the operation of the inter-memory data transfer control device of the present invention in comparison with a conventional one.

FIG. 3 is an explanatory view (No. 2) showing the operation of the inter-memory data transfer control device of the present invention in comparison with the related art.

[Explanation of symbols]

 1, 2 memory 4 data transfer control device between memories 41, 42 read buffer 43 write buffer 44 transfer control unit

Claims (1)

[Claims] 1. A memory-to-memory data transfer control device for performing direct memory access control between a source-side memory and a destination-side memory, for storing data for each read access unit to the source-side memory. Two read buffers, a write buffer for storing data of one write access unit to the destination side memory, and an alignment of the read address from the source side memory to the two read buffers The data stored in the write buffer is stored in the write buffer by recombining the data in the two read buffers so as to store different data in each unit and to match the alignment of the write address to the destination memory. It is equipped with a control unit And a data transfer control device between memories.