JPS63174157A - Microprocessor device - Google Patents

Abstract

PURPOSE:To selectively switch to the reciprocal two forms of the byte of data to be accessed at the time of accessing a memory by selectively switching and connecting a first and a second circuits between an internal and an external data buses. CONSTITUTION:A microprocessor (MPU) is constituted of 16 data buses of 16 bits and the data of the 16 bits is accessed for every access between the microprocessor and the memory 6. A first buffer circuit 1 is disposed between the internal data bus in the MPU and the external data bus and the data of the 16 bits is directly transferred to the memory 6 through the circuit 1. The second circuit is constituted of a byte swapper circuit 2 and a buffer circuit 3 and the byte array of the data of the 16 bits is inverted and the data is transferred to the memory 6. An instruction fed from the internal part of the MPU is decoded in a decoder 4 one of the circuits 1 or 3 is selectively turned on according to the contents of the instruction by a selection circuit 5.

Description

[Detailed Description of the Invention] [Summary] A first circuit includes an internal data bus that transfers data of multiple bytes, connects the internal data bus as it is to an external data bus, and a byte swapper circuit that connects the internal data bus. a second circuit connected to the external data bus via the
A microprocessor device selectively connected between the internal data bus and the external data bus, the microprocessor devices having different byte sequences of data accessed during memory access. data compatibility is ensured.

[Industrial application field]

The present invention relates to a microprocessor device, and more particularly to a microprocessor device configured to read data from or write multiple bytes of data (for example, 16-bit data) into memory.

[Conventional technology]

Conventionally, in this type of microprocessor device (for example, a 16-bit or 32-bit MPU), when data spanning multiple bytes is stored in memory (addresses are assigned in units of bytes), the data is moved from the lower address toward the upper address. There are two methods: one in which data is stored in order from the lower byte of the data, and the other in which data is stored in order from the upper byte of the data, and which method is adopted differs from processor to processor.

For this reason, data between different computer systems and peripheral ICs are not compatible (for example, if one type of MPU writes multiple bytes of data and another type of MPU reads the data, This incompatibility is absorbed by the software and external circuits (data with the reverse order is read), resulting in a decrease in system performance and an increase in the burden of software/hardware development. There was a point.

[Problem that the invention seeks to solve]

The present invention was made to solve this problem, and includes a hardware mechanism inside the MPU that reverses the byte order of data accessed when accessing the memory of the MPU, and transfers multiple bytes of data from the MPU to the memory. Store (or read multiple bytes of data from the memory)
In this case, it is possible to select and use the two storage methods (or reading methods) described above.

[Means for solving problems]

In order to solve the above problems, the present invention provides an internal data bus that transfers multiple bytes of data, and a first bus that connects the internal data bus directly to an external data bus.
and a second circuit that connects the internal data bus to an external data bus via a byte swapper circuit, the microprocessor device is selectively connected between the internal data bus and the external data bus. is provided.

[For production]

According to the above configuration, the first circuit and the second circuit are selectively connected between the internal data bus and the external data bus, so that bytes of data accessed during memory access are It becomes possible to selectively switch the arrangement between forward and reverse.

〔Example〕

FIG. 1 shows the internal configuration of a microprocessor device as an embodiment of the present invention, for example, a 16-bit MPU.
If so, 16 data buses are provided as internal data buses of the MPU, and 1 data bus is provided for each access to the memory U6 connected through 16 external data buses.
6 bits of data are accessed. Note that the address itself of the memory 6 is assigned in byte units.

Between the data bus inside the tgMpu and the external data bus, there is a buffer circuit 1 (a gate circuit that amplifies the data inside the MPU and outputs it to the outside of the MPU) and transfers 8 to 16 bits of data as is to the memory. In addition to the above circuit, a second circuit is provided which inverts the byte arrangement of the 16-bit data and transfers it to the memory through the byte swapper circuit 2 and the buffer circuit 3,
The command (instructing whether to transfer the 16-bit data as is or to invert the byte arrangement) sent from the inside is decoded by the command decoder 4, and the selection circuit 5 selects the above-mentioned Either the buffer circuit 1 or the buffer circuit 3 is selectively turned on depending on the content of the instruction.

Here, inside the byte swapper circuit 2, as shown in FIG. 2, connections are formed to invert the byte arrangement of the 16 data buses D0 to I)ts (that is, the arrangement of eight buses at a time).

In addition, as an instruction that involves memory access as mentioned above,
For example, there are two types of instruction codes for data read commands from memory: LD (reads 16-bit data from the memory as is) and LDX (reads 16-bit data from the memory with the byte order reversed). is prepared, and the command to write data to the cough memory is ST.
Two types of instruction codes are available: (writes 16-bit data into the memory as is) and 5TX (writes 16-bit data into the memory with the byte order reversed). When the instruction code LD or ST is sent to the instruction decoder 4, the buffer circuit 1 is turned on via the selection circuit 5;
When X or STX is sent, the buffer circuit 3 is turned on via the selection circuit 5. In other words, processing such as calculations is performed between registers inside the MPU,
Memory access is limited to read (LD) and store (ST)
) instructions, and there are two types of load and store instructions each (LD, LDX, ST
and 5TX), and is configured to selectively switch the connection between the MPU internal data bus and the external data bus so that both the forward and reverse byte arrangements described above can be handled.

By simply providing two types of load and store instructions in this way, it is possible to switch the byte order of multiple bytes of data within the MPU into two types of forward and reverse formats, thereby allowing multiple bytes of data to be stored in memory. Data stored by one MPtJ having a different storage format can be correctly read by the other MPU, and the data can be processed accurately and quickly.

〔Effect of the invention〕

According to the present invention, the byte arrangement of data accessed during memory access by an MPU can be switched between forward and reverse formats within the MPU, thereby improving data compatibility between MPUs that use different memory access formats. data processing can be performed accurately and quickly.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the internal configuration of a microprocessor device as an embodiment of the present invention, and FIG. 2 is a diagram illustrating the internal wiring of the soba circuit with bites shown in FIG. 1. (Explanation of symbols) 1.3: Buffer circuit, 2: Byte swapper circuit, 4: Instruction decoder, 5: Selection circuit, 6: Memory.

Claims (1)

[Claims] 1. A first circuit that has an internal data bus that transfers multiple bytes of data and connects the internal data bus directly to an external data bus, and a second circuit that connects the internal data bus to the external data bus via a byte swapper circuit. A microprocessor device characterized in that a circuit No. 2 is selectively connected between the internal data bus and the external data bus.