JPH05151150A - Computer data input/output device - Google Patents

Abstract

PURPOSE:To increase the data transfer speed in response to a high bit of a computer by making use effectively of the performance of a high-bit computer and at the same time to reduce the CPU load for the transfer of data. CONSTITUTION:A computer data input/output device is provided with an input/ output interface 10 which is connected to an internal bus 2 via an input/output data bus 9 of a smaller number of bits than the bus 2. Then the data input/ output device contains a higher order byte buffer 11 which is connected to the higher order bits of the bus 2 at one of both sides of the buffer 11 and connected to all bits of the bus 9 of the interface 10 at the other side respectively and at least two bidirectional latch buffers of a lower order byte buffer 12 which is connected to the lower order bits of the bus 2 at one of both sides of the buffer 12 and connected to all bits of the bus 9 at the other side respectively. Then the data input/output and latch operations of both buffers 11 and 12 are individually controlled by a buffer switch controller 14 with a given data transfer request.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data input / output device for a computer, and more particularly to a data input / output device for an input / output interface for data transfer with the outside.

[0002]

2. Description of the Related Art As a peripheral interface of a computer, an input / output interface for data transfer with the outside has been standardized and standardized in various modes. One of them is a parallel GPIB (General).
Purpose Interface Bus) is well known. GPI
B is due to the 8-bit bidirectional data bus,
It is a standard that can connect up to 15 devices,
It is used as a parallel input / output interface for various devices.

[0003]

As in the GPIB, the parallel input / output interface is based on an 8-bit data bus, whereas the computer CPU and internal bus are 16-bit, 32-bit, and high-bit. It is progressing rapidly. GP for such a high-bit computer
When a low bit parallel input / output interface such as IB is simply connected, the performance of a high bit computer is not sufficiently drawn out, and the data transfer rate does not improve regardless of the high bit of the computer. The load on the CPU for data transfer becomes high.

The present invention has been made by paying attention to the above-mentioned problems in the data input / output of the conventional computer, and it is possible to effectively use the performance of the high-bit computer and to increase the bit of the computer. The data transfer speed can be improved accordingly, and the CPU for data transfer
It is an object of the present invention to provide a data input / output device for a computer that can reduce the load on the computer.

[0005]

SUMMARY OF THE INVENTION According to the present invention, the above-described object is to input data of a computer to which an input / output interface of an input / output data bus having a smaller number of bits than the internal bus is connected. In the output device,
One is connected to the upper bit of the internal bus and the other is connected to the upper byte buffer to which all bits of the input / output data bus of the input / output interface are connected.One side is connected to the lower bit of the internal bus and the other side is input / output. At least two bidirectional latch buffers of the lower byte buffer connected to all bits of the input / output data bus of the interface, and the upper byte buffer and the lower byte buffer of the upper byte buffer and the lower byte buffer when a data transfer request is given from the input / output interface. The present invention is achieved by a data input / output device of a computer having a buffer switching controller for individually controlling data input / output and data latch operations by the upper byte buffer and the lower byte buffer.

[0006]

According to the above-described structure, either the upper byte buffer or the lower byte buffer performs data latch when inputting / outputting data to / from the input / output interface,
These function as a word buffer, absorb the difference in the number of bits between the internal bus and the input / output interface, and transfer the data between the internal bus and the input / output interface in one transfer cycle with the number of bits of the internal bus. To be done.

[0007]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows an embodiment of a computer equipped with a data input / output device according to the present invention. In FIG. 1, reference numeral 1 indicates a CPU, which is connected to a DMAC (Direct Memory Ac) by an internal bus (system bus) 2.
cess controller) 3, bus buffer 4, work RAM
5 and firmware EPROM 6 are connected.

An input / output interface 10, which is a peripheral LSI, is connected to the internal bus 2 via a word buffer 7 via an input / output data bus 9, and data transfer between a computer and external equipment is performed via this. It is supposed to be.

The input / output interface 10 is, for example, a GP.
Like the IB, it is based on an 8-bit data bus,
As a result, the input / output data bus 9 is naturally constituted by an 8-bit data bus.

On the other hand, the CPU 1 is composed of, for example, a 16-bit CPU, and accordingly the internal bus 2 is V
It is configured as a 16-bit data bus such as ME bus.

The DMAC 3 is composed of a 16-bit DMA controller and transfers data between the input / output interface 10 and the bus buffer 4 and work RAM 5 and between the bus buffer 4 and the memory space by direct memory access. ing.

The word buffer 7 is the upper byte buffer 1
1 and a lower byte buffer 12, and the upper byte buffer 11 and the lower byte buffer 12 are each constituted by a buffer with a bidirectional latch.

The upper byte buffer 11 is connected to the upper 8 bits of the internal bus 2 on one side and to all the bits of the input / output data bus 9 of the input / output interface 10 on the other side. The latch operation is performed, and the through state is selectively set.

The lower byte buffer 12 is connected to the lower 8 bits of the internal bus 2 on the one hand, and is connected to all the bits of the input / output data bus 9 of the input / output interface 10 on the other hand. In addition, the data latch operation is selectively performed, and the through state is selectively set.

The operations of the upper byte buffer 11 and the lower byte buffer 12 are individually performed by the buffer switching controller 13.

The buffer switching controller 13 is composed of a programmable logic array or the like, and has a CPU 1 and a DMA.
Control signals such as address strobe, read, write, and data strobe from C3 are input / output interface 10
When a data transfer request is given from the decoder, it is decoded, and the data transfer request is output to the DMAC 3 in accordance with a predetermined logic and at the same time, the latch timing, the bus open / close control signals are output to the word buffer 7, and the input / output interface is also used. Control signals for address strobe, read, write, data strobe, etc. are output to 10.

Next, the data input / output operation using the word buffer 7 operated by the control signal from the buffer switching controller 13 will be described.

First, data input will be described with reference to FIGS. In addition, in FIG. 2 and FIG.
Is the input / output interface 10 to the buffer switching controller 1
3 is a data transfer request to DMAC 3 and DREQ is a data read request from the buffer switching controller 13 to DMAC 3.

When the data transfer request is asserted from the input / output interface 10, the buffer switching controller 13 does not request the DMAC 3 to read data, and the input / output interface of the upper byte buffer 11 of the word buffer 7 is instructed. Only 10 side will open. As a result, the data from the input / output interface 10 is latched in the upper byte buffer 11. (See FIG. 2) Next, when the data transfer request is asserted again from the input / output interface 10, the buffer switching controller 13
Requests the DMAC3 to read data in word units. At this time, the internal bus 2 side of the upper byte buffer 11 is opened, the data latched by the upper byte buffer 11 is output to the upper 8 bits of the internal bus 2, and the input / output interface 10 of the lower byte buffer 12 is output. Side and the internal bus 2 side are both opened, the lower byte buffer 12 is in the through state, and the data output by the input / output interface 10 is output to the lower 8 bits of the internal bus 2. This allows DMA
C3 reads the data in the word buffer 7 in word units (see FIG. 3). That is, the data input for one word is completed. This is performed at the memory access timing of the DMAC3, and 1 by one access cycle
Data transfer for words will be performed. , The access of the input / output interface 10 is performed by the DMAC.
3 is not performed, the internal bus efficiency is improved as compared with the case where the input / output interface 10 accesses the DMAC 3 twice when transferring 1-word data.

There is a case where the assertion of the data transfer request from the input / output interface 10 is stopped, which is determined by the truth value of a predetermined bit of the device address register. In this case, the upper byte buffer is used. 11 leads are made. This makes it possible to capture the last data.

Next, data output will be described with reference to FIGS. 4 and 5. In addition, in FIG. 4 and FIG.
Is the input / output interface 10 to the buffer switching controller 1
3 is a data transfer request to DMAC 3 and DREQ is a data write request from the buffer switching controller 13 to DMAC 3.

When a data transfer request is asserted from the input / output interface 10, the buffer switching controller 13 requests the DMAC 3 to write data in word units. At this time, both the input / output interface 10 side of the high-order byte buffer 11 and the internal bus 2 side are opened, and the high-order byte buffer 11 enters the through state. First, only the high-order 8-bit high-order byte data of the internal bus 2 is transferred. The input / output interface 10 is transferred. On the other hand, the lower byte buffer 11 is opened only on the internal bus 2 side, and the lower 8-bit lower byte data of the internal bus 2 is latched in the lower byte buffer 12. (See FIG. 4) Next, when the input / output interface 10 reasserts the data transfer request to the buffer switching controller 13, the buffer switching controller 13 does not request the DMAC 3 to read the data, and the buffer switching controller 13 stores the data in the word buffer 7. The input / output interface 10 side of the lower byte buffer 12 is opened. As a result, the data latched by the lower byte buffer 12 is output to the input / output interface 10. (Refer to FIG. 5) When accessing the input / output interface 10 by the CPU 1 when reading or writing a program, for example, the lower byte buffer 12 is in a through state by the control of the word buffer 7 by the buffer switching controller 13. It can be performed without being aware of the word buffer 7.

[0024]

As can be understood from the above description, according to the data input / output device for a computer of the present invention, either the upper byte buffer or the lower byte buffer is used when data is input / output to / from the input / output interface. Performs data latch, these function as word buffers, absorb the difference in the number of bits between the internal bus and the I / O interface, and use the number of bits of the internal bus to establish the internal bus and I / O interface in one transfer cycle. Since the data transfer between the two can be performed, the performance of the high-bit computer is effectively used, the data transfer speed is improved according to the increase in the bit of the computer, and the CPU of the CPU for the data transfer is improved. The load will be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a computer including a data input / output device according to the present invention.

FIG. 2 is a time chart at the first stroke during data input in the data input / output device according to the present invention.

FIG. 3 is a time chart in the second stroke at the time of inputting data in the data input / output device according to the present invention.

FIG. 4 is a time chart of the first stroke during data output in the data input / output device according to the present invention.

FIG. 5 is a time chart at the time of the second stroke when outputting data in the data input / output device according to the present invention.

[Explanation of symbols]

 1 CPU 2 Internal bus 3 DMAC 4 Bus buffer 5 Work RAM 6 Firmware EPROM 7 Word buffer 9 Input / output data bus 10 Input / output interface 11 Upper byte buffer 12 Lower byte buffer 13 Buffer switching controller

Claims (1)

[Claims] 1. In a data input / output device of a computer, to which an input / output interface of an input / output data bus having a smaller number of bits than the internal bus is connected, the upper bit of the internal bus is connected on one side. On the other hand, the upper byte buffer to which all bits of the input / output data bus of the input / output interface are connected, and on the other hand to the lower bit of the internal bus and on the other side all of the input / output data bus of the input / output interface. At least two bidirectional latch buffers of lower byte buffers to which bits are connected, and data input / output and data latch operations of the upper byte buffer and the lower byte buffer given a data transfer request from an input / output interface. A buffer that controls the upper byte buffer and the lower byte buffer individually. Data input-output device of the computer, characterized in that it has a replacement controller, a.