JPS583054A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To remarkably reduce both the development cost and the development period, by using in common a terminal connected to an outer program memory, and a terminal connected to an external peripheral equipment. CONSTITUTION:The first input terminal 201 has an input/output port function and an output function of an address, the second input/output terminal 202 has an input/output port function and an output function of a control signal, and the third input/output terminal 204 has an input/output port function and an input/ output function of a data. A control signal 208 controls each part of the input/ output terminals 201, 202 and 204, a gate 206 and a multiplexer 207. In accordance with this signal 208, a CPU 100 reads out a program from an internal program memory 101, executes it, and executes switching as to whether the input/ output terminals 201, 202 and 204 are used as a regular port terminal, or the input/output terminals 201, 202 and 204 are connected with an outer program memory and are used.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a single-chip microcomputer that effectively uses external terminals. A single-chip microcomputer is one in which a central processing unit, data memory, program memory, and input/output devices are integrated on a single chip using L8I technology. A mask ROM is usually used as the program memory. This is a ROM in which a program to be built in at a stage is written. Therefore, it is impossible to modify or change this mask ROM. If it is necessary to modify or change the program, a new single-chip microcomputer must be created and the program modified during the snow manufacturing process must be rewritten into the mask ROM, which requires software development. Now, instead of mask ROM, we use RAM that can be freely modified and changed! There is a strong demand for the use of single-chip, micro-combi, and external devices, but conventional single-chip, micro-combi, and microcombi devices do not have the ability to attach the above-mentioned RAM externally. That is, external devices that replace the built-in program memory do not have the ability to read and execute programs from the memory. Therefore, the hardware has the same functions as the above-mentioned single-chip microphone 4 computer, and the external device uses an evaluation L8I chip (hereinafter referred to as Eva chip) that is created to read and execute programs from memory. I was doing software development. This conventionally used evaporator will be explained with reference to the configuration diagram in FIG. CPUI OOH Controls this entire Eva chip. Port 102, 103, 104゜105#1 CPU100
Input to each terminal using control.

The output can be set in both directions, and input/output data is exchanged with the outside of the EV chip via the I10 bus 106t. Addresses on the internal address bus 108 are transferred to the outside of the EV chip from the address bus terminal 107. A signal terminal 109 outputs a read control signal for an external memory. The data bus terminal 110 receives and receives instruction data read from an external memory, and the CPU 100 reads this instruction via an internal data bus. Here, address pin 107, read signal terminal 1
09゜Data bus terminal 110t! , External is a group of terminal functions added to read programs from memory, and its operation will be explained next in the original single-chip microcomputer. CPU100Fi data bus terminal 110.
Using the read signal terminal 1o9 and the address bus terminal 107, an external program is loaded from the memory and executed.

Also, under the control of the CPU 100, the boats 102, 103,
104.105 input/output settings, data output on I10 bus 106, baud') 102, 103, 104.10
5, the external data is inputted. This Ebachi.

Since the LSI receives a program from an external memory and executes it, it is necessary to add terminals for an address bus, data bus, and control signals, resulting in an LSI with a very large number of terminals. Therefore, in order to develop this EV chip, a new package with a large number of terminals must be created, which has the drawback of increasing development costs. Also, we are grateful for the development of a single-chip micro converter.
There are actually two types of LSIs, one for mass production and one for software development as mentioned above? There is a disadvantage that the table is too thick and the development cost and development period are further increased.

SUMMARY OF THE INVENTION In view of the above drawbacks, it is an object of the present invention to provide a single-chip microcomputer that shares a terminal connected to an external program memory and a terminal connected to an external peripheral device.

Single-chip microcombi according to the present invention.

- the central processing unit, the internal program memory, and the first. Second. The central processing unit t has a third input/output terminal, a first input terminal, and a signal line interconnecting these.
reads the program from the internal program memory and executes it. Second. The first mode uses the third input/output terminal as an input/output board, and the first mode uses the first input/output terminal as an address signal output terminal to an external program memory, and the second input/output terminal is used as its control signal output terminal. and a second mode in which the third input/output terminal is used as a data input terminal from an external program memory, and switching between the first and second modes is controlled by the first input terminal. It is characterized by being able to respond to signals.

An embodiment of the present invention will be described below with reference to FIG.

The CPU 100 controls the entire computer including the single computer and the computer. The first input/output terminal 201fl has an input/output port function and an address output function, the second input/output terminal 202 has an input/output port function and a control signal output function, and the third input/output terminal 204 has an input/output port function and an address output function. The input control signal 208 from the first input terminal 205, which has an input/output port function and a data input/output function, is input to the input/output terminals 201, 202, 204, . Gate 206 and multiplexer 20
Controls each part of 7. This signal 208 causes the CPU 10
0 reads and executes a program from the internal program memory 101 via the gate 206 and multiplexer 207, and uses the input/output terminals 201, 202, and 204 as normal port terminals, that is, terminals that can be connected to peripheral devices. , or input/output terminals 201, 202,
204 and the external program memory are connected to each other for switching to use.

Next, the operation of this single-chip microcomputer will be explained. By inputting a high level signal @1'' to the input terminal 205, this single unit/micro combination unit operates in the normal operating mode (first mode), reads the program from the internal program memory 101, and executes it. At the same time, the input/output terminals 201, 202, and 204t are used as normal input/output ports.
If you input "low level @0" to 5, this single search will occur.

Microcombi, internal program memory 101
Each port is used for connection with external memory without reading programs from the memory.

That is, an address signal is output from the input/output terminal 201,
The input/output terminal 202 outputs a control signal to the external memory, thereby performing data transfer with the external program memory via the input/output terminal 204t. Input/output terminals 201, 202, 2 by input/output terminal port operation command
When 04 functions as an input/output port for a peripheral device, the output data of the port and each input/output specification data are sent from the input/output terminal 204, and the control signal is sent to the input/output terminal 202.
Next, the configuration and operation of one of the input/output terminals 204 in FIG. 2 will be explained using the block diagram in FIG. 3.

Hereinafter, a mode in which the input/output terminal functions as an input/output port for a peripheral device will be referred to as a port mode, and a mode in which the input/output terminal functions as a port to an external memory will be referred to as an engineering mode.

The control signal 208 is a control signal for specifying the function of the input/output terminal 204-1.
03. ) Controls the opening and closing of Lance 7 Agate 312°313. Port F/F 304Fi, F/F that holds data output from input/output terminal 204-1 in port mode
It is. Mode F/F305IIi, F that holds input/output specification data of input/output terminal 204-1 in port mode
/F, this output controls transfer gates 307, 308. The CPUIGO sends a mode P/F write signal 309 that controls data writing to the mode F/F 305 and a port F/F2O3.
mode F/P write signal 310, which controls data writing on the input/output terminal 204-1;
Port control signal 315t becomes active 5III' during P write cycle and boat F/F write cycle
- generate each and control them.

Next, the operation will be explained. High level @ to input terminal 205
By inputting ``1'', the control signal 208 becomes high level ``1'', and as a result, the output signal 302
When Fi is not selected, a low level "1o" is output, and when the AND gate 303 is selected, the output state of the mode F/F 305 is output from the OR gate 314, and the transfer gate 313 is turned on. In this state, the input/output The terminal 204-1 operates in port mode. In this mode, port data on the I10 bus 106 is written to the Fi port F/F 304 under the control of the boat F/F write signal 31G. Mode F
The mode data on the I10 bus 106 is written under the control of the /F write signal 309. This mode P/F 30
When a high level 11" is written to F/F 5, a high level @1" is output from this F/F, and a high level 11" is similarly output from the OR gate 314. As a result,
Output cover 7, 306, transformer 7 agate 307 are ON
state, the transfer gate 308 is in the OFF state,
The contents of port F/P 304 are transferred) 31
Input/output terminal 204- via 3% output puffer 306t-
Output from 1. Also, the number of people terminal read signal 311
The period this signal is active, baud) F
The contents of /F 304 are output onto I10 bus 106 via transfer signal 307 and input cover 77316Th. Also, low level 1 is set to mode F/F 305.
o” is written, low level 10 is written from this F/P.
" is output, and the OR gate 314 similarly outputs the low level "IO". As a result, the
゜Transfer gate 307 is OFF, transformer 7
) 308 is in the ON state, and the boat torque is 30
4 is prohibited from being output from the boat terminal 204-1. In addition, in synchronization with the input/output terminal read signal 311, during the period when this signal is active, the input/output terminal 204-1
The above data is transferred to the I10 bus 106 via the input buffer 31, transfer gate 308, and input buffer 316.
is output above. Further, in FIG. 2, when the control signal flag is at a high level "1", the gate 206 is turned on, and the multiplexer 207 selects the output from the internal program memory 101 to output cptyio.

Transfer to.

As explained above, the high level @1 is input to the input terminal 205.
”, the CPU 100 connects to the input/output terminal 20.
1, 202, 203, and 204 function as normal boat terminals (boat mode), and the internal program memory 10
It reads and executes the program from 1 and operates as a normal single-chip microcombi.

Next, the operation when a low level "mθ" is input to the input terminal 205 will be explained.

The control signal 201j is at low level @0'', and the AND gate 303 is at low level 10'' in the unselected state.
is output, the AND gate 302 is in the selected state, and the vote control signal 315 is output from the OR gate 314. Further, the transfer gate 313 is turned off. As a result, only when the boat control signal 315 becomes active@1", the transformer 7 agate 312 is turned on, the OR gate 314 outputs a high level "1", and the output cover and foot 306 are turned on. Shi0 bus 10
Mode data or boat data on the input/output terminal 204-IK is outputted from the output buffer 306 via the transfer gate 312 to the input/output terminal 204-IK. At other times, the output buffer 306, ) Lance 7 access) 307 is OFF.
state, the transfer gate 308 is in the ON state, and the input/output terminal 204-! is in the ON state, and the input/output terminal 204-! The above data is input buffer 317
It is input into the I10 bus 106 via the transfer gate 308 and the input buffer 316. Furthermore, data on the internal data bus 111 IIcFi and the input/output terminal 204-1 can always be inputted via the input cover and foot 317. Also, in Figure 2, game) 206F
The iOFF state is entered, and the multiplexer 207 selects the input data transferred from the input/output terminal 204 and sends it to the CPU.
100, instructions or data in external memory t
- Inform the cPU 100.

an input/output terminal 201 waiting for a function to output an address signal;
The configuration of the input/output terminal 202 having a control signal output function is as follows.
Address signals and control signals are sent to the output cover and foot 306, respectively, to the transfer gate 31 instead of the I10 bus 106.
They are the same except that they are connected differently and the internal data bus 111 is removed. Therefore, both the input/output terminals 201 and 202 operate in the same manner as the input/output terminal 204 in the boat mode. Maku, emulator.

At the time of read cycle of the external program memory in the on mode, an address signal of the external program memory is output from the input/output terminal 201, and a control signal is output from the input/output terminal 202.

On the other hand, during a write cycle of output port data or input/output designation data for external input or input, the input/output terminal 201 sends an address signal to the external output or input, and the input/output terminal 202 outputs an address signal to it. Control signals are output respectively.

Now, when the CPU is operating in the emulation mode, each port is connected to an external memory, so simply speaking, it becomes impossible to connect the peripheral device 1 to the CPU. However, this inconvenience does not occur in the present invention as shown below, and this will be explained using the professional diagram of FIG.

This is an example of compensating for the port function for peripheral devices lost in the EMI mode by adding a simple circuit tube, and shows the configuration of one terminal. Single chip micro combination, -1400t! Since it is used in emulation mode, the chip's input/output terminals 204 are data bus terminals, input/output terminals, 201u address bus terminals, input/output terminals 202-1tj write signal terminals, and input/output terminals 202-2 are read terminals. Each functions as a signal terminal and is connected to an external memory.

Therefore, the port functions originally possessed by these input/output terminals are compensated for by the circuit inside the broken line. The input/output terminal 204-1 explained in FIG. 3 corresponds to one of the input/output terminals 204 in FIG. 2, and the boat function that this input/output terminal originally has is realized by the boat terminal 409 in FIG. Ru. The circuits within this broken line are required as many as the number of boat terminals used as address bus, data bus, read signal, and write signal terminals, but they may all have the same circuit configuration.

Program memory 405 is an external memory that stores programs executed by the single-chip microcomputer 400.
0tit data bus 406. address bus 407. Under the control of lead No. 1 408, the external device receives the program from the program memory 405 and executes it. port latch 41
0 holds the data output from the port terminal 409, and has the same function as the port F/F 304 in FIG.

The mode latch 411 holds the input/output data of the boat terminal 4090, and the output data of this latch controls the output buffer 420, the input cover, and the input/output data of the input port 414415. Further, this latch has a function similar to that of the mode F/F 305 in FIG.
This control signal produces a boat terminal read signal 421t which controls the input/output terminal read signal 3 in FIG.
Same work as u! +? do. AND gate 41f generates an address signal for boat latch 41 (l) on address bus 407 and a boat latch write signal 422 that controls writing of port data on data bus 406 from write signal 419 to port latch 410. Gate 418 is connected to address I (Modra on
11 and a mode latch write signal 423 that controls the write sound of mode data on the data bus 406 from the write signal 419 to the mode latch 411.
and create.

Next, the operation will be explained with reference to the tie construction diagrams of FIGS. 5, 6, 7N, and 8. First, the operation of a read cycle for reading a program from the external program memory 405 will be explained. The single-chip, micro-combi, and 400 outputs an address signal for the program memory 405 on the address bus 407 at the timing t500, and then becomes active @0' at the timing of the read signal 408''t-t5θl.Program The memory outputs data onto the data bus 406 from this timing t501, and the single-chip microcomputer 400
In synchronization with the rising timing of the Ready word 408 of the Fit 502, this output data is taken in from the input/output terminal 204 functioning as a data bus terminal. The write cycle operation 1ta6 is to write the mode data to the 0th order mode controller and the driver 411. Explain using. The single-chip, micro-combi, and 400 output the address signal of the mode latch 411 on the address bus 407 at timing t600, and the port control signal 31 at the same timing.
5t active@1'' and outputs mode data from the input/output terminal 204.

Subsequently, between t601 and t602 when the mode F/F write signal 309 becomes active @1'', the write signal 4
19 becomes active @0” and write signal 4 of t602
19 rises, the mode latch write signal 423 falls, and at this timing, the mode data on the data bus 406 is written into the mode latch 411.

Next, the write cycle operation for writing board data to the port latch 410 will be explained using FIG. The single-chip, micro-combi, and port 400 send the address signal of the portra and chi 410 on the address bus 407 at timing t700, and the port control signal 3 at the same timing.
1st-active@1” and outputs port data from the input/output terminal 204.

Then, the F/F write signal 310 becomes active@
1” from t701 to t702, the write signal 41
9 becomes active @l Og, and the port latch write signal a falls in synchronization with the timing at which the write signal 419 rises at t702, and the mode data of the data bus king is written to the port latch 410 at this timing. When the high level 11'' is latched in the mode controller 411, the output buffer 420 is in the ON state, and the data loaded into the port latch 410 is outputted to the port terminal 409 via the output buffer 420. When the low level @IO'' is latched in the mode latch 411, the output cover 420 is in the OFF state, and the data that is input to the port 410 is not output to the port terminal 409.

Next, the operation of the read cycle of the boat will be explained by referring to the timing diagram of FIG. A high level "1" is set in the mode latch 411, and the checked W# is the AND gate 4.
13 is in the selected state and the AND gate 412 is in the non-selected state, and when it is deviated, the AND gate 412 is in the selected state and the 7yF gate 413 is in the non-selected state.

Port latch 4 is applied to the single-chip, micro-combi, and data 400fl address bus 407 at the timing of t800.
Outputs 10 address signals. Then from t801 to t
During t802, the input/output terminal read signal 311 is made active ``1'', and from t8 (11 to t802), the read signal 408t is made active 10'.As a result, the port terminal read signal 421 becomes active @1'', and synchronized with this. When the high level @1'' is latched in the mode controller 411, the controller 413 is selected, the input buffer 415 is turned on, and the contents of the port latch 410 are output onto the data bus 406. ,Also,
When the mode latch 411 is at a low level @0'', the AND gate 412 is selected and the input buffer 414 is turned on and the data on the port terminal 409 is output onto the data bus 406. Single-chip microphone vs. core!--The data bus 400 generates the read signal 40B at timing t802 and releases the port terminal read signal 421.Synchronizing with this, the data bus 40
6. The data above is single-chip, microcomputer, -ta 4
It is taken inside 000.

As explained above, the input terminal 205 has a low level "0".
By inputting “, the pcPU100tj input/output terminal 20
Using external circuits 1, 202, and 204, the external program 'tfif' can be extracted from the program memory and executed, and the board functions of input/output terminals 201, 202, and 204 can be completely realized with external circuits. . Therefore, according to the present invention, a mass-produced single-chip microcomputer can be used as an evaluation chip as it is, and there is no need to make a special evaluation chip.

The present invention has a great advantage in the development of a single-chip microcombiner, in that it does not require the development of an evaluation chip, and the development cost and development period can be significantly reduced. Furthermore, it is not necessary to use an EV chip specially developed for software development, and it is possible to provide an extremely inexpensive EV chip.

In addition, if the control signal t-cptr is generated from the terminal 205, or if it is switched to "1" only during data transfer with a peripheral device in the Emirates mode, the fourth The external circuit indicated by the broken line in the figure can also be omitted. It is clear that the present invention is applicable to all cases where a terminal is used for multiple functions, that is, when it is used as a shared terminal.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional EV chip for single-chip microcombi processor software development; The figure is a detailed circuit diagram of the input/output terminal part of the single-chip microcombi in Figure 2, and Figure 4 is the circuit diagram of a system using the single-chip microphone a'': 1 amp, -7 in Figure 2. , Figure 5 is a timing diagram of the read cycle of the external programmable memory, Figure 6 is a timing diagram of the write cycle of the external mode latch for ports, and Figure 7 is the timing diagram of the external mode latch for ports. Timing diagram of write cycle. Figure 8 is a timing diagram of read cycle of external ports. 100...CPU, 101...Program memory, 102, 103, 104.105. ...
・-Port, 106...I10 bus, 1o7・
River...Address bus terminal, 10g...Internal address bus, 1o9 River...Read signal terminal, 11o...
・River/Data bus terminal, 111... Internal data bus, 201, 202. 202-1, 202-2, 20
4,204.1・River...Input/output terminal, 205...
・Input terminal, 2o6...Gate, 307.30
8,312,313...Transfer gate,
207・River... Multiplexer, 208... Control signal, 302, 303, 412° 413.4
16,417,418...antogame), 30
4...Port F/F, 305...Mode F/F, 306,420...Output cover, F,
...baud) F/F, write signal, 311...
・I/O terminal read signal, 314...OR gate, 315...Port control signal, 316,3
17゜414.415...Inner cover, Fa, 40
0...Single branch, micro combination, -ta,
405... External program memory, 406...
...Data bus, 407...Address bus, 408...Read signal, 410...
・Port latch, 411...Mode latch, 4
19...Write signal, 421...Boat terminal read signal, 422...Port latch write signal, 423...MODRA, CH write signal, Figure 1 Figure 2 4ρO Figure 15 Start Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] In a single-chip microcombi device having a central processing unit and a memory input/output board therein, a first control means for controlling said input/output board to perform data transfer with an external peripheral device; 1. A single-chip microcombinator comprising second control means for controlling the input/output board to perform data transfer with an external memory.