JPH0254341A - Testing method for digital signal processor - Google Patents

Abstract

PURPOSE:To test a digital signal processor with no extra circuit added to the processor by forming a 1st storage circuit with the 3rd and 4th storage means, storing the input signal data in time division into the 3rd and 4th means and then reading out these stored data. CONSTITUTION:A 1st storage circuit 220 of a digital signal processor DSP consists of the 3rd and 4th storage means 270 and 280. The input test signal data are stored in time division into both means 270 and 280 via a selection circuit 210. Then the data read out of the means 270 and 280 of the circuit 220 are read out to a 2nd storage circuit 230 and processed by a decoder DEC 240, tested. Then the data read via an external memory data bus are written in time division into a higher rank IRU 27 and a lower rank IRL 28 via a selection circuit SEL 21 which is switched to the test side. The address of an IR 23 is obtained from the data stored temporarily in the IRU 27 and the IRL 28, and a control signal is outputted via the DEC 24.

Description

[Detailed Description of the Invention] [Summary] Regarding a testing method for digital signal processors that are widely used in fields that require high-speed calculations such as high-efficiency speech encoding, this method does not require the addition of extra circuits for the above-mentioned tests. The purpose of the present invention is to provide a sequence control unit for controlling the program sequence of a digital signal processor having a random access memory, the sequence control unit for controlling the program sequence of a digital signal processor having a random access memory, which a selection circuit that selects one of the input signals based on a control signal; and a first circuit that is connected to the selection circuit, temporarily stores input signal data consisting of a predetermined number of points, and determines an address for storing the data in a random access memory. a second memory circuit that is connected to the first memory circuit and reads and stores signal data stored in the first memory circuit using a control signal; and a second memory circuit that is connected to the first and second memory circuits. , and a decoder for reading out signal data stored in first and second storage circuits and decoding the contents of the signal data, wherein the first storage circuit is configured to include third and fourth storage means, The input signal data is stored in the third and fourth storage means in a time-sharing manner, and the stored signal data is read from the third and fourth storage means.

[Industrial application field]

The present invention is a digital signal processor (
The present invention relates to improvements in testing methods for DSP (hereinafter referred to as DSP).

At this time, there is a need for a DSP testing method that does not require the addition of an extra circuit for the above testing.

[Conventional technology]

FIG. 4 is a block diagram showing the configuration of an example DSP.

FIG. 5 is a block diagram showing the configuration of an example of a sequence control section.

FIG. 6 is a block diagram showing an example of a DSP test circuit.

FIG. 7 is a block diagram showing the configuration of a conventional circuit.

FIG. 8 is a time chart showing the operation of the conventional example.

Widely used in fields that require high-speed calculations such as high-efficiency speech encoding.
An LSI DSP is used. On the other hand, due to the demand for lower power consumption and lower costs, it is desired to reduce the number of external components and the number of input/output terminals of LSIs as much as possible. For this reason, the ROM for program storage is
Built-in mask ROM that cannot be written to later.
The data terminal for reading instructions has been removed.

However, for DSP shipping tests and failure diagnosis, there are cases where it is desired to input and execute commands from the outside.

In FIG. 5, which shows the configuration of the sequence control unit 1 in the DSP 6 shown in FIG.
The interface for OM13 has 16 outputs and 32 inputs.
Requires several terminals. Considering the miniaturization and low power consumption of the LSI package, it is desirable to have a built-in ROH for instructions.

If the interface terminal of the extended instruction ROM 13 is removed, instructions cannot be input from the outside, so an instruction buffer (hereinafter referred to as IB) 14 shown in FIG. 5 is added. lB
Commands are input to 14 from an external memory bus.

A DSP having such a configuration is tested using the circuit shown in FIG. The "1" of the control signal "lN5T" is changed to "0" through the gate 15 and inputted to the external instruction RAM 18, and the instruction is read out and sent to the DSP via the data bus MD.
Enter 6. In addition, the control signal "XMS" of "1" is used to access the external data RAM 17 via the gate 16 to read the data, and the data is read out from the data RAM 17 via the data bus MD.
Enter 6. After various arithmetic processing is performed by the DSP 6, the test results are obtained by branching from between the data buses.

As shown in FIG. 8, when the control signal UXL is "O", the data read via the external memory data bus MD is stored in the upper word instruction buffer IB as shown in FIG.
For example, 16 bits are time-divisionally input to the IBL 20, which is an instruction buffer for the lower word when [IXL is "1", and are temporarily stored.

The data stored at the above-mentioned time is read out by a control signal and inputted to a selection circuit (hereinafter referred to as SEL) 21. Then, at SEL 21, it is switched to the test side and output as 32-bit test data.

The above data is transferred from SEL 21 to the instruction register (hereinafter referred to as IR).
22). In lR22,
An address for storing data in the RAM 3 shown in FIG. 4 is calculated in advance. This result is sent to a decoder (hereinafter referred to as DEC).
) 24, and after one cycle delay shown in FIG. 8, it is input to lR23 and temporarily stored.

In other words, IR22 and IR23 perform pipeline operations.

The data temporarily stored in lR23 is read out by the control signal from DEC24 and inputted to DEC24, and
The contents are decoded separately from the data input from 2,
Various control instructions are created.

Note that normally, not during testing, the program counter (hereinafter referred to as PC) 25 shown in FIG. 7 outputs an instruction address, and data corresponding to this address is stored in the mask ROM.
26 and input to SEL 21.

Below, SEI, 21 is switched to the normal side and lR2
2. The same operation as above is performed with IR23 and DEC24.

[Problem to be solved by the invention]

However, the above test method has the problem of requiring an extra instruction buffer, resulting in high costs.

Therefore, an object of the present invention is to provide a DSP testing method that does not require the addition of extra circuitry for the above testing.

[Means to solve the problem]

The above problem is solved by the circuit configuration shown in FIG.

That is, in FIG. 1, there is shown a sequence control unit that controls the program sequence of a digital signal processor having a random access memory, which inputs test signal data and data representing a predetermined program command, and selects one of them using a control signal. a first storage circuit connected to the selection circuit for temporarily storing input signal data consisting of a predetermined number of bits and determining an address for storing the data in a random access memory; A second memory circuit 230 is connected to the circuit and reads and stores signal data stored in the first memory circuit using a control signal;
and a decoder 240 for reading signal data stored in a second storage circuit and decoding the contents of the signal data, the first storage circuit is configured to include third and fourth storage means 270 and 280. , the input signal data is stored in the third and fourth storage means in a time-sharing manner, and the stored signal data is read from the third and fourth storage means.

[For production]

In FIG. 1, the first memory circuit 220 is connected to the third and fourth memory circuits.
The input signal data is stored in the third and fourth storage means in a time-sharing manner,
The stored signal data is read from the third and fourth storage means.

As a result, it is possible to eliminate the need to add extra circuits for testing digital signal processors.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a circuit according to an embodiment of the present invention.

FIG. 3 is a time chart explaining the operation of the embodiment.

The same reference numerals indicate the same objects throughout the figures.

In Fig. 2, the difference from the conventional example is the IB shown in Fig. 7.
The U 19 and IBL 20 are removed, and the IR 22 is divided into an IRU 27 on the upper word side and an IRL 28 on the lower word side. For example, 1 entered in SEL 21.
Test data in 6-bit units IRU 27 and IRL
28 in a time-sharing manner.

As shown in Figure 3, the data read through the external memory data bus is transferred to the SE switched to the test side.
The signals are first input to the IRtl 27 via the L 21, and then similarly input to the IRL 28 in the next cycle, where they are temporarily stored. The IRU 27 and IRL 28 calculate an address for storing the previously stored data in the RAM. Input this result to the DEC24, and
It is inputted to lR23 with a delay of one cycle and is stored at - hours.

The following operation in the DEC 24 is similar to that described in the prior art.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to eliminate the need to add an extra circuit for testing a DSP.

In the figure 270 is a third storage means; 280 is the fourth storage means shows.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block diagram showing the circuit configuration of an embodiment of the invention, Fig. 3 is a time chart explaining the operation of the embodiment, and Fig. 4 is an example of a DSP. FIG. 5 is a block diagram showing the configuration of an example sequence control section. FIG. 6 is a block diagram showing an example OSP test circuit. FIG. 7 is a block diagram showing the configuration of a conventional circuit. 8 are time charts for explaining the operation of the conventional example.・From L! 3 Ba's Ashari Eigyu 1 Warm / 1 - Chiro (7) Roasted] Rejuvenation of Spring Groove and Demonstration 7
``O-y 77 ya 2 bad time Jitsukata Kosuke/I/)ju n('f-also say H time ke V
Figure 4 shows the 5P mechanism p number, a rough diagram.
Figure L
7 prisoners

Claims (1)

[Scope of Claims] A sequence control unit for controlling a program sequence of a digital signal processor having a random access memory, which inputs test signal data and data representing a predetermined program command, and selects one of them using a control signal. a selection circuit (210) connected to the selection circuit;
Temporarily stores input signal data consisting of a predetermined number of bits,
a first storage circuit (220) determining an address for storing the data in the random access memory;
a second memory circuit (230) connected to the first memory circuit and reading out and storing signal data stored in the first memory circuit using a control signal; A decoder (
240), the first storage circuit is connected to third and fourth storage means (270,
280), input signal data is stored in the third and fourth storage means in a time-sharing manner, and the input signal data is stored in the third and fourth storage means in a time-sharing manner;
1. A test method for a digital signal processor, characterized in that signal data stored from a storage means is read out.